TW583675B - A split-gate flash memory cell array able to program data in bytes and erase - Google Patents

Abstract

A split-gate flash memory cell array having functions to program data in bytes and to erase is provided. In the first embodiment, every array element consists of a switch and memory cells forming a byte, and a local word line connecting all of the control gates of the memory cells in the byte. The memory cells belonging to the same row commonly share a source line, but the common source lines of the adjacent two rows are separated to avoid the punch-through disturb or reverse tunneling happening in the adjacent byte when one byte is proceeding data refresh. In the second embodiment, read R cell and program P cell is used to replace the single cell in the first embodiment. At this time, 2T memory cells of the adjacent rows commonly use a bit line through the R memory cell, and the P memory cells located in another row do not share the same bit line, and they are arranged alternatively. Or, the P cell in the 2T memory cells is adjusted to high threshold voltage to prevent the punch-through disturb or reverse tunneling problems of the adjacent bytes.

Description

583675 V. Description of the invention (1) Field of the invention: The present invention relates to an open flash memory cell array, in particular to an open flash memory cell array that can use a byte as a data access unit and its peripheral circuits. Background of the invention: The flash memory system is a brand new storage system with low power consumption, high access speed, and shock-resistant, mobile-resistant, high stability and other safe data access conditions. Information can be more efficiently stored ( blocks) to record (or eliminate) them, rather than as slowly as byte-wise sequential recording. In addition, once data is stored in flash memory, no power is needed to retain the data. Generally speaking, with the current technology, the stored data can be retained for at least ten years even after the power is turned off. This advantage has eclipsed other portable storage systems, so flash memory is extremely competitive compared to other storage media. Stance of a full tomorrow star. Not only digital cameras, notebook computers, handheld electronic notebooks, mobile phones and other electronic products, the demand for flash memory is inseparable.

583675 V. Description of the invention (2) CF (compact memory card) card, MMC (mu 11 i med i a memory card) card, MS (memory stick card) card or SMC (smart memory c a r d) card. These memory cards are often overwritten to update data. In other words, flash memory cells can not only provide data reading after data writing, but also often need to update data. Therefore, in addition to using blocks as the unit of data update, it is necessary to use bytes as the unit of data update. However, in the current open-memory cell array, since the two adjacent columns are mostly shared by the source and control the gates facing each other, when a byte is updated, it will affect the data content stored by the adjacent byte. A typical SST (Silicon Storage Technology Inc. flash memory product) array, as shown in Figure 1, cannot be erased in bytes. In the figure, it contains the memory cells of the odd and even columns adjacent to each other (only two adjacent memory cells are shown on the picture, instead of a complete one-byte X 8-bit array, that is, other The six memory cells are not shown, but of course they can also be lx 1 6 or lx 3 2 bits, depending on how many bits are in each byte. The four groups of adjacent bytes shown in Figure 1 ( byte) ll, 21, 12, 2 2. For these four groups of bytes, the odd and even columns share the source line (source 1 ine), and the word lines are the same word lines in the same column. When the word line When the voltage is increased and the source line is grounded, the data in the same column can be erased. If you want to update in bytes, in addition to cutting the word line in bytes, each byte Need to have their own separate switches.

Page 5 583675 V. Description of the invention (3) Even so, all memory cells in the same row in the array share the bit line. In addition, the adjacent two columns of memory cells also share the source line. Therefore, simply cutting the word line in bytes is not enough. Otherwise, when the memory cells are programmed, or data is erased, or read, the conditions set by the above actions are not the same, so there will be different degrees of program disturb. For example, taking the two-byte tuples 1 1 and 2 1 as an example, the first digit of this tuple 1 1 is recorded as 1 1-1 and the first digit of byte 2 1 is recorded as 2 1-1 The bit line BL is a total of his 7 bits. For example, 1 1-2 corresponds to 2 and 2 and other 1 1-3 to 1 1-8 and 2 1-3 to 2 and 8 (not shown). Second, 8 bits and bytes of byte 1 1 The 8 bits of 21 are all common source lines. Only word lines are not shared. Therefore, when the byte 11 is programmed, the regional word line applies a voltage of 1.8 volts, and the bit lines 1 1 -1 and 1 1-2 apply BL 0.6 and 0.6 The voltage of the common source line SL is, for example, 10 volts. At this time, it is inevitable that the byte 21 will have a so-called punch through interference (punch through d i s t urb)). That is, when byte 1 1 is stylized, byte 2 1 is also stylized at the same time, but because the word line of byte 2 1 is 0 volts, each bit of byte 2 1 is weaker. Stylized. Instead, it should be kept in the erased state and turned into a state where the floating gate contains electrons. Another byte 2 2 farther away from the byte 1 1 also has the problem of so-called reverse tunneling (r e v e r s e t u η n e 1 i n g). I.e. bytes 2 2 are not

Page 6 583675 V. Description of the invention (4) The VCC voltage is applied to the bit line. In addition, the word line is 0 volts, and the common source line S L = 10 volts. At this time, the floating gate of the memory cell of the bit line 22 will be combined with a large voltage of 10 volts. Therefore, the electrons enter the floating gate from the control gate, and similarly, the byte 22 is programmed. The bytes 11 and 12 are shared by the source line SL and the word line WL. In this case, the situation of interference is generally referred to as the interference programmed as l (program FF). The word line WL also has 1.8 volts in common, and the source is 10 V, but the bit line is VCC, so the channel under the memory cell may be slightly opened, similar to the penetrating interference described above. Therefore, the above interference may be different due to conditions such as a common bit line, a common word line, or a common source line. This would run counter to the basic premise that one byte cannot be disturbed when other bytes are not programmed. To solve the above interference problem, unless the source lines of two adjacent columns are also separated, the common source line relationship between the bytes and the bytes in the same column is also broken. However, this will occupy a large area of the chip by opening and setting up the respective controlled switches. Therefore, the method of SST is to refer to Figure 2. All the memory cells in two adjacent columns still share the source line, and the bit lines of the memory cells in two adjacent rows are staggered from each other. Bytes 1 1 use BL1 to BL8 bit line (28 is drain contact window). The byte 21 uses the BL1 'to BL8' bit lines (reference numeral 2 8 'is a drain contact window). That is, the nearest neighbor of the same memory cell is

583675 V. Description of the invention (5) Dummy memory cell (dummy ce 1 1) (without making contact with the drain electrode) to reduce interference. As shown in the schematic diagram of Figure two. In view of this, the present invention will provide a new flash memory cell array architecture to solve the above-mentioned problems to be overcome. Summary of the Invention: The main object of the present invention is to provide a flash memory cell array that can use byte data as a basic data update unit. Another object of the present invention is to provide a flash memory cell array that uses byte data as a basic data update unit, and to provide a neighboring byte to be protected from the interference of the updated byte. . The present invention discloses a split flash memory cell array that can program and erase byte data. In the first embodiment, each array element includes the number of memory cells and a switch that form a byte, and has a switch. The area word line connects the control gates of all memory cells of the byte group. Among them, all memory cells in the same row of the array element share a source line, but the common source lines of two adjacent columns are independent to prevent When a byte is updated with data, the adjacent bytes generate the problem of penetration interference or reverse tunneling interference. In addition, in order to prevent another byte of the same source line from being affected by the update of the adjacent byte data , And the byte to be updated and the byte not to be updated are first written into the memory cell buffer page, and then the byte data to be updated is written from the memory cell buffer page.

583675 V. Description of the invention (6) Into the memory cell, finally, all the data in the memory cell and the memory cell buffer page are verified and compared. If it is found that the previously unupdated data has been disturbed, it is rewritten from the memory cell buffer page. In the second implementation of the present invention, the common source lines of the two adjacent columns of parity are not monologous, but a single memory cell is replaced with a 2 T memory cell. The so-called 2 T memory cell refers to two memory cells connected by a floating gate, an R memory cell that provides a reading function and a stylized P memory cell. However, in order to prevent P memory cells in two adjacent columns from sharing bit lines, the problem of penetration interference or reverse tunneling interference is avoided. The corresponding relationship between the two adjacent columns is that the odd columns are arranged in order with P memory cells, R memory cells, and D memory cells. The even-numbered columns are D memory cells, R memory cells, and P memory cells, which are arranged in order. D memory cells are pseudo memory cells (memory cells whose drain is not connected to the bit line). The third embodiment of the present invention is similar to the second embodiment of the present invention. The D memory cell is changed to an R memory cell, so that the unit occupied by the R memory cell is doubled, and the area of the silicon substrate is not wasted. The fourth implementation of the present invention is similar to the second implementation of the present invention and also uses 2 T memory cells instead of 1 T memory cells of the first embodiment, but the P memory cells and the R memory cells are well opened, but the P memory cells are adjusted to high The initial voltage is used to prevent the problem of penetrating interference or reverse tunneling interference between adjacent bytes. Since the reading is in the R memory cell, the high starting voltage of the P memory cell will not affect the reading data of the R memory cell.

Page 583675 5. Description of the invention (7) In the second, third and fourth embodiments described above, as in the first embodiment, the bytes to be updated and the bytes not to be updated are written. In the memory cell buffer page, the byte data to be updated is written into the memory cell from the memory cell buffer page, and finally, all the data in the memory cell and the memory cell buffer page are verified and compared. If it is found that the previously unupdated data has been disturbed, it will be rewritten from the memory cell buffer page. To ensure that all information is correct. Details: In view of the fact that the typical open flash memory array cannot use bytes as the access unit, however, having this function is a necessary function to save data update time. However, as described in the background of the invention, when a byte is programmed, other adjacent bytes or a shared bit line (bit 1 i ne) or a shared word line (word 1 i ne) that are not programmed are adjacent. ) Or shared source line (source 1 i ne) and other conditions are different. Therefore, when the memory cell is programmed, or data is erased, or read, the conditions set by the above actions are different, so the There are different levels of interference problems. These interferences include penetrating interference or reverse tunneling and program FF interference. Therefore, in order to achieve the programming or data erasure of a single byte without affecting the purpose of changing the data content of other bytes. Traditional SST memory cell arrays must be modified. According to the method of the present invention, please refer to FIG. 3. First, the bytes and bits

Page 10 583675 V. Description of the invention (8) The sub-lines between the groups must be cut. Therefore, as shown in the figure, each byte has an individual ^ Γ switch HV connected to the local word line LWL (local word 1 ine), and is erased with the data of the 3 组 2 l wide group. All switches are connected again-wide area word line GWL (glObal worfi; ^, mη a-1 1 ne), so that it can also be erased in a whole row. = '(Two "le two;:, the group switch HV is controlled by the same signal EN / ENB to tmm drbie) ° the word line of each area ^ there are-every bit line is cut or isolated), as shown in the figure ^ The common source of the series and even series is the penetrating interference of the second type and the reverse type of the second type is perfect. So the 'number-u' for the odd-numbered byte u stylized u4 can be solved. Because GWL2 Both the source line SL2 and the source line SL2 are 0 volts from the bit line of the iron ^ 2 series.…, There will be no first and second types, but because the bytes 1 1 and 12 are still this The three kinds of field-programmed interferences will still exist, so use the source line SL1 ', so cut the common source line SL1 of the second group, add two respectively; The space for each column is limited. Fortunately, the inventor Researching on the Su switch, #there is too much and the wave condition is the less serious of the above three kinds of interference. The second kind of interference will no longer divide the tuples of each column into two; for now, the present invention will Method for remedy. For example, when stylized, the times: = moth and other data are used to verify the data. The third kind of interference was not found in the society; Ke also performed data verification 'times. After the data was updated, the data was checked :; beam :: shell :; and then re-programmed-the condition exists, the data is updated again. Right miscellaneous Three types of interference

583675 V. Description of the invention (9) Suppose that a memory cell page has 64 bytes, 30 bytes need to be updated, and the other 34 bytes do not need to be updated. At this time, these 6 4 For each byte, the data to be updated is first written into a page buffer (pagebuffer) which is also 64 bytes. The unupdated 3 or 4 byte data is also written in the page buffer. Then write 30 bytes of the memory cell page to be updated from the page buffer. The 3 or 4 bytes that are not updated are left in the page buffer and are not written to the memory cell. Therefore, after the 30-byte data of the memory cell page is updated, the data verification is performed immediately. The updated 30-byte data in the memory cell page and the 34-byte data that is not updated are all page buffered. Compare the data in the area. If they are the same, it means that there is no interference, and the process ends. If the updated data is incorrect after verification, it must be reprogrammed. Another situation is that after the 30 bytes of updated data in the memory cell page are verified, the result is correct, but if the data in the memory cell page is not updated and the result is incorrect, it means that the memory cell page has 3 4 The bytes have been disturbed, so the data of the 34 bytes in the page buffer is written into the memory cell page. The updated information is no longer written. Generally, for a qualified memory cell page, the newly updated data will not be disturbed by the writing of neighboring memory cells, so there will be no problem of interaction. Finally, verify the memory cell page data again as described above. Please refer to the chart in Figure 4. The graph shows the interference level when the memory cells of 0.3 5 / z m are programmed with 10 2 (1 k) bits. The curve in the figure is the comparison between the number of programmed times and the memory cell current when the programming time is 10 seconds. In addition to showing the second type of interference (reverse tunneling; as shown in curve 1 6 0)

Page 12 583675 V. Explanation of the invention (ίο) It is more serious than the third type of interference (programmed as FF; such as curve 1 50). It also shows the fact that the newly written data will pass through (50/2 ms / Time), that is, the memory cell current will decrease significantly after 2 5 0 0 0 = 2 5 k times. The common source lines of the odd and even columns can be cut or isolated to avoid the interference of the first and second types. Please refer to the diagram in Figure 5. In Figure 5, two memory cells 5 1 1 R (the memory cell is provided for reading) and 5 1 1 P (the memory cell is provided for stylization) are connected together as a single floating gate 5 1 1 F. Memory cell 5 1 1, two even cells 5 2 1 P, 5 2 1 R floating gate 5 2 1 F are connected together as a memory cell 2 T memory cell 5 2 1. The memory cell 5 1 1 P and the memory cell 5 2 1 P are staggered so that when programmed, the bit lines programmed by the two rows of memory cells are not on the same bit line, and when read, they are the same bit. Yuan line. 2 The advantage of T memory cells is that they can increase the tolerance of the number of cycles of memory cells. Please refer to another Taiwan application filed by the applicant, with application number 0 9 1 1 1 0 4 4 6 and the invention name is "lifting cycle" The structure of flash memory cell and its programming method of the service life "are presented for reference. This will also avoid the problem of the first type of penetrating interference. According to Figure 5-2, the layout of the T memory cell. It is shown that 2 T memory cells 5 1 1 and 5 2 1 each have an inactive memory cell 5 1 1 D and 5 1 2 D. In order to make full use of any area allowed on the layout of Shi Xijing. The layout of Figure 5 can also be made as shown in Figure 6. Create a larger memory cell and a smaller memory cell, and then combine the floating gates of the large and small memory cells together, such as 3 T Memory cells, large memory cells are twice as large as small memory cells. As shown in Figure 6

Page 13 583675 V. Description of the invention (11) The odd-numbered rows of memory cells and the even-numbered rows of memory cells still share the source line, but as shown in Figure 5, the smaller memory cell 5 1 1 P serves as the main stylized function. The large memory cell 5 1 2 R is responsible for providing data reading functions.

Another embodiment designed to prevent the first type of penetrating interference according to the method of the present invention is that if the 2 T memory cells shown in FIG. 7 are used, three memory cells need not be staggered as shown in FIG. 5 or FIG. Area, the method of this embodiment is to use the channel-specific anti-penetration ion implantation technology to adopt two channels of adjacent 2 T memory cells to provide stylized memory cells to increase the starting voltage. There will be no problems with penetrating interference. Since the reading of the data of the memory cell is provided by another memory cell in the 2 T memory cell which is responsible for reading, there is no problem of reducing the current. Although the above 2 T memory cells will make the horizontal direction (2 X as shown in the figure, the length becomes larger, that is, 2 times the length of the memory cells or 3 X as shown in the figure, that is, 3 times the length of the memory cells, but the vertical length is unchanged ( That is, as shown in the figure, compared with the case where two adjacent rows of memory cells do not share the source, the vertical length needs to be increased. Therefore, the 2T memory cell design according to the present invention (Figures 5 to 7) will not increase. Extra layout area.

Please note that in the above 2 T memory cell, as in the first embodiment, the bytes to be updated and the bytes not to be updated are written into the memory cell buffer page, and the self-memory buffer page will be updated. The byte data is written into the memory cell, and finally, all the data in the memory cell and the memory cell buffer page check are performed.

Page 14 583675 V. Description of the invention (12) Certificate comparison. If it is found that the previously unupdated data has been disturbed, it will be rewritten from the memory buffer page. To ensure the accuracy of all information. From the above, it can be known that the switching memory cell of the present invention has the following advantages: 1. Each byte is added with a word line switch, and the source line is also added with a switch. In addition, even and odd columns are separated. Therefore, as long as each electrode is properly given a voltage, data can be read, programmed, and erased from the selected byte.

2 · When operating on any byte, adjacent bytes will not have data to prevent mutual interference. The above description uses the preferred embodiment to describe the present invention in detail, rather than limiting the scope of the invention, and it is well known Those skilled in the art can understand that making appropriate changes and adjustments will still not lose the essence of the present invention, nor depart from the spirit and scope of the present invention.

Page 15 583675 Schematic description Figure 1 is a schematic diagram of a traditional flash memory cell array. Figure 2 is a schematic diagram of a memory cell array proposed by SST in order to prevent reverse tunneling interference and penetration interference of traditional flash memory cells. Figure 3 is a schematic diagram of a flash memory cell designed according to the method of the present invention. The two adjacent columns have independent sources, and each byte word line is controlled by a switch. Figure 4 is a schematic diagram comparing the accumulation of the memory cell array in Figure 3 at the time of data update and the change in the memory cell current due to interference. FIG. 5 is a flash memory cell designed according to the method of the present invention. The two adjacent columns of the source are still shared, but each bit memory cell is a 2 T memory cell and contains a dummy memory cell so that the adjacent column P The memory cells are staggered to solve the problem of penetrating interference between two adjacent columns. In addition, each byte word line is a schematic diagram of a memory cell array controlled by a switch. Figure 6 is a flash memory cell designed according to the method of the present invention. The two adjacent columns of the source are still shared, but each bit memory cell uses 2 T memory cells, and the R memory cell is larger and the P memory cell is smaller. In order to solve the problem of penetrating interference between two adjacent columns, each byte word line is a schematic diagram of a memory cell array controlled by a switch. Figure 7 is a flash memory cell designed according to the method of the present invention. The two adjacent columns of the source are still shared, but each bit memory cell uses a 2 T memory cell. The starting voltage of the P memory cell is increased to solve the adjacent two cells. Schematic diagram of memory cell array with column penetration problem and each byte word line controlled by a switch. Figure number description:

Page 16 583675 Schematic description of byte memory cell 1 1 512P, 512R, 512D source line bit line wide area word line area word line odd column bit line even column bit line HV switch control signal drain contact

12, 2b 22, 511P, 511R, 511D 521R SL2 521P SU, BL GWL LWL BL1, BL2 BL1 ’, BL2, EN / ENB 28

521D

Page 17

Claims (1)

583675 VI. Scope of patent application 1 · A flash memory cell array that can program and erase byte data, including at least: multiple array elements, each element including the number of memory cells and A switch with a regional word line connecting the control gates of all memory cells of the byte group, wherein all memory cells in the same row of array elements share a source line; and The output terminal of each switch is connected to each regional word line, and the input terminals of switches of all elements in the same column are connected to a wide-area word line (g 1 〇ba 1 w 〇rd 1 i ne) signal input terminal in the same row. The control terminals of the switches of all elements are connected to the same control signal terminal. 2. The split flash memory cell array as described in item 1 of the scope of the patent application, wherein the odd and even columns in the above-mentioned array elements do not share source lines to prevent two adjacent rows of memory cells from sharing source lines. And bit line will cause the problem of penetration interference. 3. The open flash memory cell array as described in item 1 of the scope of patent application, wherein each of the above elements has a memory cell number of one of lx 8, lx 16, or lx 3 2. 4. The open flash memory cell array described in item 1 of the scope of patent application, wherein the above open relationship is used to achieve that each byte can independently control the operating voltage. Page 583675 Page 6 6. Patent application scope 5 · The split flash memory cell array described in item 1 of the patent application scope, where the above-mentioned array elements are updated with the data of the bytes to be updated first and The unupdated byte data is written into a memory cell buffer page at the same time, and then the byte data to be updated is written into the byte memory cell to be updated in the array element. After the reminiscence of I5, the new and updated "materials, materials, element B, element 5 of the fifth element in the rufanfanyuan ruj rnj ί", the application for the special group as stated above on the CD, and their reassurance, etc. March. The surface interference is completely unreliable. The group is not listed. The group of funds and the group of resources are not in the line. The page is not recognized. It has been identified as f U. V. Cell It. V Γ ^ Gate Bank 7 If the item issued by f is described in f, if the result of b is the conclusion of the certificate, the result of the test will be as follows: 7. The unit of the Chinese fund. The new page is more advanced within the new year, and the new page is more aggressive. The cell is not recalled. The original record is written in the original element. The original array will be entered, and it will disturb the Xingan weight. Erasing and chemical engineering materials group: Yuan-containing bit packs can be reduced to one, 8 columns meaning Yijigukou = mouth of the group, each bit of the byte group into the structure containing the connected envelope prime character field Each area in a region is well-equipped, and the arrays are opened and counted, and the number of cell sources T 2 is used in conjunction with the common cell phase. In this column, the numbers in the column are even, and the number of column poles is unique and controlled. The cells in the column are listed in the same line of the word field area 1 per connection-\ HC terminal output 45— of the open 1 and each; the line pole Page 19 583675 6. The input terminal of the switch with elements in the scope of patent application is connected to a global word 1 i ne signal input terminal, and the control terminals of the switches of all elements in the same row are connected to the same control signal terminal. . 9. The gated flash memory cell array as described in item 8 of the scope of the patent application, wherein the 2 T memory cell connected to the floating gate includes a P memory cell dedicated for programming and a P memory cell for providing R memory cell for reading data. 10. The split flash memory cell array described in item 9 of the scope of the patent application, wherein the P memory cells in the 2 T memory cells in the two adjacent columns and the same row share a bit line, but the R memory cell is Each has its own bit line to achieve the problem of allowing adjacent column memory cells to share the source line but preventing penetration interference. 1 1. The split flash memory cell array as described in item 9 of the scope of the patent application, wherein the 2 T memory cells in the two adjacent rows and the same row are such that the 2 T memory cells in the odd row are D memory cells, The R memory cell and the P memory cell are arranged, and the even numbered column corresponds to the P memory cell, the R memory cell, and the D memory cell, of which the D memory cell is a dummy cell 0 1 2. The split flash memory cell array, wherein the 2 T memory cells connected to the floating gates described above include-a unit-sized p-memory cell and one or two unit-sized read-only cells for reading. Get the R memory cell of the data. Page 583675 6. Application for patent scope 1 3. The split flash memory cell array as described in item 11 of the patent application scope, wherein the 2T memory cell connected to the floating gate is an odd 2T The memory cells are arranged in P memory cells and R memory cells and the even number of 2 T memory cells correspond to R memory cells and P memory cells so that the positions of P memory cells are staggered without sharing bit lines, and R memory cells each have a unit Adjacent but can share a bit line. 1 4. The split flash memory cell array according to item 9 of the scope of the patent application, wherein in the 2 T memory cell connected to the floating gate, the starting voltage of the channel of the P memory cell is lower than that of the R memory cell. The starting voltage of the channel is high to achieve the problem of allowing the adjacent column memory cells to share the source line but preventing penetration interference. 15. The split flash memory cell array as described in item 14 of the scope of the patent application, wherein the starting voltage of the channel of the P memory cell is higher than the starting voltage of the channel of the R memory cell in the P memory cell. The channel position is implanted with anti-penetration ion implantation, and impurity ions are implanted to increase the initial voltage. 16. The gated flash memory cell array as described in item 8 of the scope of the patent application, wherein each of the above elements has a memory cell number of 1 × 8. 1 7. The open flash memory cell array as described in item 8 of the scope of patent application, wherein the above open relationship is used to achieve that each byte can independently control the operating voltage. 18. The switched flash memory cell array as described in item 8 of the scope of patent application, which Page 21 583675 6. When updating the above-mentioned array elements in the scope of patent application, the byte data to be updated and the byte data not to be updated are written into a memory buffer page at the same time. The updated byte data is written into the byte memory cell to be updated in the array element. 19. The split flash memory cell array as described in item 18 of the scope of the patent application, wherein after the above-mentioned array elements are updated with some element data, the byte data in the memory cell buffer page is comprehensive with the array elements. Perform data verification to confirm that the byte data that has not been updated has not been disturbed. 20. The flash memory cell array as described in item 19 of the scope of patent application, wherein if the above data verification result finds that the byte data that has not been updated has been disturbed, the original data is backed up in the memory cell buffer. The unupdated byte data in the page is rewritten into the elements of the array element that were not updated. Page 22