TW583397B - Power on detect circuit - Google Patents

Abstract

A power on detect circuit. The power on detect circuit is designed for detecting low power on voltage and having low temperature coefficient of power on voltage. Detected power on voltage range is insensitive to process and temperature. The power on detect circuit includes two MOS transistors, one has a larger aspect ratio and is coupled to a voltage source by two series resistors, the first resistor and the second resistor, and the other has a lower aspect ratio and is coupled to the voltage source by a resistor, the third resistor. A comparator senses out voltage difference the first resistor and the third resistor to generate a power on reset signal.

Description

583397

FIELD OF THE INVENTION The present invention relates to a power-on detection circuit for detecting a voltage. The prior art is particularly concerned with the detection of the first chart and the power-on detection circuit. In the figure i, the power-on detection circuit 100 includes a voltage detection circuit 1 () and an Rc filter 1 2 0 0. The voltage detection circuit 1 10 includes a PM0S transistor MP1 and an NM0s transistor MN1. , MN2 and a resistor R1. The NM0S transistor MN1 and the pM0s transistor Mρι form a voltage reference circuit. The source and gate of the PM0S transistor MP1 are both connected to the node A 'and the source and gate of the NMOS transistor MN1 are both coupled to the node A. Node A is coupled to the gate of NMOS transistor MN2. The NM0S transistor Li 2 and the resistor R1 form a detection circuit. The resistor R1 is coupled between the drain of the NMOS transistor and the voltage source VCC. The PMOS transistor MP1 and the NMOS transistor MN1 form a voltage dividing circuit for generating a reference voltage VREF at the node A. The reference voltage VREF is generated by the PM0S transistor MP1 threshold voltage Vthp and the NMOS transistor MN1 threshold voltage Vthn. The NMOS transistor MN2 and the resistor R1 are used in a common source mode to output a detection result at the node B.

When the manufacturing process or temperature changes the threshold voltage Vthn of the NMOS transistor MN2, the threshold voltage Vthn of the NMOS transistor MN1 has the same change. Therefore, the threshold voltage Vthn of the NMOS transistor MN1 causes the same change in the reference voltage VREF. Under the condition that the power source VCC is unchanged, the change in the reference voltage vref compensates for the change in the threshold voltage Vthn of the NMOS transistor MN2. Node b is maintained

0697-8481twf (nl); p2002-042; rliu.ptd page 5 583397 ϊ L Ά n fi \ k .. 5. Description of the invention (2) unchanged, free from the change of threshold voltage Vthn of transistor MN2. The conventional technique of FIG. 1 has a disadvantage. The worst case is that the threshold voltage Vthp of the PMMOS transistor MP1 and the threshold voltage Vthn of the NMOS transistor MN1 change in the same direction. The change in the threshold voltage Vthp of the PMOS transistor MP1 hinders the compensation effect of the threshold voltage Vthn of the NMOS transistor MN1. The worst conditions are those in the PFNS / PSNS process. Power-on detection circuit 1 〇 Another disadvantage is that in advanced processes, the reduction of the voltage source VCC leads to a reduction in the allowable range. Since the threshold voltage (¥ 1: 111) and the threshold voltage Vthn do not decrease with the process, the detection voltage changes very much and the required voltage overhead is too high. Figure 2 shows another conventional technique. The power-on detection circuit 2 includes BJT transistors Q1, Q2, resistors R1, R2, R3, R4, and a comparator 22. The base and collector of the B J T transistor Q 1 are coupled to ground. The emitter of the B j τ transistor q j is coupled to the resistor R1. Resistor R2 and resistor R1 are connected in series and coupled to node A. The base and collector of the B JT transistor Q2 are coupled to ground. The emitter of b jt transistor Q2 is coupled to resistor R3 at node β. The resistor R4 is coupled to the resistors R2 and R3 and the voltage source VCC. The non-inverting input of comparator 22 is coupled to node a, and the inverting input of comparator 22 is coupled to node B. The area of the emitter of BJT transistor Q2 is n times the area of the emitter of BJT transistor Q 1. , Resistor R2 and resistor R3 have the same resistance value. -¥ The voltage source V C C starts to rise to the detection voltage range, and the voltage v a approaches the voltage VB. The power-on detection circuit 200 detects the voltage range from the voltage difference between the emitter-base junction voltage VEB2 of the BJT transistor Q2 and the resistor R3. The emitter-base junction voltage VEB2 has a negative temperature coefficient. The voltage difference of resistor R3 is connected

583397 1L 26 I. Description of the invention (3) The voltage difference between the surface voltage VEB1 and the interface voltage VEB2 is the thermal voltage multiplied by a factor. Because the resistance R1 = R3, the voltage VA = VB, the temperature coefficient of the voltage difference of the resistance R3 is positive and proportional to the resistance ratio (R3 / R2) + l and multiplied by 111 (? 0, so the power-on detection circuit 2〇〇 detects The voltage is measured by adjusting the emitter area ratio N and the resistance ratio R3 / R1. Θ resistor R4 is used to adjust the detection voltage to the required level. Comparator Z = Knife! Detect the voltage of nodes A and B VA and H. The output of comparator 22. The state will not change until the voltage source VCC rises to the detection voltage range. 65V system to m.13um 'The detection voltage range required is therefore required: The normal voltage 'BJT transistor does not work properly. This starts the detection circuit at the power source of the low voltage source. Including the first], the detection circuit is powered by electricity, which includes the drain, the first gold gas car, and the metal oxygen half. The gate of the transistor is coupled to a resistor, j: the source of the right oxygen-rich body is coupled to the first voltage source; the second resistor has the drain of the solar body; The other end of the first resistance of the crystal; its source is coupled to the first to the first- Resistor and first and second input terminals lightly connected

〇697.8481twf (nl); p2〇2.〇42; rlil • ptd page 7

V. Description of the invention (4) The content of the invention is obvious: Let ϊ = = other purposes, features, and advantages can be described in more detail as follows: 4 ♦ The preferred embodiment, and the accompanying drawings, will be the first embodiment. As shown in FIG. 3, the power is turned on MN2, the resistors Ri, R2, and the gate of the NMOS transistor MN1 are shown in FIG. 3. FIG. R6, and a comparator 22 f and the drain are connected together. The non-electrode surface of the triode MN1 is connected to the electric second 1. The f resistance R2 and the resistance R1 are connected in series and coupled to the node A. The gate and drain of NM〇s transistor # 2 are coupled together. The drain point B of the .s transistor mn2 is coupled to the resistor R3. The aspect ratio of the NMOS transistor MN1 is N times that of the NMOS transistor MN2. The resistor R4 is coupled between the resistors R2, R3 and the power source VCC. The non-inverting input terminal of comparator 22 is coupled to node A, and the inverting input terminal of comparator 22 is coupled to node b. The resistor is coupled between the source of NM1 transistor MN1 and the ground. The resistor R6 is coupled between the source of the NMOS transistor MN2 and the ground. Fig. 4 shows a timing chart of the first embodiment. Initially, the voltage source vcc is lower than the voltage Vf r, so the voltage VA is lower than the voltage VB, and the output r f voltage of the comparator 22 is at a low level. The voltage source VCC rises to the voltage Vfr, and the output voltage Vout of the comparator 22 is at the low level edge. In the process of increasing the voltage source VCC from the voltage Vfr to the voltage Vrr, the voltage VA and the voltage VB have a crossing point, and then the voltage vA is higher than the voltage VB. The comparator

0697-8481twf (nl); p2002-042; rliu.ptd p. 8 583397

V. Description of the invention (5) The crossing point of the voltage VA and the voltage VB is measured at 22, and the output voltage Vout of the comparator 22 changes from a low level to a high level. The voltage source VCC rises to the voltage Vrr, and the output voltage Vout of the comparator 22 is at the high level edge. Compared with the power-on detection circuit 200 of Fig. 2, the nm MOS transistors MN1 and MN2 are used to ensure that the power-on detection circuit 300 detects the voltage range Vrr = 0 · 8V and Vf r = 0 · 65V. Therefore, it can be lower than the working voltage of general BJT transistors. The resistor Ri is used to adjust the detection voltage ranges V rr and V f r to the required ranges. The voltage source VCC is between the voltage Vrr and the voltage Vfr. The voltage VA is close to the voltage VB. The resistance R1 is close to the voltage of the NMOS transistor. The gate-source voltage Vgsl and the NMOS transistor MN2 are gate-source. The voltage difference of the voltage Vgs2 (Vgsl-Vgs2), the currents of the resistors Rl, R2, and R3 are nearly the same, so the voltage difference of the resistor R3 is close to (R3 / Rl) (VgSbVgs2). The voltage difference (Vgs and Vgs2) has a negative temperature coefficient, and the gate-source voltage Vgsl has a negative temperature coefficient. The resistance ratio R3 / R1 is used to adjust the temperature coefficients of the voltages Vrr and Vf r, and can be reduced by the resistance ratio R3 / IU. The temperature coefficient of the gate-source voltage Vgs2 is reduced by the source degeneration of the NMOS transistor MN2. The resistor R6 is used to realize the source degradation of the NMOS transistor MN2. The resistor R5 has the same 4 energy. Figure 5 shows the process variation of the voltage start detection circuit. As shown in FIG. 5, the 'curves 200 A and 3 0 A represent the detection voltages Vrr of the voltage start detection circuits 2 00 and 3 00, respectively. Various extreme process pFNF, pFNS, pTNT,

im

583397 I η I

PSNF changes to NMOS and PMOS transistors. The variation range of the voltage start detection circuit 300 is smaller than that of the voltage start detection circuit 2000. Figure 6 shows the temperature change of the voltage start detection circuit. As shown in Fig. 6, the curves 200B and 300B represent the voltage start detection circuits 200 and 3 () () to detect the voltage Vrr, respectively. The temperature varies from -40 ° C to 125 ° C. The temperature coefficient of the voltage start detection circuit 300 is smaller than that of the voltage start detection circuit 2 00. 'Figure 7 shows a comparison between the embodiment and the conventional technique. The maximum and minimum detection voltages are obtained from various extreme process conditions PFNF, PFNS, PTNT, PSNF, temperature change from -40 ° C to 125 ° C, and resistance change by 20%. As shown in FIG. 7, the range of variation of the voltage start detection circuit 3 0 0 is 58.3% smaller than that of the voltage start detection circuit 200. Fig. 8 shows another circuit diagram of the first embodiment of the present invention. As shown in FIG. $, The power-on detection circuit 310 includes NMOS transistors MN1, MN2, resistors R1, R2, R3, R4, and a comparator 22. The source of the NM0S transistor MN1 is directly coupled to ground. The source of the NM0S transistor MN2 is directly coupled to the ground. Second Embodiment Fig. 9 shows a second embodiment of the present invention. As shown in FIG. 9, the power-on detection circuit 400 includes PM0S transistors MP1 and MP2, resistors Ri, R2, R3, R4, R5, R6, and a comparator 22. PM0S transistor MP1 ‘Gate and Sink are coupled together. The drain of the PM0S transistor MP1 is coupled to the resistor R1. The resistor R2 and the resistor R1 are connected in series and coupled to the node a. The gate and drain of the PM0s transistor MP2 are coupled together. The drain of the pM0s transistor Mp2 is coupled to the resistor R3 at node B. Aspect ratio of PM0S transistor MP1 (aspect

583397

p · 丄 程 · ΐί, 26 I k t I * '一 ____ V. Description of the invention (7) rat io) N times of PMOS transistor MP2. Resistor R4 is coupled between resistors R2 and R3 = ground. The non-inverting input of comparator 22 is coupled to node A, and the inverting input of comparator 22 is coupled to node B. The resistor R5 is coupled between the source of the PM0S transistor MP1 and the voltage source vcc. The resistor R6 is coupled between the source of the pMOS transistor MP2 and the voltage source vcc. Fig. 10 shows another circuit diagram of the second embodiment of the present invention. As shown in the figure, the power-on detection circuit 41o includes a PMOS transistor MIM, MP2, resistors Ri, R2, R3, R4, and a comparator 22. The source of the PM0S transistor MP1 is directly coupled to the voltage source vcc. The source of the pM0s transistor MP2 is directly coupled to the voltage source VCC. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

0697-8481twf (nl); p2002-042; rliu.ptd / Simple explanation of the diagram '----------------- Picture 1 矣 -Main Picture 2 Know the power-on detection circuit. Figure 3 is a second conventional power supply detection circuit. FIG. 4 is a circuit diagram of the first embodiment of the present invention. FIG. 5 is a timing chart of the first embodiment of the present invention. Figure β / shows the process variation of the voltage start detection circuit of the present invention. It shows the temperature change of the voltage start detection circuit of the present invention. Lef chart shows the comparison between the embodiment and the conventional technology. Fig. 8 shows another circuit diagram of the first embodiment of the present invention. Fig. 9 shows a circuit diagram of a second embodiment of the present invention.

FIG. 10 shows another circuit diagram of the second embodiment of the present invention. Symbol description: 22 comparator 1 0 0 power start detection circuit 11 0 voltage detection circuit 120 Rc filter 2 G 0 conventional voltage detection circuit 3 G 0 power start detection circuit 310 power start detection circuit 40 0 power supply Startup detection circuit

410 Power-on detection circuit j

Claims (1)

6. Scope of patent application1. A power-on detection circuit, which includes a pole, = 'It has a -drain, -gate, -source-metal oxide half thunder' day_m inter-electrode_connection To the drain, the source of the above-mentioned oxygen-rich electric solar element is coupled to a first electric body which has-terminal to the above-mentioned: metal-oxide semi-electric crystal terminal; the first resistor 'which has one end coupled to the above The other pole of the first resistor, called a body, has a pole, a gate, a source, and a gate light receiving electrode of the metal-oxide semiconductor transistor. The voltage source is the third source. Resistor, its body's drain; terminal ";; two and another; there is: the other end of the second resistor has a terminal coupled to the second metal-oxide semiconductor transistor and the terminal, and the other end is coupled to A second voltage source; the end surface is connected to the drain of the upper Zhu # transistor, and the second input end is coupled to the first metal-oxide half-comparator, which has a first input connected to the stem — ^ The contact point of the resistor. ^ The first resistor and the first one: 2. The power-on detection power as described in item 丨 of the scope of patent application ' The first metal oxide semiconductor is an N-type metal oxide semiconductor; the second metal oxide semiconductor is an N-type metal oxide semiconductor; the first voltage source is a low voltage source; and 0697-8481twf (nl); p2002-042; rliu.ptd p.13 583397 6. The scope of the patent application mentioned above 3 · If the patent further includes: a fifth electricity and the first electricity-a sixth electricity and the first electricity 4 · as a patent where: the first above the second above the first above The second 5 · If the patent further includes: a fifth electricity and the first electricity-a sixth electricity and the first electricity 6 ·-a kind of electricity-a first gold electrode, wherein the first metal oxygen half electricity-a first The source voltage source of the transistor is a high voltage source. The power supply start-up circuit described in item 2 of the scope of application blocks the resistance which is connected between the first metal-oxide-semiconductor half-voltage source and the resistance circuit which is coupled to the second metal-oxide-semiconductor voltage source. between. The source activation detection circuit described in item 1 of the source application scope of the anode body, the metal-oxide semiconductor is a P-type metal oxide semiconductor; the metal-oxide semiconductor is a P-type metal oxide semiconductor | The voltage source is A high voltage source; and the voltage source is a low voltage source. The power-on detection circuit described in item 4 of the application scope, a resistor, which is coupled between the source voltage source of the first metal-oxide-semiconductor; and a resistor, which consumes the second metal-oxide-semiconductor. The source of the crystal is between the sources. The source start detection circuit includes:-a milk semi-electric solar element, which has a gate electrode, a gate electrode, a gate electrode of a first metal-oxide semiconductor transistor, and a source electrode of the crystal; A pole coupled to a first voltage source; a resistor having one end coupled to the first metal-oxide-semiconductor 583397 VI. The terminal of the patent application body; terminal; a second resistor with an -end connected to the other electrode of the first resistor, an I μ metal-oxide semiconductor with a drain and an open K second metal-oxide half-electricity: Fengdian said the gate of the body is coupled to the drain, and the above-mentioned third thunder Γ t is coupled to the first voltage source; the drain of the body; To the second metal-oxide-semiconductor terminal and the third terminal I: another: there is another-comparator to the second resistor, and the f-th part is coupled to " the second voltage source; The drain of the transistor and the input terminal are coupled to the above-mentioned second metal-oxide half-resistor; and the second input terminal is connected to the above-mentioned resistance; ^ 4 I ·, +, and the fifth resistor, which are coupled It is connected between the first Jin Dong If and the first voltage source; and the source of the first milk + transistor-sixth resistor, which is coupled between the first voltage source and the first cross-bow voltage source. The source of this first gold semi-transistor is: the power-on detection circuit described in item 6 of Lishen Jinggan, the soil is an n-type metal-oxide semi-transistor; ^ The above-mentioned voltage plant Type metal oxide semi-transistor; · 8 · such as patent ff:-high voltage source. Power-on detection circuit described in item 6, 583397 .91 li 2β 岸 η ^ Sixth, the scope of the patent is requested. The first metal oxide semiconductor is a P-type metal oxide semiconductor; the second metal oxide semiconductor is a P-type metal oxide semiconductor; the first voltage source is a high voltage. A voltage source; and the second voltage source is a low voltage source. 0697-8481twf (nl); p2002-042; rliu.ptd page 16 iiii