TW200407544A - Power on detect circuit - Google Patents

Abstract

A power on detect circuit. The power on detect circuit is designed for detecting low power on voltage and having low temperature coefficient of power on voltage. Detected power on voltage range is insensitive to process and temperature. The power on detect circuit includes two MOS transistors, one has a larger aspect ratio and is coupled to a voltage source by two series resistors, the first resistor and the second resistor, and the other has a lower aspect ratio and is coupled to the voltage source by a resistor, the third resistor. A comparator senses out voltage difference the first resistor and the third resistor to generate a power on reset signal.

Description

200407544

The present invention relates to a power-on detection circuit, and more particularly to a power-on detection circuit for a primary voltage measurement. Figure 1 shows the conventional power-on pre-test circuit. Figure] The motion detection circuit 100 in the figure includes a voltage detection circuit 1 () and an RC filter. The voltage detection circuit 110 includes a PM0S transistor MP1, and NM0s transistor MN1 MN2. And resistor R1. The NM0S transistor Dragon 1 and the PMOS transistor MP1 form a voltage reference circuit. Both the source and the gate of the PM0S transistor MP1 are coupled to the node A, and the source and the gate of the NM0S transistor MN1 are coupled to the node A. Node A is connected to the gate of NMOS transistor MN2. The NM0S transistor MN2 and the resistor R1 form a detection circuit. The resistor is coupled between the drain of the NMOS transistor MN2 and the voltage source VCC. The PM0S transistor MP1 and the NMOS transistor MN1 form a voltage dividing circuit for generating a reference voltage VREF at the node A. The reference voltage VREF is generated by the PM0S transistor MP1 threshold voltage Vthp and the NMOS transistor MN1 threshold voltage Vthn. The NMOS transistor MN2 and the resistor R1 are used as a common source to output a detection result at the node b. When the process or temperature causes the threshold voltage Vthn of the NMOS transistor MN2 to change, the threshold voltage Vthn of the NMOS transistor MN1 has the same change. Therefore, the threshold voltage Vthn of the NMOS transistor MN1 causes the same change in the reference voltage VREF. Under the condition that the power source VCC is not changed, the change in the reference voltage VREF compensates for the change in the threshold voltage Vthn of the NMOS * transistor MN2. The node b remains unchanged and is protected from changes in the threshold voltage Vthn of the transistor MN2. The conventional technique in Figure 1 has a disadvantage. The worst case is the PM0S transistor.

0697-84811 wf (η1); ρ2002-042; r1i u. Ρ t d page 5 200407544 V. Description of the invention (2) The bulk MP1 threshold voltage Vthp and the NM0 transistor MN1 threshold voltage vthn have the same tendency to change. The change in the threshold voltage vthp of the PM0S transistor MP1 hinders the compensation effect of the threshold voltage vthn of the NM0 transistor MN1. The worst conditions are those in the PFNS / PSNS process. ′, Power-on detection circuit 1 00 Another disadvantage is that the reduction of the voltage source VCC in the advanced process leads to a reduction in the allowable range. Because the threshold voltage Vthn and the threshold voltage Vthn do not shrink with the process, the detection voltage varies greatly and the required voltage overhead is too high. Figure 2 shows another conventional technique. The power-on detection circuit 20 () includes BJT transistors Q1, Q2, resistors η, R2, R3, R4, and a comparator 22. The base and collector of the BJT transistor Q1 are coupled to ground. The emitter of the BJT transistor is coupled to resistor R1. The resistor R2 and the resistor R] are connected in series and coupled to the node A. The base and collector of the BJT transistor Q2 are coupled to ground. The emitter of the BJT transistor Q2 is lightly connected to the resistor R3 at the point b. Resistor R4 is connected to resistors R2 and R3 = voltage source VCC. Comparator 22 non-inverting input is coupled to node A. Comparing, 22 inverting input is coupled to node 8. The area of the emitter of BJT transistor Q2 is N times the area of the emitter of BJT transistor Q1. Resistor R2 has the same resistance value. When the voltage source vcc starts to rise to the detection voltage range, the voltage VA approaches the voltage VB. The power-on detection circuit 200 detects the voltage range from the voltage difference between the emitter-base junction voltage VEB2 of the BJT transistor Q2 and the resistor R3. The emitter-base junction voltage VEB2 has a negative temperature coefficient. The voltage difference of the resistance μ is the voltage difference between the interface voltage VEB1 and the interface voltage VEB2, which is the thermal voltage multiplied by a factor. Because the resistance R1 = R3, the voltage VA = VB, the temperature difference between the resistance R3 and the voltage is 0697-8481twf (nl); p2002-042; rliu.ptd Page 6 200407544

V. Description of the invention (3) The number is positive and proportional to the resistance ratio (R3 / R2) + 1 and multiplied by 111 (1 ^), so the power-on detection circuit 2 00 detects the voltage by adjusting the emitter area I And resistance ratio R3 / R1. 'Resistor R4 is used to adjust the detection voltage to the required level. The comparator 22 is used to detect the voltages VA and VB of the nodes a and b, respectively. The output voltage of comparator 22 will not change until the voltage source vcc rises to the detection voltage. & process 〇 65V to 〇 So need to include the first gold to the drain, one resistor, two resistors, half transistor two metal oxygen half with one end with one end coupled to the first power for obvious It is easy to understand that it is reduced to 0 · 1 3um, the required detection voltage range is • 8V, which is lower than the normal voltage, and the BJT transistor cannot work normally. Power-on detection circuit capable of operating on a low voltage source. Herein, the present invention provides a power-on detection circuit. The gate coupling of the first metal-oxide-semiconductor transistor is: the source of the first metal-oxide-semiconductor transistor is coupled to the first voltage source, and the first end surface is connected to the first The drain of a metal oxide semi-transistor: the first terminal: connected to the other-terminal of the first resistor; the second metal oxide source is coupled to the first voltage source; The drain of the transistor; the fourth resistor connected to the other end of the third resistor and the other-end of the third resistor, the second and the comparator 'which has the first input resistance and the first pole of the first body' "and The second input terminal connection = the contact point of the Leyi resistor. Let ΐ: i ff and other purposes, features, and advantages can be a better embodiment, and with the accompanying diagram, make

200407544

The detailed description is as follows: First Embodiment FIG. 3 shows a first embodiment of the present invention. As shown in FIG. 3, the power-on detection circuit 300 includes NMOS transistors MN1, MN2, resistors R1, R2, R3, R4, R5, R6, and a comparator 22. The gate and terminal of the NM1 transistor MN1 are coupled together. The drain of the NM0S transistor MN1 is coupled to a resistor R1, a resistor R2 and a resistor R1 are connected in series and coupled to the node a. The gate and drain of the NMOS transistor M ^ 2 are coupled together. The drain of the NMOS transistor MN2 is coupled to the resistor R3g at the node B. The aspect ratio of the NMOS transistor is N times that of the NMOS transistor. The resistor R4 is coupled between the resistors R2 and R3 and the voltage source VCC. The non-inverting input terminal of the comparator 22 is coupled to the node a, and the inverting input terminal of the comparator 22 is coupled to the node b. The resistor R5 is coupled between the source of the NMOS transistor MN1 and the ground. The resistor R6 is coupled between the source of the NMOS transistor 2 and the ground. Fig. 4 shows a timing chart of the first embodiment. At the beginning, the voltage source ¥ (:(: is lower than the voltage vfr, so the voltage "below the voltage", the output voltage of the comparator 22 is at a low level. The voltage source VCC rises to the voltage Vf r, and the output voltage of the comparator 22 Vout is at the edge of the low level. In the process of the voltage source VCC rising from the voltage Vf r to the voltage Vrr, the voltage VA and the voltage VB have a crossing point, and then the voltage VA is higher than the voltage. ”The comparator 22 detects the voltage VA and the voltage. At the crossover point, the output voltage σ Vout of the comparator 22 transitions from a low level to a high level. The voltage source VCC rises to a voltage Vrr, and the wheel-out voltage of the comparator 22 is vout.

200407544 Fifth, the description of the invention (5) is on the edge of the high level. Compared with the power-on detection circuit 2 in FIG. 2, NM0S transistors MN1 and MN2 are used to ensure that the power-on detection circuit 300 detects the voltage range Vrr = 0.8V and Vfr = 0.65V, so it can be low. Working voltage of general BJT transistor. The resistor R 4 is used to adjust the detection voltage ranges v Γ r and V f r to the required ranges. When the voltage source VCC is between the voltage Vrr and the voltage Vfr, the voltage VA is close to the voltage VB, and the voltage difference of the resistor R1 is close to the NMOS transistor M1 gate-source voltage Vgsl and the NMOS transistor MN2 gate-source voltage VgS2 The voltage difference between resistors (Vgs and Vgs2) is nearly the same, and the currents of resistors R1, R2, and R3 are nearly the same, so the voltage difference between resistors R3 is close to (R3 / Rl) (VgshVgs2). The voltage difference (Vgsl-Vgs2) has a negative temperature coefficient, and the gate-source voltage Vgs 1 has a negative temperature coefficient. The resistance ratio R3 / ri is used to adjust the temperature coefficients of the voltages vrr and Vfr, and can be reduced by the resistance ratio R3 / Ri. The temperature coefficient of the gate-source voltage Vgs2 is reduced by the source degeneration of the NMOS transistor MN2. The resistor R6 is used to realize the source degradation of the NMOS transistor MN2. Resistor R5 has the same power color. Figure 5 shows the process variation of the voltage start detection circuit. As shown in Fig. 5, the curves 200A and 300A represent the detection voltages Vrr of the voltage start detection circuits 2000 and 300, respectively. Variations of PFNF, pFNS, pTNT, PSNF on NMOS and PM0S transistors in various extreme conditions. The variation range of the voltage start detection circuit 3O () is smaller than that of the voltage start detection circuit 200. Figure 6 shows the temperature change of the voltage start detection circuit. As shown in Figure 6, 200407544 V. Description of the Invention (6), the curves 200B and 300B respectively represent the voltage start detection circuits 200 and 300 to detect the voltage Vrr. Temperature change from -40 ° C to 125 t :. The temperature coefficient of the voltage starting debt measurement circuit 300 is smaller than that of the voltage starting detection circuit 2000. Fig. 7 shows a comparison between the embodiment and the conventional technique. The maximum and minimum detection voltages are obtained from various extreme process conditions PFNF, PFNS, PTNT, PSNF, temperature change from -40 ° C to 125 ° C, and resistance change by 20%. As shown in FIG. 7, the range of variation of the voltage start detection circuit 3 0 0 is 58.3% smaller than that of the voltage start detection circuit 200. Fig. 8 shows another circuit diagram of the first embodiment of the present invention. As shown in FIG. 8, the power-on detection circuit 310 includes NMOS transistors MN1, MN2, resistors R1, R2, R3, R4, and a comparator 22. The source of the NMOS transistor MN1 is directly coupled to ground. The source of the NMOS transistor MN2 is directly coupled to ground. Second Embodiment Fig. 9 shows a second embodiment of the present invention. As shown in FIG. 9, the power-on detection circuit 400 includes PMOS transistors MP1, MP2, resistors R1, R2, R3, R4, R5, R6, and a comparator 22. The gate and drain of the PMOS transistor MP1 are coupled together. The drain of the PMOS transistor MP1 is coupled to a resistor R1. The resistor R2 and the resistor R1 are connected in series and coupled to the node a. The gate and drain of the PMMOS transistor MP2 are coupled together. The drain of the pmos transistor MP2 is coupled to a resistor R3 at node B. Aspect ratio of the PMOS transistor MP1 is N times that of the PMOS transistor MP2. Resistor R4 is coupled between resistors R2, R3 and ground. The non-inverting input of comparator 22 is coupled to node a, and the inverting input of comparator 22 is coupled to node B. Resistor R5 is coupled to the PMOS transistor

200407544 V. Description of the invention (7) Between the source of MP1 and the voltage source Vcc. The resistor R6 is coupled between the source of the pMOS transistor MP2 and the voltage source Vcc. Figure 1_0 shows another circuit diagram of the second embodiment of the present invention. As shown in the figure, the power-on detection circuit 41o includes a pMOS transistor, MP2's resistors Ri, R2, R3, R4, and a comparator 22. The source of PM0S transistor 1 is directly coupled to the voltage source VCC. The source of the PM0S transistor MP2 is directly coupled to the voltage source VCC. Although the present invention has been disclosed as above with a preferred embodiment, it is not limited thereto. The present invention, anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

0697-84811 wf (η1); ρ2002-042; r1i u.ρ t d Page 11 200407544 Brief description of the diagram The first diagram shows the conventional power-on detection circuit. Fig. 2 is a circuit diagram of another conventional prior art power-on pre-measurement circuit. Fig. 3 is a circuit diagram of a first embodiment of the present invention. Fig. 4 is a timing chart showing the first embodiment of the present invention. FIG. 5 shows the process variation of the voltage start detection circuit of the present invention. FIG. 6 shows the temperature = temperature of the voltage start detection circuit of the present invention. FIG. 7 shows a comparison between the embodiment and the conventional technology. Fig. 8 shows another circuit diagram of the first embodiment of the present invention. Fig. 9 shows a circuit diagram of a second embodiment of the present invention. Kind of circuit diagram Figure 10 shows another symbol description of the second embodiment of the present invention: 22 comparator 100 110 120 200 300 310 400 410 power-on detection circuit voltage detection circuit RC filter power-on detection electric power-on detection Power On Weigang Power; Power On Weigang i

Claims (1)

A range of humiliation range A range of humiliation range, a second resistor, a terminal; a second metal-oxygen half-pole, of which the second metal-oxygen half-transistor is a second metal-oxygen semi-transistor'—the second resistor, of which: two: a kind of power source The start-up detection circuit includes: an oxygen semi-transistor having a drain electrode, a gate electrode of the first metal oxide semiconductor = the first metal-oxide semiconductor transistor is coupled to the source of the I 3 transistor; To a drain of a first voltage a; the electric 11 has a terminal coupled to the drain of the first body; π handles the first terminal sum; another 3 has an end surface connected to the first and It is also known that the other end is coupled to a first comparator, which has a first input terminal connected to the drain of the power-up terminal, and a second input terminal coupled to the above two resistors. 4 Start the power supply as described in item 1 of the patent application. The first metal oxide semiconductor is an N-type metal oxide semiconductor. The second metal oxide semiconductor is an N-type metal oxide semiconductor. The first voltage source is A low voltage source; and • a gate electrode, a source, a drain electrode, the other gate electrode, a source electrode of the aforesaid metal-oxide-semiconductor resistor, the above source, and another voltage source of the metal-oxide-semiconductor resistor; With two metal-oxygen half-one resistors and the circuit under test, the crystal is 200407544 6. The non-polar terminal of the patent application body; .-resistor 'which has a-terminal coupled to the other pole of the first resistor, and its electric drain, -open electrode, -source-second light are connected to the above-mentioned first -The source of the galaxy, the drain of the body; one end is coupled to the second metal-oxide-semiconductor terminal and the second is connected to the other two resistors of the second resistor: And the second input terminal is coupled to the above-mentioned resistors and ί buckle and five resistors, and its surface is connected between the above-mentioned first metal-oxygen half-electricity and the above-mentioned voltage source; m + 胄 source body The resistors f and f are coupled between the first voltage source of the second metal-oxide-semiconductor crystal s and the first voltage source. "The source of the body wherein:" The power-on detection circuit as described in item 6 of the scope of patent application, said first metal-oxide semiconductor is an N-type metal oxide semiconductor; as mentioned above, the two metal-oxide semiconductor is The N-type metal-oxide semiconductor; the first voltage source is a low voltage source; and the second voltage source is a high voltage source. 8. The power-on detection circuit as described in item 6 of the scope of patent application, m 0697-8481twf (nl); P200.02.42; rliu.ptd Page 15 200407544 6. The scope of patent application Among them: A metal oxide semiconductor is a P type metal oxide semiconductor; the second metal oxide semiconductor is a P metal oxide semiconductor; the first voltage source is a high voltage source; and the second voltage source is A low voltage source. 0697-8481twf (nl); p2002-042; rliu.ptd p. 16