TW579499B - Data processing method using error-correcting code and an apparatus using the same method - Google Patents

Data processing method using error-correcting code and an apparatus using the same method Download PDF

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Publication number
TW579499B
TW579499B TW90129583A TW90129583A TW579499B TW 579499 B TW579499 B TW 579499B TW 90129583 A TW90129583 A TW 90129583A TW 90129583 A TW90129583 A TW 90129583A TW 579499 B TW579499 B TW 579499B
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TW
Taiwan
Prior art keywords
error correction
data
correction code
memory
block
Prior art date
Application number
TW90129583A
Other languages
Chinese (zh)
Inventor
Koichi Otake
Yoshiyuki Ishizawa
Tadashi Kojima
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2000377838A priority Critical patent/JP3619151B2/en
Priority to JP2000401172A priority patent/JP3519684B2/en
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW579499B publication Critical patent/TW579499B/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/18Error detection or correction; Testing, e.g. of drop-outs
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes
    • H03M13/15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515Reed-Solomon codes
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909Product codes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10527Audio or video recording; Data buffering arrangements
    • G11B2020/1062Data buffering arrangements, e.g. recording or playback buffers

Abstract

When an error-correcting code is created for the data stored in a memory and added to the data, even if an error occurs in the data on the memory, the adverse effect of the error will be eliminated. In the present invention, when the data is stored in the memory, an error-correcting code PI is created beforehand using another memory, such as an S-RAM. The error-correcting code PI, together with the data, is written into the memory. After 16 sectors of data and PI have been stored, an error-correcting code PO is created for the data and PI and added to them. When the data is read from the memory, a PI correcting process is carried out each time a PI series is read out. This makes it possible to restore the original data, even if the data is destroyed (or an error occurs) on the memory.

Description

579499 Α7 Β7 Printed by the Consumers' Cooperative of the Bureau of Wisdom and Finance 1 of the Ministry of Economic Affairs 5. Description of the Invention (彳) Background of the Invention The present invention relates to an effective use of recording video data, audio data or computer data in a medium (such as a CD or (Diskette) or an error correction code generation method for reproducing data recorded on a medium. The invention further relates to a method for generating an error correction code, which can effectively transmit or receive video data and the like. The present invention further relates to a recording device, a reproduction device, and a receiving device, which employ an error correction code generation method. The present invention is particularly characterized by an error correction method using a buffer memory to perform error correction processing. When video data, audio data, computer data, etc. are recorded on, for example, a disc or disk, an error correction code is added to the data block. In the process of adding the error correction code, the data block is temporarily stored in a memory, and the error correction code of the data block row and row is generated. The error correction code added to the column is generally referred to as internal parity and is simply referred to as PI. The error correction code added to the line is generally called parity and is referred to as P 0 for short. In the process of adding the error correction code, when the data block is temporarily stored in the memory before the error correction code is generated, a part of the data in the memory may be damaged (or an error may occur) ). The damage can be attributed to the joint state of the memory or the data pattern. In addition, sudden external noise is also a disadvantage. The error that occurs at this time is called a memory error. At this time, the error correction code in the data block where the memory error occurred ((Please read the precautions on the back before filling this page). The size of the paper is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) -4 -579499 A7 B7 Printed by the Consumers' Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs. 5. Description of Invention (2) (hereinafter referred to as the changed data block) was generated. The error correction code is added to the changed data block, and the generated block is recorded in a recording medium. When data is reproduced from the recording medium, the error correction circuit uses the error correction code to perform an error correction process on the changed data block. That is, the changed data blocks are correctly reproduced. That is, the data block including the memory error has been correctly reproduced. However, this memory error is unnecessary for the original data. Therefore, when a memory error occurs, the original data cannot be restored correctly. Brief description of the invention Therefore, the object of the present invention is to provide a data processing method using an error correction code that can correctly restore the original data when a data error (memory error) occurs in the memory, and records using this method The system is also a regeneration system unit, and a transmission system and a reception system using the method. The following are the basic concepts of the error correction code processing method of the present invention. The invention is characterized in that the transmission or recording system generates an error correction code p I for each row of a data block having a matrix structure, and stores the error correction code p I and the data block in a memory, and when an error occurs, When the correction code PI plus the added data block is read from the memory, the error correction process is performed in the data block column according to the error correction code PI. (Please read the precautions on the back before filling this page) The size of the paper used in this edition applies to the Chinese National Standard (CNS) of 8 and 4 (210X: 297 mm) -5- 579499 A7 B7 Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing 5. Description of the invention (3) Further, the present invention is characterized in that when the data block of the matrix structure that applies the error correction processing by the data error correction code PI is read from the memory, the receiving or regeneration system is again An error correction process is performed using the error correction code PI for each column. In particular, when data is stored in a memory (first memory), the present invention uses a separate second memory (memory having a structure that does not damage data) in advance to generate an error correction code PI and The generated data is written into the first memory in combination with the data. Thereafter, when the data of the K sector (sector) and PI have been stored in the first memory, the error correction code P 0 is generated for the data and PI and added to it. When the data is read from the first memory, the PI correction process is executed each time the PI series is taken out. This allows the data to be restored to its original state, despite the destruction of the data in the first memory (or a memory error). When the data is reproduced, the reproduced data is temporarily stored in the memory, and the PI and P 0 error correction processing is performed. When the data in the memory is sent out after the error correction processing, the PI error processing is performed again for the data read from the first memory. This allows the data to be restored to its original state, despite the damage to the data in the memory (or a memory error). Further, the object of the present invention is to provide a data processing device that can correctly restore the original data, even though a data error (or a memory error) occurs in the memory, and a method of using the memory to ensure reliable operation Sex. ------ : ίL # -------- Order ------ # 1 (Please read the precautions on the back before filling in this purchase) This paper size applies to Chinese national standards (CNS & gt Α4 Specification (210 × 297 mm) -6-579499 Printed by the β Industrial Consumer Cooperative of the Ministry of Economic Affairs and Intellectual Property 4th Bureau A7 _B7_ V. Description of the Invention (4) In particular, the present invention is characterized by a transmission or recording system for An error correction code PI is generated for each row in a data block having a matrix structure, and the error correction code PI and the data block are stored in the memory. When it is read in the memory, the error correction process is performed in the data block according to the error correction code PI. After that, when an error cannot be corrected when an error correction process is performed using the error correction code PI The memory blocks that store related rows or data blocks will be changed to avoid memory errors. And the areas where memory errors occur are learned and are no longer used. Brief description of the figure Figure 1 is shown on DVD To obtain the data section of the physical sector (sector) An explanatory diagram of the configuration in the data block of the DVD; FIG. 3 is an explanatory diagram of a feedback shift register for generating scramble data; and FIG. 4 is an illustration of the ECC block. Explanatory diagram; Figure 5 is an explanatory diagram showing a recording section; Figure 6 is an explanatory diagram showing an error correction code P 0 interleaved with an ECC block; and Figure 7 is a block diagram for explaining a conventional recording and reproducing unit. The method of generating error correction codes in the recording and recording system; Figure 8 is a block diagram for explanation in the conventional recording and reproduction unit (please read the precautions on the back before filling this page) CNS) Α4 specification (210X297 mm) 579499 A7 B7 Printing method of the error correction code of the reproduction system of the Intellectual Property Office of the Ministry of Economic Affairs, Employees' Cooperatives 5. The invention description (5); Figure 9 is a diagram to explain Know the error correction code when a D RAM memory error occurs in the recording and reproduction unit; Figure 10 is a block diagram of a recording system to explain an embodiment of the error correction code generating method of the present invention; Figure 11 is a display of this An explanatory diagram of the data structure of the ECC block obtained by the clear error correction code generation method; Figure 12 is a block diagram of a reproduction system to explain the error correction code generation method in the ECC block An embodiment of the error correction method; FIG. 13 is a block diagram of a recording system to explain another embodiment of the error correction code generating method of the present invention; FIG. 14 is a block diagram of a recording system to explain this Another embodiment of the method for generating the error correction code of the invention; FIG. 15 is another embodiment of the method for correcting errors in the ECC block obtained by the method of generating the error correction code of the invention; FIG. 16 is a record And a reproduction system block diagram to explain the error correction code generating method of the present invention and an embodiment of the error correction code using the error correction code to correct errors; FIG. 17 is a block diagram of a recording system and a reproduction system to explain Another embodiment of the error correction generating method of the present invention; FIGS. 18A and 18B are explanatory diagrams for illustrating processing in the error correction code generating method of the present invention. At the time of the data, including the memory map of the buffer memory and the data string of the ECC block of the memory error; (Please read the precautions on the back before filling this page)-The paper size of the book applies to the Chinese National Standard (CNS) A4 Specifications (210X297mm) -8-579499 A7 B7 V. Description of the Invention (6) and Figure 19 are explanatory diagrams to show the processing of the ECC block of the memory error including the method of generating the error correction code of the present invention Another example 0 (please read the precautions on the back and fill in this page) Order component comparison table 2 0 1 Buffer memory (DRA M) 2 0 2 Section information adding mechanism 2 0 3 Ε DC generating and adding mechanism 2 0 4 Hybrid mechanism 2 0 5 Ε CC memory (DRA M) 2 0 6 P I generation and joining mechanism 2 0 7 P 0 generation and joining mechanism 2 0 8 Detailed description of the invention of the modulation / synchronization joining mechanism Here, Exemplary embodiments of the present invention will be explained with reference to the drawings. The use of a DVD (Digital Versatile Disc) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will be explained with reference to FIGS. 1 to 8 Recording and reproducing unit of the error correction circuit and the error correction code added to the circuit configuration. First, referring to Figs. 1 to 6, the structure of data recorded on a DVD will be explained. Figure 1 shows the sequence of data processing to obtain the physical section in D V D. The section is called “% data section” according to the signal processing stage. The paper size of the record applies to the Chinese National Standard (CNS) A4 specification (210X: 297 cm).--9- 579499 Intellectual Property Bureau, Ministry of Economic Affairs Employee Consumer Cooperatives printed A7 B7 V. Invention Description (7) Section 〃, or% Entity Section 〃. As shown in Figure 2, the data section includes the main data of 208 bytes, 4-byte identification data (ID), and 2-byte ID error induction code (IED) (as the Error code in the code), 6-byte copyright management information (CPR_MAI), and 4-byte error induction signal (EDC) (as a signal that senses errors in this data segment. 0 ID, IDE, The steps of CPR-MAI and EDC are steps A1 to A3 in Fig. 1. In step A1, ID is added to the main data. In step S2, IED is further added. In addition, in step S3 Add CPR — MAI. Then, calculate the EDC of the main data. The EDC is added to the main data. Then the mixed data is added to the main data (including 2048 bytes) in the data section (steps A4, A5, A6) ). Then, after mixing the data, 16 data sections are put together. A Reed-Solomon error correction code is generated and added to the 16 data sections (step A6). The The recording section (ECC adding section) is for adding the error correction code PI and The data section of the error correction code P0 (step A7). This physical section is a standard that applies 8/16 correction and adds the synchronization code (SYNC code) to the interleaved 9 1 bytes in the recording section. Head (step A8). Use Figure 2 to explain the structure of the DVD data section. The data section contains the main data including a 20-by-8-byte leader or 2064-bits with a 72-by-12 byte Tuple. That is, a data section contains the main data of 2048 bytes, and the discrimination of the 4-byte paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 cm) ------ r--I — (please read the precautions on the back before filling out this page) Order-10- 579499 A7 B7 Printed by the staff of the Ministry of Economic Affairs ’s Smart Finance 1 Bureau Cooperative, V. 'Invention Note (8) 1 I Information (ID), 2-byte ID error induction code (IED) 1 1 I% 6-byte copyright management information (CPR Μ AI), and 4 1 1-byte error induction code (EDC). 1 I Please 1 1 Figure 3 shows the main data generated in step A 4 (including the first news) 1 1 read 1 2 0 4 8 bytes) of the mixed data Sk shift register. For example, the back 1 I If the ID part of the data segment is used as the starting point to generate the mixed note 1 I data S k. This mixed data Sk is used as the main item of the mixed data! 0 □ and then 1 1 4 required data (208 bytes). As a result, the material Dk 'after the mixing is the result of the mutual exclusion of Sk (k is 0 to 2047) and Dk. 1 | described with reference to FIG. 4] The structure of the E C C block. 1 I data block has been formed to have 172 rows X 1 9 2 columns 9 per package 1 order I contains 172 bytes X 1 2 columns 16 data sections 0 Red Solomon 1 1 I The error correction code is generated and added to 172 rows X 19 2 columns. First f 1 1 1 6 byte error correction code P 0 is generated and added to each 172 rows 1 1. In the sequence of P 0 Each row contains 192 bytes plus 16 bits and 1 m bytes, and it is 208 bytes. Next, a 10-byte error correction 1 1 I code P I is generated and added to each of the 128 columns including the column of the error correction code P 0. The 182 rows X 2 0 8 1 1 columns added with the error correction code P I form an E C C block. Although when P0 and P1 are generated in the reverse order of 1 1 > the same code pattern can be obtained. 1 | A vertical row in the E C C block is called P 0 sequence 9 and horizontal.   The 1 I to one column is called the PI sequence. The P 0 sequence contains 192 bytes plus 1 1 I 16 bytes, or 208 bytes. In a single P 〇 sequence> can be 1 1 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -11- 579499 Printed by A7 B7 of the Consumer Finance Cooperative of the Bureau of Wisdom and Finance of the Ministry of Economic Affairs Explanation (9) Detect errors up to 8 bytes. The p 1 sequence contains 172 bytes plus 10 bytes, or 182 bytes. In a single PI sequence, errors of up to five 7C groups can be corrected. Next, the structure of the recording sector is explained with reference to FIGS. 5 and 6. In the ECC block composed of 20 8 columns X 1 82 rows, 16 columns constituting the error correction code P 0 are separated by individual columns to columns. The separated rows are inserted one by one at the interleaving positions of the 12 rows of the 192 rows of data sections, resulting in the construction shown in FIG. 6. This is referred to as the interleaving of P0. Therefore, the ECC block after the parent error is made up of 16 groups of 13 columns X 1 8 2 bytes (= PI added data (for 12 columns) plus P 〇 (for one column)) ° such as As shown in FIG. 5, the recording section is composed of PI adding data (for 12 columns) plus P 0 (for one column), that is, 13 columns X 1 8 2 bytes. The E C C block after the column interleaving is composed of 16 recording sectors, as shown in FIG. 6. The physical section is such that a SYNC code is added to the 91 bytes of each column in the record section of 13 columns X 1 8 2 bytes (2 3 6 bytes). Interleave the header, and start to adjust from column 0 and column by column. The one obtained by adding the S Y N C code to the header of the 91-byte data is the SYNC box. Therefore, the physical section is composed of 16 groups X two SYNC boxes. Referring to Figs. 7 and 8, the error correction code adding circuit in the data recording unit is explained. In Figure 7, the user data transmitted by the autonomous computer are sequentially stored in this paper. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) '-12--------— Mm—— (Please read the notes on the back before filling in this card.) Order 579499 A7 B7 Printed by the Anti-Corruption Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs V. Description of the invention (1〇) Buffer memory 2 0 1 When the data is read in the body 2 01, the stored user data is processed by the section information joining organization 2 02, the EDC generating and joining organization 203, and the hybrid organization 204. The processing is performed at the interleaving of the main data of 2048 bytes, and the data is converted into a single data section. The information in this section is added by the institution 202 to the 4-byte identification data (1 D), the 2-byte ID error sensing code (I e D), and the 6-byte copyright management information (CPR — ΜΑ I ) To the main profile. The ED C generation and joining mechanism 203 generates and adds a 4-byte error sensing code (EDC) to the entire 060-byte data, and generates the entire 206-byte data. The mixing mechanism 204 mixes the main data in the data section. The mixed data sections are sequentially stored in the ECC memory 205. In the ECC memory 205, a data section of 172 rows x 192 rows is formed, and 16 data sectors of 172 bytes x 12 rows ( sector). PI generation and joining mechanism 206 and P 0 generation and joining mechanism 207 generate and add error correction codes to 172 rows x 192 columns of data blocks, and generate an ECC block. ECC explained before Block, which is interleaved by columns, and then transmitted to the modulation / synchronization joining mechanism 208. The modulation / synchronization joining mechanism 208 converts the 8-bit input data into 16-bit code characters and interleaves EC C blocks in the input column. That is, a modulation of 8/1 6 is generated. After that, the SYNC code was added to the staggered portion of the input data of 91 bytes. The paper size of the specimen is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) L0 ------, 玎 ------ (Please read the notes on the back before filling out this page) -13- 579499 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the A7 B7 V. Invention Description (11) header to form a physical section. The formed physical section is transmitted as recording material and recorded in a medium. Now, the effect of the error correction code will be explained. A data reproduction system including error sensing and sensing mechanisms reproduces recorded data. When an error occurs in the data in the reproduction entity section of the reproduction process, this mechanism uses an error correction code to correct the error in the error containing the E C C block. The error sensing and correction mechanism can recover the original E C C block without errors within its correction capability. Referring to Fig. 8, an error generation method on the data reproduction side is explained. After the playback data read from the recording medium is separated from the synchronization code by the synchronization separation / modulation mechanism 2 21, the 8/16 modulation data is demodulated and the recording section is decompressed. Because errors may occur in recording or regenerating the recorded data due to defects, noise, chatter, crosstalk, etc. in the disc, the playback data will include some errors. The read-out recording sections are sequentially stored in the ECC memory 205. Therefore, the read-out recording sections are composed of 182 rows and 208 columns of 16 recording sections (: (: block.?) Correction mechanism. 2 2 2 and? 1 correction mechanism 22 3 performs error correction on ECC blocks of 1 8 2 rows X 1 92 columns, and corrects errors in the playback signal. The PI correction mechanism 2 2 3 for each of the ECC blocks Column calculation error pattern induction 値 polysemes (syndr omme). If an error is detected, error correction is performed. When the original data is reproduced without errors, the polysemes get 0 to 0. When errors occur in the record or When transmitting a signal, the ambiguous word is obtained from the error position indicating the position where the error occurred. ^ Paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm 1 " " (Please read the precautions on the back before filling in this (Page) -14- 579499 at _B7_ V. The description of the invention (12) and the error pattern determined by the error state. The P0 correction mechanism 2 2 2 reads from the memory 2 0 5 in the P sequence 2 0 8 Byte data and perform specific operations on that data When the synonym does not turn to 0 after the result of the operation, the P 0 correction mechanism performs error correction on the sequence. When the corrected data is subjected to an error calculation, the error correction code is generated to recover When the data, the synonym gets 0 to 0. The above operation is performed on all 182 bytes of ECC blocks. When the length is 8 bytes or more, errors occur in a sequence. At this time, the P0 correction mechanism 2 2 2 cannot correct errors. At this time, however, because the PI correction mechanism 2 2 3 can perform error correction of up to 5 bytes on the PI sequence, if the error length is included in a single P 0 sequence, When the P 0 correction is performed on lines 182 or shorter, the error can be corrected. Further, the repetition of the P 0 correction and the PI correction will correct a single P 0 correction and a single correction. Errors that cannot be corrected by PI correction. When all consents have a value of 0, the error correction of the ECC block is completed. The error correction ECC block printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is transmitted to the hybrid cancellation agency 2 2 4. The mixing cancellation mechanism 2 2 4 adds the mixed data (or the mixed data is mutually exclusive or) to the main data of the 20 48-bit leader in the mixed data section, and cancels the mixing of the main data and stores it in the buffer Result data in memory 2 01. EDC error sensing mechanism 2 2 5 According to the 4-byte error sensing code (e DC) included in the data segment, the error in the data segment is sensed. The paper size is applicable to China. National Standard (CNS) A4 Specification (210X297 mm) -15- 579499 A7 printed by Employee Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs ___B7_5. The invention description (13) is incorrect. When an error is sensed, the segment is regenerated. The data segments stored in the buffer memory 201 are sequentially transmitted to the host. Low-cost and large-capacity DRAM (Dynamic RAM) is used as buffer memory 205, 201. Because of the structure of DRAM, it depends on the connection state of the memory or the pattern of the data, so that the data in the memory is Destroyed (or memory error occurred). When the data part in the memory is destroyed (or a memory error occurs) and the data block is changed, when the error correction code PI, P 0 is generated and added, the error correction code PI, For data changed by a memory error, the PO will become the correction error correction code. When an EC C block having an error correction code generated for the changed data is recorded and then reproduced, the changed data is reproduced, although the error correction process is performed after the reproduction. When the memory error 32 occurs in a part of the data block 32 having a column of 172 bytes X 192 and the situation where the block is changed, it will be described with reference to FIG. 9. First, the PO generation and joining mechanism 9 generates an error correction code P 0 for each 172 rows, and adds the P 0 to the row. The error correction code PO 3 3 (16 bytes) for line 31 is generated based on the data changed by the memory error 32. Next, the PI generating and adding circuit 8 generates a 10-byte error correction code P I into each 108 column including the error correction code P 0, and adds the PI to the column. The error correction code P 136 (10 bytes) generated for column 3 4 will be based on the memory error 32 ------: --- MW ------, 1T ---- -(Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 size (210X297 mm) -16-Printed by the staff of the Intellectual Property Bureau of the Ministry of Economy 579499 A7 ___B7_ 5. Description of the invention (14) The changed information is generated. Further, the error correction code P I 3 7 generated by the error correction code P 0 of 16 rows is generated based on the data including the error correction code P 0 3 3 generated by the data changed by the memory error 32. As a result, an appropriate error correction code is added to the data block changed by the memory error 32. At this time, for all error patterns of the PI sequence including the error 32 2 to 0 8 sequence, the synonym and the synonym for the P 0 error of the 18 2 line are obtained, and as a result, the E CC block is I think there is no error. Actually, however, the original data in the E C C block has been changed by memory error 32. Here, it is considered that the E C C block generated according to the changed data block is recorded to a recording medium and then the playback data of the block is reproduced from the medium. The playback data uses an error correction code to apply an error correction process. Here, the error occurred in the reproduced data is corrected within the range of the correction capability, and the playback data is restored by this. However, memory errors, including before recording, cannot be corrected. That is, although the error in the P 0 sequence 31 is corrected using the error correction code P 0 3 3, the data including the memory error 3 2 is reproduced, and then the error correction is properly completed, and the original cannot be restored. Use of information. If the memory error occurs in the data in the buffer memory on the reproduction side, it can cause the data including the memory error to be transferred to the host computer. (Target point of the present invention) This paper size is applicable to Chinese National Standard (CNS) A4 wash case (210X 297 mm), ... ⅠΦ ------ ΤΓ ------ (Please read the back Note: Please fill in this page again) -17- 579499 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (15) As mentioned above, the data in the memory is destroyed (or when an error occurs ), Although the error correction code is generated based on the data changed by the record error, and the data is read and subjected to an error correction process during the reproduction operation, and the data is recorded in a recording medium, the original The information cannot be correctly restored, although the information changed by the error is restored. When the data applied to the error correction memory is destroyed (or an error occurs), it may cause the error data to be transferred to the host computer. In order to prevent the data in the memory from being destroyed (or an error occurs), the memory that stores the data must be implemented by a structure that prevents the data from being destroyed, such as S-RAM. However, this structure is less suitable for cost considerations. Therefore, an object of the present invention is to provide a method and an apparatus for generating an error correction code without losing the original data, although an error occurs in a memory, and a recording apparatus, a reproduction apparatus, a transmission apparatus, and a receiving apparatus using the method and the apparatus . (Basic idea of the present invention) The error correction code generating system of the present invention includes a section of memory (for example, constituted by SRA M), a PI generating and adding mechanism for generating and adding PI, and a buffer memory as The PI adding data is stored, and the PO generating and joining mechanism is used to generate and join PI, a row of memory (for example, composed of SRAM), the PI correcting mechanism 睃 performs PI correction, and the PO correcting mechanism is used to perform PO correction. The system uses the segment memory to add an error correction code PI to the data, and stores the PI to add --------- a ------ IT ------ ψ n ( Please read the precautions on the back before filling out this page.) The scale of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) • 18- 579499 A7 ___B7 V. Description of the invention (16) Information to this buffer memory, Prior to transmitting the PI-added data or recording it on a recording medium, a p I correction is performed using a bank memory to correct a memory error. When the above processing is reproduced, the PI correction is performed again before data is transferred to the host computer, and memory errors can be corrected. Further, the error correction code generating system according to the present invention includes the segment memory, a PI generating and adding mechanism, a buffer memory, a po generating and adding mechanism, a PI correcting mechanism, and a PO correcting mechanism. The system uses segment memory to add the error correction phone number to the data to generate a data segment (PI addition data), stores the PI addition data to the buffer memory, and transmits the PI addition data or transfers it Before recording on a recording medium, the buffer memory is used to store the PI correction, thereby correcting the memory error. Printed by the Consumer Cooperative of the Bureau of Intellectual Property 1 of the Ministry of Economic Affairs In addition, the error correction code generation system of the present invention includes the PI generation and joining mechanism, buffer memory, P 0 generation and joining mechanism, column memory, PI correction mechanism, and P0 Calibration mechanism. The system uses the data stored in the buffer memory to generate an error correction code, generates a data block that adds the error correction code PI to the data (PI adds data), stores the block in the buffer memory, and self-buffers Before the PI is transmitted in the memory or recorded, the PI memory is used to perform p I correction to correct memory errors. And, the error correction code generating system of the present invention includes a segment memory, a PI generating and joining mechanism, a PO generating and extracting mechanism, a PI correcting mechanism, and a PI correcting mechanism. This system uses the error correction code p I to use this paper. The size of the paper applies to the Chinese National Standard (CNS) A4 (210X297 mm) -19. 579499 A7 B7. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (17) This Segment memory and add to the data to generate a data block (p J adds data), and store p I added data to the buffer memory, and transfer or record the PI added data from the buffer memory, After that, before transmitting the data to the host computer, PI correction is performed on the data added to the PI on the reproduction side, and data errors are corrected by this. Hereinafter, the characteristic parts of the present invention will be described with reference to the drawings using specific embodiments thereof. Referring to Fig. 10, an error correction code adding circuit in the data recording apparatus of the first embodiment of the present invention will be explained. User data (main data) transmitted from the autonomous computer are sequentially stored in the section memory 1. At this time, the section information adding mechanism 5 adds the 4-byte identification data (ID), the 2-digit ID error induction code (IED), and the 6-byte copyright management information (CPR-ΜΑ I) To the main data of 208 bytes. The EDC generates and joins the organization 6 for the data of a total of 260 bytes (including ID, IED, c P R_MA I), and mixes the error induction code of 4 bytes, and adds the error induction code to 2 0 6 0 byte data. The mixing mechanism 7 adds the mixed data to the main data of the 2048-bit leader (or to mutually exclusive the main data and the mixed data), thereby mixing the mixed data sections. The PI generating and adding mechanism 8 generates an error correction code PI (10 bits) for each row (172 bytes) of the mixed data section (or data block) stored in the section memory 1. Group), and the PI is added to the column, thereby generating 182 bytes X 12 columns of PI joining funds {please read the note on the back before filling this page) This paper size applies to China Standard (CNS) A4 Washer (210X297 mm) -20- 579499 A7 B7 Printed by the Employee Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs V. Invention Description (18) Material section (data block). The segment memory 1 has a capacity (18 bytes X 1 2 rows) for storing PI added data segments, and is composed of, for example, SR A M (static RAM). The SRAM has a structure in which errors can be rarely generated in the stored data. This ensures that the error correction code PI generated by using the sector memory 1 is the correct code generated by the user data without errors. The PI added data from the memory 1 (or the data block having 18 bytes X 1 2 rows is called a data block) are sequentially stored in the buffer memory 2. In the buffer memory 2, 16 data segments (PI adding data) having 182 bytes X 1 2 rows are grouped together to form a total of 182 bytes X 1 92 rows. PI joining Data (or sum data block). However, the P 0 generation and joining mechanism 9 generates one for each row (192 bytes) of the total data block (18 2 bytes X 1 92 columns) stored in the buffer memory 2. Error correction code P0 (16 bytes), and add this P0 to the line. As a result, the ECC block to which the error correction codes P I and P0 are added is constituted for the total data block stored in the buffer memory 2. The buffer memory 2 has a sufficient capacity, and maintains a plurality of E C C blocks to ensure the storage function of data transmitted from the autonomous computer until it is recorded on a recording medium and is composed of, for example, DRAM. It may happen that the data located in the memory is destroyed or a memory error occurs, depending on the connection state of the DRAM or the pattern of the data. Ran (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 size (210X29 * 7mm>) • 21-579499 Α7 Β7 Printed by the Employees ’Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs System 5. Description of the invention (19) Moreover, the data processing method according to the present invention will remove the billion-body error as described later. In the buffer memory 2, the ECC block is read in a row by a row (by 1 8 2 Bytes as a unit), and store it in row memory 3. The PI correction mechanism 10 uses the row of memory 3 to perform PI correction, thereby correcting the memory error and restoring the original data (or (Corrected ECC block). This row of memory 3 is composed of, for example, SRA M, and can store the capacity of a single row (182 bytes) of the PI sequence. The data output from row 3 is Sequentially sent to the modulation / synchronization adding mechanism 4, which processes 8/1 6 modulation and synchronization code addition, and outputs the resulting data when recording data to the recording medium. Figure 11 shows the output from the buffer memory Error in the data part of ECC block 2 Situation (such as error 42 due to external noise or the above-mentioned memory error). In the present invention, the error correction code PI is generated using data memory 1 before the data is stored in the buffer memory. Therefore, in all 192 columns including column 1 45, the error correction code PI is an error correction code generated based on the original data. That is, the error correction code PI is for data without error 42. On the other hand, the P 0 generation and joining mechanism is combined with the buffer memory 2, and an error correction code P is generated based on the data in each row (192 bytes). 0. Thus, the error correction code 4 4 (16 bytes) for line 4 1 is an error correction code generated based on the data including the memory error 4 2. ----------- ----- Order ------ (Please read the notes on the back before filling out this page) This paper size applies to Chinese national standards (CNS M4 specification (210X297 mm) -22- Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative 579499 A7 _B7_ V. Description of the invention (20) The product code is Part of the error correction code 4 8 (indicated by a circle), although the code PI is first generated and added, and then P0 is generated and added, or the code P 0 is generated and added first, and then the phone number PI is generated and added The same code pattern is obtained. Here, the error correction code PI is the correct error correction code added to the original data when an error occurs. Therefore, the error correction code P 0 is generated and added to the error correction code PI. It is the correct error correction code of the original data. In addition, the error correction code P0 (shown in FIG. 11) added to the other line (171) of line 4 1 of line 17 2 is a correct error correction code. When the E C C block is sequentially read from the buffer memory 2 and the PI correction is performed in the column memory 3, the error 4 2 in the column 4 5 can simply perform the PI correction. That is, columns 3 to 4 of the erroneous data are replied. Further, each column of the PO sequence generated from the data including the error 42 is also subjected to PI correction, and the correct PO sequence is returned. That is, the column 4 6 is subject to the P I correction, and the correction unit is a single byte 4 3. Similarly, the other columns (indicated by triangles) are subject to the P I correction and the correct P 0 sequence is generated. In the above processing, the PI correction is performed for all the columns in the ECC block in the column memory 3. The PI correction is not limited to this *, but can be applied to each column marked with a triangle mark to shorten the processing time. This is because the memory error 4 2 can be correctly corrected afterwards. If the P 0 sequence in the triangle position in the figure is the correct error correction code ® In the above explanation, it has been used in the sum data block. This paper size applies to China National Standard (CNS) A4 (210X297 mm) ------. --------- 1T ------ Office (please read the precautions on the back before filling in this purchase) -23- 579499 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (21) And the distributed ECC blocks of P 0. However, in the actual E C C block, the error correction code P0 is distributed one by one in the sum data block as shown in Fig. 1 and Fig. 6. Fig. 12 shows a reproduction mechanism for performing an error correction process on the E C C block obtained by the above-mentioned process (the process performed by the circuit of Fig. 10) and reproduction from a recording medium. The playback data read from the recording medium by the optical head is imported to the synchronous separation / demodulation unit 11 · The synchronous separation / demodulation unit Jun 1 1 senses the synchronization from the playback data and applies the 8/1 6 The modulated data is demodulated. The error can be included in the data of the recording section because of an error occurring in the data due to a disc defect or noise that is recorded or reproduced from a recording medium. The read-out recording sections are sequentially stored in the buffer memory 2, and 16 recording sections are put together to form an ECC having 182 rows X 2 0 8 columns in the buffer memory 2. Block. What? The 0 correction mechanism 14 and the PI correction mechanism 10 apply error correction to the E C C block having 182 rows and X 2 0 8 columns. However, the PI correction process may be performed before this PI correction process. The reason is that if a memory error occurs in the P 0 block, the P I correction can recover the correct error correction code P 0. The error correction E C C block is read from the buffer memory 2 (in 182-bit units) row by row in the order of data transmission, and is stored in the section memory 1. The PI correction mechanism 10 uses the segment memory 1 to perform PI correction in 172 bytes of each column. This (please read the precautions on the back before filling this page) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -24-579499 A7 _B7_ V. The description of the invention (22) is because the memory The error error occurs in the buffer memory 2 and exerts the P0 correction. The PI correction will effect the error when correcting the error. (Please read the note on the back before filling this page.) Next, the hybrid cancellation mechanism 1 3 will include the mixed data of the main data (2 0 4 bytes) in the mixed data section, X the mixed data. (Or the two data are mutually exclusive or), thereby generating a data section before mixing. After that, the EDC error sensing mechanism 12 uses a 4-byte error sensing code (EDC) included in the data sector to sense the error in the data sector. If it senses that there is no error in the data sector, the data The session will be transferred to the host computer. In the above explanation, when the data is stored in the segment memory 1 from the buffer memory 2, the PI correction mechanism 10 performs PI correction. Or, the PI correction is performed only when an error is sensed using EDC. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed further. In each column of the error pattern, the synonym (10 bytes) is detected. Only the part of the synonym is counted to detect an error, and only if its judgment is correct. When an error occurs, PI correction is performed. That is, in the error correction process using the error correction code PI, only the portion of the error pattern induced by the error correction code PI of the P byte (R byte, R < P) is calculated, and error sensing is performed. An error correction occurs only when an error occurs in its judgment. FIG. 13 shows another embodiment of the present invention. This embodiment is obtained by removing the memory 3 in the embodiment of FIG. 10. In the embodiment of FIG. 13, the PI correction mechanism 10 performs the PI correction using the buffer memory 3. Since the other structures are the same as those of the embodiment of Fig. 10, explanations will be omitted. When a memory error occurs, the paper size of P0 is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -25- 579499 A7 B7 V. Description of the invention (23) Error generation caused by joining and joining the organization The code P 0 becomes an error correction code generated based on data including memory errors. Performing PI correction on all the columns of the error correction code P 0 can return the error correction code P 0 generated based on the data including the memory error, to the error correction telephone number P 0 generated based on the original data. In this embodiment, since the EC C block after PI correction appears in the buffer memory 2, it may include a memory error. However, the error correction code P 0 was once returned to the error correction code generated based on the original code. Therefore, although the ECC block includes an error, the error will be corrected by the Po correction. FIG. 14 shows another embodiment of the present invention. The use data from the host computer is added to the single data section with the main data of 2048 bytes by the section information adding mechanism 15. The section information adding mechanism 15 adds 4 bytes. Identification data (ID), 2-byte ID error sensing code (IED), and 6-byte copyright management information (CP R_MA I) to the main data. The ED C generation and joining organization 16 generates a 4-byte error correction code (EDC) for a total of 260 bytes of data, and adds the brick to the latter, thereby generating a total number of 20 containing 6 4-byte data section. The mixing mechanism 17 mixes the main data into the data section. The mixed data segments are sequentially stored in the buffer memory 2. In this buffer memory 2, 16 data segments with 172 bytes X 1 2 columns are integrated to form a paper size with 172 rows and X 192 columns, which is applicable to Chinese national standards (CNS > Α4 specifications ( 210X297 mm) (Please read the “Notes on the reverse side before filling in this card”) Order the printed by the Consumer Cooperatives of the 1st Bureau of Smart Finance of the Ministry of Economic Affairs -26- 579499 A7 B7 V. Description of the invention (24) Information section. PI generation and The joining organization 18 receives the data segment from the hybrid organization 17 and then sequentially generates a 10-byte error correction code PI for each data column and sends the PI to the buffer memory 2. Results, In the buffer memory 2, a PI joining block having a column of 182 bytes X 192 is constructed. At this time, the error correction code PI is an error correction code generated based on the original data. The lower part is the same as the above embodiment, and is not repeated here. Fig. 15 is an error correction circuit corresponding to the error correction code generating circuit. This embodiment is almost the same as the embodiment of Fig. 12, except for the buffer memory 2 becomes column memory3. The PI correction mechanism Using the buffer memory 2 to perform error correction for at least a column including P 0 will cause the error correction code P 0 to become a correct error correction code. Then, the P 0 correction mechanism 14 performs a P 0 correction process. At P 0 After the correction process, the data is sent to the bank of memory 3 in the order of transmission. The PI correction mechanism 10 uses the bank of memory 3 to perform a correction. This allows the memory error to be corrected in the bank of memory 3. Correction, although the memory error occurred in the buffer memory during the P 0 correction. The mixing of the data output from the memory 3 is canceled by the mixable cancellation mechanism, and a data section is generated. "The data area The segment applies error sensing by the EDC error sensing mechanism 12. Figure 16 shows another embodiment of the present invention. This embodiment uses the buffer memory 2 of the embodiment of Figure 13 and the paper scale is adapted to Chinese national standards ( CNS) A4 Washer (210X297 mm) inn ϋ u ϋ nnn (Please read the notes on the back before filling out this page. Order printed by the Employees ’Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs-27 · 579499 Intellectual Property of the Ministry of Economic Affairs A7 B7 printed by the employee elimination cooperative. V. Invention description (25) Remove the PI correction mechanism 1 0. The rest is the same as the embodiment in FIG. 13. In this embodiment, when the regeneration system is constructed in the buffer The ECC block in the memory 2 performs error correction, and the PI correction mechanism 10 performs PI correction before P0 correction. As described above, the present invention can be applied to a signal that can perform error correction code generation processing without losing original data. Transmission / recording and reproduction device, even when errors occur in memory. Further, the present invention can be applied to an inexpensive signal transmission / recording and reproduction device, which can record data on a recording medium without losing original data, although it allows more memory errors instead of simplifying inspection of defective memory While increasing production capacity. The present invention can further be provided in devices of various transmission / reception systems in the field of digital transmission. It includes a wireless unit, such as a mobile phone, a transmitting / receiving end between computers, and a TV transmitter / receiver unit. In the field of recording and reproduction systems, the present invention can be applied to DVD units, CD units, and memory devices to which communication functions are further applied. As described above, with the present invention, it is possible to provide a data processing method that uses an error correction code that can recover the original data, although when a data error (memory error) occurs, use one of the methods to record or reproduce the system device, and Transmission and reception system using this method. The invention is not limited to the embodiments described above. Hereinafter, other embodiments of the present invention will be explained. In Fig. 17, the user data from the host computer is converted into a single data segment by using 2048 bytes as a unit by the segment information adding mechanism 15. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ------: --- 4 ------ 1T ------_ (Please read the precautions on the back first (Fill in this page again) -28- 579499 A7 B7 V. Description of the invention (26) f Please read the notes on the back before filling in this I ^ The section information is added to the organization 1 5 The 4-byte identification data (ί d ), 2-byte ID error induction code (I ED), and 6-byte copyright management information (CPR — MA I) are added to the main data (including 2048 bytes) 〃 EDC generation and joining institutions ι6 The total number of ID, IED, and CPR_MAI is 2060 bytes. A 4-byte error correction code (EDC) is generated. Blend; ^ Structure 17 Add the miscible data to the main data (208 bytes) (or by mutually exclusive of the main data and the miscible data), and the stomach mixes the main data. PI generation and joining mechanism 8 for each column (172 bytes) in the mixed data section (or data block) (172 bytes x 1 2 rows = 2 0 64 bytes) ) Generate an error correction code PI (10 bytes printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs). After that, the generated error correction code PI is sequentially stored in the buffer memory 2 through the memory control mechanism 20, and the 20 generates PI addition data with 182 bytes X 1 2 rows (data Block). This data processing is continued, and 16 data blocks of the error correction code PI are formed in the buffer memory 2. That is, in the buffer memory 2, 16 data segments (PI-added data) having 18 2 bytes X 1 2 rows are aggregated to constitute 1 82 bytes X 1 9 2 歹 [J The sum PI is added to the data (or the sum data block). The error correction code PI generated in the above process is a correct error correction code generated based on the original data. The P 0 generation and joining mechanism 9 applies the Chinese National Standard (CNS) A4 for each row and paper size of the total data block (18 2 bytes X 192 rows) stored in the buffer memory 2. Specifications (210X297 mm) -29- 579499 Α7 Β7 5. Description of the invention (27) (192 bytes) and an error correction code P0 (16 bytes) is generated. As a result, the ECC block added with the error correction codes PI and P0 is constructed for the total data block stored in the buffer memory 2. The buffer memory 2 has a sufficient capacity to hold a plurality of ECC blocks to ensure the function of storing and transmitting data of the autonomous computer until it is recorded on a recording medium, and is composed of, for example, DRAM. It may cause the data in the memory to be destroyed or a memory error to occur due to the joint state of the memory or the pattern of the data. When the error correction code P 0 is generated at this time, the error correction code P 0 becomes an error correction code generated based on the data including the memory error. The E C C block in the buffer memory 2 is read row by row (in units of 182 bytes) and stored in the row memory 3. The PI correction mechanism 10 uses the column memory 3 to perform PI correction, thereby correcting the memory error and recovering the original data (or the correct E C C block). The bank of memory 3 is composed of, for example, SR A M (static RAM), and can store a single row (182 bytes) of a PI sequence. The output data from the column memory 3 is sequentially sent to the modulation / synchronization adding mechanism 4, which processes 8/1 6 modulation and synchronization code addition, and outputs the result data as record data to the record media. Here, referring to FIG. 11 again, the functions of the above embodiment will be described. Figure 1 1 shows the situation where errors (such as the above-mentioned memory errors or errors caused by external noise 4 2) occur in the data portion of the E C C block output from buffer memory 2. This paper size applies Chinese National Standard (CNS) M specification (210X297 mm) n nn · I,-ulm > ^ n — / t-hr (Please read the precautions on the back before filling this page) Order the wisdom of the Ministry of Economic Affairs Printed by the Finance 4 Bureau Consumer Cooperative -30-579499 A7 B7 V. Description of the Invention (28) In the present invention, the error correction code PI is generated using data memory 1 before data is stored in buffer memory 2. Therefore, the error correction code PI in all the columns including 45 to 192 is an error correction code generated based on the original data. That is, the error correction code PI in FIG. 11 is an error correction code for the miserable data without error 42. On the other hand, the P0 generation and addition mechanism 9 and the buffer memory 2 are based on each line. (192 bytes) data to generate an error correction code P0. Therefore, the error correction code for column 4 1 (16 bytes) is an error correction code generated based on the data including the memory error 4 2. The error code is part 4 8 of the error correction code for the error correction code, although the code PI is first generated and added, and then the phone number P0 is generated and added, or the code P0 is first generated and added, and thereafter The code PI is generated and added to obtain the same code pattern. Printed by the Intellectual Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Here, the error correction code PI is the correct error correction code added to the original data before the error occurred. Therefore, the error correction code P 0 generated and added to the block of the error correction code P I is a correct error correction code generated based on the original data. However, the error correction code P 0 added to other lines (1 7 1) (not included in line 41 of line 1 72 shown in FIG. 11) is a correct error correction code. When the E C C block is sequentially read from the buffer memory 2 and the P I correction is performed in the column memory 3, the error 4 2 in the column 4 5 is simply applied with the P I correction. That is, the correct data list 4 5 is replied. Next step: For each of the P 0 rows generated by the incorrect data, the paper size is also applied to the Chinese National Standard (CNS) A4 specification (210X: 297 mm > ~ -31-579499 A7 B7 V. Description of the invention (29) (Please read the precautions on the back before filling this page) PI correction to restore the correct P 0 sequence. That is, the column 4 6 is applied with PI correction to correct a single bit. Group 4 3 is the same, the other columns (indicated by triangles) are applied with a PI correction to generate the correct P0 sequence. In the above processing, the PI correction uses column memory 3 and for all the ECC blocks The PI correction is not limited to this, but can be applied to each column marked with a sigma of the triangle to shorten the processing time. This is because the memory error 4 2 can be later Simple correction, if the p 0 sequence at the triangle position in the figure is the correct error correction code. In the above explanation, the ECC block of the P 0 block distributed one by one in the sum data block is used. At the timing In the ECC block, then The error correction code P 0 is a row-by-column distribution in the total data block as explained in Fig. 1 and Fig. 6. That is, the error correction code P 0 is distributed so that a single column of the error correction code P 0 is derived. Now it is in the 12-column data section. After that, the reproduction system of FIG. 17 will be explained. The Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperation Agreement will describe the function of the memory control mechanism 20. The memory control mechanism 20 Receive a request, and read from PI generation and joining mechanism 8, synchronous separation / demodulation mechanism 1 1, P0 generation and joining mechanism 9, P ◦ correction mechanism 9, PI correction mechanism 10, and column memory 3 Or store data. According to this request, the memory control mechanism 20 reads data from the buffer memory 2 or writes data to the buffer memory 2. At this time, the memory control mechanism 20 controls the data storage location Therefore, the standard of Chinese paper (CNS) A4 (210X297 mm) -32 · 579499 A7 B7 is applied without using this paper scale. 5. Invention description (31) and management can also be listed. Then, the explanation will be explained when PI correction Failed (or none Data reproduction during execution. When 6 or more memory errors occur in a single row, PI correction cannot be performed. When 6 or more memory errors occur in data in a single ECC block In this case, the PI calibration of P0 (16 columns) will fail. When an error exceeding the number of correctable errors is sensed during the PI calibration process, the used memory area is changed and the regeneration is completed. In this regeneration , The host computer is requested to transmit the data again. After that, the error correction code PI added data is stored in the buffer memory 20 through the memory control mechanism 20. At this time, the used memory area is caused by an error. An error area or a blank area different from the error area is replaced. When the number of errors exceeds the error correctable number in each column of the area where the error correction code P 0 is stored, the regeneration is performed in the following manner. At the time of the regeneration, the total data block (including the error correction code PI) of 192 rows X 1 92 bytes in the first storage area in the buffer memory 2 is moved to the buffer memory 2 In the second storage area. After each column is subjected to the P I correction process, the second storage area of the bit in the buffer memory 2 is used to perform the P 0 generation and addition process again. In this case, the regeneration can be performed within the system without requiring the host computer to transmit the data again. Figure 19 is a diagram to help explain the paper size of the data in the buffer memory 2 applicable to the Chinese National Standard (CNS) A4 wash (210X297 mm) (Please read the note on the back before filling this page) Order Printed by the Employees' Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs-34 · 579499 A7 _ B7 _ V. Description of Invention (32) Mobile. (Please read the precautions on the back before filling this page) The data moving mechanism 24 will start to move from the stored E C C block (η) of A 〇 to the blank area of the header address A3. At this time, the mobile data includes a memory error contained in the address A 0 area. Performing PI correction for each column will cause these memory errors to be corrected. The data using the PI correction process is applied, and the P0 generation and addition processes are performed. If the number of memory errors at this time is 5 or less, the generated error correction code P 0 can be corrected by PI correction processing. The operation of data reproduction will be described using FIG. 17. The playback data read from the recording medium by the optical head is introduced to the synchronization separation / demodulation mechanism 11 · The synchronization separation / demodulation mechanism 1 1 senses and separates synchronization from the playback data, and The data to which 8/16 modulation is applied is demodulated, thereby generating a recording section. Because the error occurred due to disc defects or noise while recording or reproducing data to / from the recording medium, the error can be included in the data in the recording section. The read-out recording sections are sequentially stored in the buffer memory 2 through the memory mechanism 20, and 16 recording sections are put together to form an ECC having 18 2 rows X 2 0 8 columns. Block in buffer memory 2. The P0 correction mechanism 14 and the PI correction mechanism 10 apply error correction to an ECC block having 208 rows and X182 columns. The error correction E C C block reads the buffer memory 2 row by row from the buffer memory 2 in the order of data transmission and stores it in the bank memory. The PI correction mechanism 10 uses column memory 3 and applies the Chinese National Standard (CNS) A4 specification (210X297 mm) for each column paper size -35 · 579499 Printed by A7 of the Consumer Finance Cooperative of the 1st Bureau of Smart Finance of the Ministry of Economic Affairs _ B7_V. The invention explains (33) that 1 72 bytes perform correction. As a result, although a memory error occurs in the miscible data section in the buffer memory 2, the error can be corrected by p I correction. Then, the blendable cancellation mechanism 13 mixes the blended data and the blended data of the main data (204 bytes) in the blendable data section (or mutually excludes or processes the two data) , Thereby generating a data section before mixing. After that, the EDC error sensing mechanism 12 uses a 4-byte error sensing code (EDC) included in the data sector to sense an error in the data sector. If it senses that it has no errors in the data section, the data section will be transferred to the host computer. As described above, the present invention can be applied to a signal transmission / recording and reproduction apparatus that can execute error correction code generation processing without losing data, even when an error occurs in the memory. Further, the present invention can be applied to an inexpensive signal transmission / recording and reproduction device capable of recording data to a recording medium without losing original data, although it allows rise in memory errors to occur instead of simplifying defective memory Increased by inspection. The present invention can be further applied to various transmission / reception system devices in the digital transmission field. It includes wireless units such as mobile phones, transmission / reception terminals between computers, and television transmitter / receiver units. In the field of a recording and reproducing system, the present invention can be applied to a DVD unit, a CD unit, and a memory device using a communication function. As described above, in the present invention, it can provide a data processing method using an error correction code that can recover the original data even when an error (memory error) occurs in the memory, and a method of recording or reusing the method. : II 4—, (Please read the precautions on the back before filling this page) The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -36- 579499 A7 B7 V. Description of the invention (34) System, and transmission and reception system using the method. —0 ------ 1T ------_ (Please read the notes on the back before filling out this page) The Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumer Cooperatives, printed this paper to apply Chinese National Standards (CNS) A4 size (210X297 mm) -37-

Claims (1)

  1. 579499 A8 B8 C8 D8 __ 夂, Application for Patent Scope No. 90 1 29 5 83 Chinese Patent Application Amendment (please read the notes on the back before filling out this page) Amendment on December 3, 1992 1. A data processing method using an error correction code, including T steps: For each row in a data block composed of (M X Ν) bytes in M columns X Ν rows, generating P bytes of The error correction code P I is added to the column using a first memory; K is placed in the M column X (N + P) row (M X (Ν + Ρ) ) The data blocks added with the error correction code PI are composed of bytes and are grouped together in a second memory to generate the total data including (K X (Μ X (Ν + Ρ))) Block; an S-byte error correction code P 0 is generated for each row of the sum data block, and the second memory is used to add the error correction code P 0 to the row to generate a Error correction generated code block (ECC block) The company prints an error correction process using the error correction code PI added to each column before reading from the second memory, and transmits the ECC block; and sequentially applies the ECC block in the order of the columns. The EC c block with the error correction process is transmitted or recorded to a recording medium. 2 · —A kind of data processing method using error correction code, including the step of τ: For the data consisting of (MX × N) bytes in column M × N—_ This paper size applies Chinese National Standard (CNS) Α4 specification (210X297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 579499 A8 B8 C8 D8 6. For each column in the patent application block, an error correction code PI of P bytes is generated and a A memory and add the error correction code PI to the column; add K (M X (N + P)) bytes in the M column X (N + P) row to add error correction The data blocks of code P I are grouped together in a second memory to generate a total data block containing (K X (MX (N + P))) bytes; for each of the total data blocks Each line generates an (S = κ XQ) byte error correction code P ◦, and uses the second memory to add the error correction code P 0 to the line to generate an error correction generation code block (ECC block); the error correction code P 0 is distributed in units of Q bytes The K data blocks to which the error correction code PI is added, so that each block constitutes an error correction code generation code block (ECC block), which is generated by the data and the error correction correction code. And includes a fixed frame of (M + Q) X (N + P) bytes; before reading from the second memory, an error correction is performed using the error correction code P I added to each column The ECC block is processed and transmitted; and the ECC blocks to which the error correction processing is applied are sequentially transmitted in a column order or recorded to a recording medium. 3. A data processing method using an error correction code, including the following steps: For each row in a data block composed of (M X Ν) bytes in the M column X Ν row, an error correction is generated Code P I and add it to this paper. Applicable Chinese National Standard (CNS) A4 specification (210X297 mm) 7 ^ 1Τ ------ (Please read the precautions on the back before filling this page) 579499 ABCD 6. The scope of patent application in this column; including a first process and a first process' the table and one process is that the autonomous computer receives the data in each row (including N bytes) and transmits the N bytes The data is sequentially stored in a second memory. The second process is parallel to the first process and generates a P-byte error correction code for each row based on the transmitted N-byte data. And the generated P-byte error correction code PI is sequentially stored to the brother * * in the thinking body, and the (M X (N + P)) byte in the M column X (NXP) row is generated. The data block formed by adding the error correction code P I; put K in the M column X (N + P) The data blocks composed of (Mχ (N + P)) bytes added with the error correction code P I are grouped together in a second memory to generate (K X (Μ X (N + P ))) Sum data block of bytes; For each row of the sum data block, an S-bit error correction code P is generated, and the second memory is used to generate the error correction code P. Added to the row to generate an error correction generation code block (ECC block); before reading from the second memory, an error correction process is performed using the error correction code Pl added to each column , And transmit the ECC block; and sequentially send the ECC block to which the error correction processing is applied in a column order or record to a recording medium. 4 · The data processing method of any one of the items 1, 2 and 3 of the scope of patent application, wherein when the error correction processing is performed according to the error correction code P I, the paper size applies the Chinese National Standard (CNS) Α4 specification (210X297 mm) )-(Please read the notes on the back before filling out this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -3- 579499 A8 B8 C8 D8 VI. Application scope of patents ^ When executed for this ECC block , Only the error correction code p ◦ is subject to error correction processing. (Please read the notes on the back before filling out this page) 5. If you want to process the data in any one of the items 1, 2 and 3 of the patent application, each column of the ECC block is from the second memory The data is sequentially read and stored in the third memory. When the error correction processing is performed on the unit block stored in the third memory according to the error correction code p I, the error correction processing is performed. The error correction is performed for each row of the data block stored in the third memory or the row of the error correction code P0, and the error correction is applied sequentially in accordance with the order of the rows. The processed unit block is transmitted or recorded to a recording medium. 6. A data processing method using an error correction code, including the following steps: when the (KX M X (N + P)) byte is added to the total data block with the error correction code Pl, and including ( SX (N + P) The error correction code P of the byte of the Intellectual Property Bureau of the Ministry of Economic Affairs (Printed by the Consumer Cooperative) ◦ When transmitted or read and received from a recording medium, the total data block is Put the data blocks composed of the (M X Ν) bytes in the M column X Ν together and include (KB X (Μ X Ν)) bytes in each column of the data block, add the P byte The error correction code P I and the error correction code P 0 block are generated for each row of the sum data block including the error correction code P I block, and the second memory is used according to the error correction code Ρ I and 〇 〇 The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 579499 A8 Β8 C8 ________D8 6. The scope of patent application is in the total information area Of the block Erroneous data blocks and performing a first error correction process; and using the first memory based on the error correction code and p I data while the first error correcting process of the error correcting process executed for the column is applied. 7-A data processing method using an error correction code, including the following steps: When an error correction generated code block (ECC block) is transmitted or received from a recording medium and received, the ECC block is Each column in the data block consisting of (M × N) bytes in the M column X N row generates a P byte error correction code P I, and K is added to the pair with the error correction code P I The data blocks composed of (M X (N + P)) bytes are placed together in the M column X (N + P) row, and the result contains (K X (Μ X (N + P))) Sum data block of bytes, and the (S = κ XQ) byte error correction code P 0 generated in each row of the sum data block is added to the row, and the error correction code ρ ◦ It is added to K data blocks with error correction code ρ I in units of Q, so that each data block is composed of a data and an error correction code, and contains (M + Q) x (N + P) fixed 値 of the byte, using the second memory according to the error correction codes ρ I and ρ 〇 Perform error correction processing on the error data bytes in the block, and then use the first memory according to the error correction code ρ I to perform a row of error correction processing on the data to which the first error correction processing is applied. This paper size applies to China's Θ standard (CNS) A4 (210X297 mm) ------ IT -----.— φ (Please read the precautions on the back before filling this page) 579499 A8 Β8 C8 D8 6. Application for Patent Scope 8. If the data processing method of the patent application scope item 6 or item 7 is used, the error correction processing using the first memory should be performed only if it (please read the precautions on the back first) (Fill in this page again) It is judged that the data with the error correction code (EDC) added to the data block is read from the second memory, and it is executed only when there is an error in the data block. 9 · A data processing method using an error correction code, including the following steps: For each row in a data block composed of (M XN) bytes in the M column XN row, a P byte error is generated Correction code PI, and use a first memory to add this error correction code PI to the column; the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs prints K in the M column X (N + P) row The data blocks composed of (Mχ (N + P)) bytes added with the error correction code P I are grouped together in a second memory to form (K X (Μ X (Ν + Ρ) ))) Sum data block of bytes, and generate an S-bit error correction code ρ for each row in the sum data block, and use the second memory to correct the error P 0 is added to the row to form — error correction generated code block (ECC block); before the ε c C block is praised and transmitted from the table-one memory, the An error correction code P for each column is performed, and an error correction process is performed; in order of the columns, For the ECC blocks to which the error correction process is applied, sequentially transmit or record the ECC to a recording medium; when the ECC blocks to which the error correction process is applied are transmitted or read from a recording medium and received, Use the second memory according to the error correction codes PI and PO, and for the error correction in the data block, use the Chinese National Standard (CNS) A4 specification (210X297 public address) 579499 Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative prints A8 Βδ C8 D8 holes, applies patents to carry out data bytes and performs a first error correction process; and uses the first memory according to the error correction code p I to apply With the data of the first error correction process, a row of error correction processes is performed. 1 0 · —A data processing method using an error correction code, including the following steps: For each row in a data block composed of (M XN) bytes in M columns XN rows, generating P bytes The error correction code ρ I is used, and a first memory is used to add the error correction code Pl to the column to form a total data block; K is placed in the M column X (N + P) row The data blocks composed of (Mχ (N + P)) bytes added with the error correction code P I are grouped together in a second memory to form (K X (Μ X (Ν + Ρ) ))) Sum data block of bytes, and generate an (S = κ XQ) byte error correction code P for each row in the sum data block, and use the second memory The error correction code P0 is added to the row; the error correction code P0 is distributed in the Q bytes as a unit among K data blocks added with the error correction code PI to constitute an error correction. Generate code blocks (ECC blocks) so that each data block consists of a data block and an error correction code (M + Q) X (N + P) bytes are fixed; before the ECC block is read from the second memory and transmitted, the error of using each column added to the ECC block is used Calibration code P 1 'and this paper size applies Chinese National Standard (CNS) Α4 specification (210X297 mm) -7-(Please read the precautions on the back before filling out this page) 579499 Α8 Β8 C8 D8 6. Scope of implementation of patent application An error correction process; (please read the precautions on the reverse side and fill in this page) in order of listing, and for the ECC blocks to which the error correction process is applied, transfer them in order, or record the ECC to a recording medium; When the ECC block to which the error correction processing is applied is transmitted or read from a recording medium and received, the second memory is used according to the error correction codes PI and P. For the data in the data block, Performing a first error correction process on the error correction data bytes; and performing a row of errors on the data to which the first error correction process is applied by using the first memory according to the error correction code PI Correction processing. 1 1 · If the data processing method of item 9 or 10 of the scope of patent application, the error correction process uses the second memory, and the first error correction process uses the second memory according to the error The correction codes PI and P are performed before the error correction data block in the data block is executed, and according to the error correction code PI, the error data bytes including memory errors are executed during recording. 1 2 · If the scope of patent application is No. 1,2,3,6,7,9, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and any of the data processing methods in Item 10, the first memory system Is SRA M (static R M). 1 3 · If the data processing method of any one of the items 1, 2, 3, 6, 7, 9, and 10 of the scope of the patent application, the error correction processing using the error correction code P I is performed by The part of the pattern sensing frame (P byte) of the error correction code P I obtained from the P byte (R byte, R < P) is calculated, and an error is induced, and only if it is judged -8-This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 579499 Printed by A8, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs C8 ______ D8 VI. A correction process is performed only when the scope of the patent application is judged to be incorrect. 14. A data processing device, when the data with an error correction code is transmitted or recorded on a recording medium, it uses a data processing method such as any one of claims 1, 2 and 3 in the scope of patent application. Get the added error correction code data. 1 ··· A kind of data processing device, when the data with the error correction code is transmitted or read from a recording medium and received, it is obtained by using the data processing method such as the scope of patent application No. 6 or 7. Added error correction code data. 1 6 · —A kind of data processing device, when the data with the error correction code is transmitted or recorded on a recording medium, or when the data with the error correction code is transmitted from a recording medium or read and received , And use data processing methods such as those in the scope of patent application for item 9 or 10 to obtain data with error correction codes or output data after error correction. 1 7 · A data processing device using an error correction code, comprising:-generating a P byte error for each row in a data block composed of (M XN) bytes in a M column XN row Correct the code P I and use a first memory to add the error correction code P I to the mechanism y in the column. An assembly mechanism will put K (M X (M X ( N + P)) bytes of data blocks added with error correction code P 1 are grouped together in a second memory to generate (κ χ (Μ χ (Ν + Ρ))) bytes The organization of the sum data block; a s byte error for each row of the sum data block (please read the notes on the back before filling this page) This paper uses the Chinese national standard ( CNS) A4 specification (210X297 mm) -9-579499 ABCD 々 、 Scope of patent application (please read the precautions on the back before filling this page) Error correction code P ◦Use the second memory to use the error correction code P 0 is added to the row to generate an error correction generation code block (ECC block); A mechanism for performing an error correction process and transmitting the ECC block using an error correction code PI added to each column before reading from the second memory; and a sequence to be applied with the The ECC block for error correction processing is transmitted or recorded to a recording medium. 1 8. A data processing device using an error correction code, including:-for each column in a data block composed of (M XN) bytes in M columns XN rows, generating P bytes of A mechanism that adds the error correction code PI to the column using a first memory; a group of K in the M column X (N + P) row (M X (N + P) _) bytes of data blocks added with the error correction code Pl are grouped together in a second memory to generate (K X (Μ X (N + P))) bytes The organization of the sum data block; the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints an error correction code P that generates one (S = κ XQ) byte for each row of the sum data block and uses the second A memory to add the error correction code P to the row to generate an error correction generation code block (ECC block); a mechanism to distribute the error correction code P to Q bytes The K data blocks added with the error correction code PI make each block constitute an error correction correction The organization that generates the code block (ECC block). The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 579499 A8 Βδ C8 ___ D8. 6. The scope of patent application for generating code blocks is caused by data and errors. The correction code is composed of (M + Q) X (N + P) bytes. (Please read the precautions on the back before filling this page.)-Before reading from the second memory A mechanism for performing an error correction process using the error correction code PI added to each column and transmitting the ECC block; and sequentially transmitting the ECC block to which the error correction process is applied in a column order or It is a mechanism for recording to a recording medium. 1 9 · A data processing device using an error correction code, comprising: generating an error correction code P I for each column in a data block composed of (M X Ν) bytes in M columns X Ν rows And add it to the column; the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a mechanism including a first process and a second process, the first process is received by each computer in each row (including N bits Group), and store the transmitted N-byte data in a second memory in order. The second process is parallel to the first process and for each of the N-byte data according to the transmitted N-byte data. To generate a P-byte error correction code 'and store the generated P-byte error correction code PI to the second memory in sequence, and generate the P-byte error correction code in the M column X (NχP) row. (Mχ (N + P)) bytes of data block added error correction code PI; a K (Mx (N + P)) bits in the M column X (N + P) row The data blocks formed by the tuples and added with the error correction code PI are grouped together in a second memory to A mechanism that generates a total data block containing (K X (MX (Ν + Ρ))) bytes; an error that generates an S byte for each row of the total data block. Paper size applies to China National Standard (CNS) A4 Specification (210X297 mm) -11-579499 Printed by A8 B8 C8 D8 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the patent application scope error correction code P 0 and using the second memory A mechanism for adding an error correction code P0 to the row to generate an error correction generation code block (ECC block);-using the error correction code PI added to each column before reading from the second memory, and A mechanism for performing an error correction process and transmitting the ECC block; and a mechanism for sequentially transmitting or recording the ECC block to which the error correction process is applied in a listed order to a recording medium. 2 0. The data processing device of any one of claims 17, 18, and 19 as claimed in the patent application, wherein when error correction processing is performed on the ECC block according to the error correction code PI, 'only The error correction code P 0 is subjected to error correction processing. 2 1. The data processing device according to any one of claims 17, 18, and 19 of the scope of patent application, further comprising: one sequentially reading each column of the ECC block from the second memory. The mechanism for storing the column in the third memory is as follows: when the error correction processing is performed on the unit block stored in the third memory according to the error correction code PI Each of the rows of the data block stored in the third memory or one of the rows of the error correction code P0 is executed and the error correction process will be applied sequentially in accordance with the order of the rows An organization that transmits or records the unit block to a recording medium. 2 2. —A data processing device using an error correction code, including: When the (KX M X (N + P)) byte is included, an error-corrected paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297) (Centi) Tl2 _ (Please read the notes on the back before filling out this page) 579499 A8 Βδ C8 D8 VI. The total data block of the positive code PI in the patent application scope, and the (SX (N + P)) byte When the error correction code P 〇 is transmitted or read and received from a recording medium, the total data block is used to place K data blocks composed of (M X Ν) bytes in the M column XN row. Together, each column of the data block containing (K X (Μ X Ν)) bytes is added with a P-byte error correction code PI and the error correction code P 0 block is included for error correction. Generated by each row of the sum data block of the code P I block, using a second memory according to the error correction codes P I and Po, and for the erroneous data block in the sum data block, A mechanism that performs a first error correction process; and A mechanism that uses a first memory and performs a row error correction process on the data to which the first error correction process is applied according to the error correction code PI. 2 3. —A data processing device using an error correction code, including: When an error correction generated code block (ECC block) is transmitted or received from a recording medium and received, the ECC block is Each column in the data block composed of (M X Ν) bytes in the row X Ν generates a P byte error correction code P I, and K is added to the error correction code P I for Data blocks composed of (Μ X (Ν + Ρ)) bytes are placed together in row Column X (Ν + Ρ) to generate (K X (Μ X (Ν + Ρ))) bits. The sum data block of the tuple, and the (S = κ XQ) byte error correction code P 0 generated in each row of the sum data block is added to the row, and the error correction code ρ is This paper uses China National Standard (CNS) A4 specifications (210X297 mm) -13-— (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 579499 A8 B8 C8 D8 VI. Scope of Patent Application (Please read the notes on the back before filling this page) Q is added as a unit to K data blocks added with error correction code p I, so that each data block is composed of a data and error correction code 'and includes (M + Q) x (N + P ) A fixed bit of bytes, a mechanism that uses a second memory to perform error correction processing for the erroneous data bytes in the data block based on the error correction codes p I and P, and a use A mechanism for performing a series of error correction processing on the data to which the first error correction process is applied according to the error correction code PI. 2 4 · If the data processing device in the scope of patent application No. 22 or No. 23, wherein the error correction processing using the first memory, only when it is judged that it is read from the second memory and added The error correction code (EDC) is the data in the data block, and it is executed only when there is an error in the data block. 2 5. A data processing device using an error correction code, including: printed by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in a data block composed of (M XN) bytes in the M column XN row Each column generates an error correction code ρ I of P bytes and uses a first memory to add the error correction code PI to the mechanism in the column. One K is in the M column X (N + P) row. The data blocks composed of (M X (N + P)) bytes added with the error correction code P I are grouped together in a second memory to form (K X (M X (N + P ))) Sum data block of bytes, and generate an S-bit error correction codebook for each row in the sum data block. Paper size applies to China National Standards (CNS) Α4 specification (210X297) (%) "14 · 579499 A8 B8 C8 D8", patent application scope P ◦ and using the second memory to add the error correction code P0 to the row to form an error correction generation code block (ECC block ) Organization (please read the notes on the back before filling this page) An ECC block performs an error correction process using the error correction code P added to each column of the ECC block before reading and transmitting from the second memory; The ECC block of the error correction process sequentially transmits or records the ECC to a recording medium; and when the ECC block to which the error correction process is applied is transmitted or read from a recording medium and received, the first Two memories and a mechanism for performing a first error correction process on the error correction data bytes in the data block according to the error correction codes PI and P 0; and The error correction code PI is a mechanism that performs a series of error correction processing on the data to which the first error correction processing is applied. 2 6 · —A data processing device using the error correction code, including: the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Print an error correction code P I for each row in a data block made up of (M XN) bytes in M columns XN rows and A first memory is used to add the error correction code PI to the column to form a total data block mechanism; an executive mechanism stores K in the M column X (N + P) row (M The data blocks added with the error correction code PI are composed of X (N + P)) bytes and are grouped together in a second memory to form (K X (Μ X (N + P))) bits. The sum of the data blocks of the tuples also applies the Chinese national standard (CNS > A4 specification (210X297 mm)) for the sum of capital and travel standards. 579499 A8 B8 C8 D8 6. Scope of patent application (Fill in this page) each row in the data block generates an (s = KXQ) bit error correction code P 0 and uses the second memory to add the error correction code P 0 to the institution in the row; An error correction code p 0 is distributed among K data blocks with an error correction code PI in units of Q bytes to form an error correction generation code block (ECC block) such that each data region The block contains (M + Q) X (N + P ) A fixed frame mechanism of bytes; an error correction is performed using the error correction code PI of each column added to the ECC block before the ECC block is read from the second memory and transmitted. A processing organization; an organization that sequentially transmits or records the ECC to a recording medium for the ECC block to which the error correction process is applied in a listed order; when the ECC block to which the error correction process is applied is transmitted or When read from a recording medium and received, the second memory is used to perform a first error correction process on the error correction data bytes in the data block according to the error correction codes PI and PO. Institutions; and the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a * by using the first one * sH 彳 thinking body, according to the error correction code PI, a row of errors is performed on the data to which the first error correction process is applied Correction processing mechanism. 2 7 · If the data processing device in the 25th or 26th of the scope of patent application, further includes a mechanism for performing the error correction process, the process uses the second memory, and the first error correction process Use the second memory and apply the Chinese National Standard (CNS) A4 specification (210X297 public envy) to the paper according to the error correction codes PI and P0. 1679499 Employee Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs A8 B8 C8 D8 is printed. Before the patented error correction data block is executed, it is executed according to the error correction code PI for the error data bytes including memory errors during recording. 28. The data processing device according to any one of claims 17, 18, 19, 22, 2 3, 25, and 26, wherein the first memory system is S R A M (static R R M). 2 9. The data processing device according to any one of claims 17, 18, 19, 22, 2, 3, 25 and 26, wherein the error correction code PI is used to execute the data processing device. The mechanism for error correction processing is to sense the part (R byte, R byte) of the pattern (P byte) of the error correction code PI from the P byte. < P) is calculated, and an error is induced, and a correction process is performed only when it judges that there is an error. 30. A data processing device comprising: a mechanism for generating an error correction code PI in each row of a data block and storing both the error correction code PI and the data block in a memory; and A mechanism for performing an error correction process when a data block added with an error correction code PI is read from the memory in a transmission or recording system and is located in the column of the data block according to the error correction code PI. . 3 1. A data processing device including an error correction for a column of the total data block when the total data block is read from the memory when an error correction process is applied using the error correction code PI. A mechanism that executes the error correction process again with the code PI. This paper size applies to China National Standards (CNS) A4 (210X297 mm). 17-IT (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 579499 A8 B8 C8 ___ D8 VI. Patent Application Range 3 2-A data processing device using an error correction code, including: PI generating and joining mechanism, as each of a plurality of data rows containing N bytes in a single row, generating an error The correction code p I (including P bytes), and the error correction code PI is added to the column; ~ the buffer memory is used to store the added error correction code PI obtained by the PI generation and addition mechanism, so that a single column The N + P byte p I error correction mechanism is used to correct errors in each row using an error correction code p I added to each row before reading and transmitting the data from the buffer memory. ; And a memory control mechanism, as before the p I error correction mechanism performs error correction, and when error data is sensed, the memory area in the buffer memory The information to be memory, and when an error is repeated sensing of data is stored, the memory region and to the other substituent in the buffer memory area in the memory. 3 3 · —A data processing device using an error correction code, including: p I generating and joining mechanism, which will send each computer in a single column to cover each of the multiple N columns in a single column, generating -An error correction code PI (including p bytes) and adding the error correction code PI to the column; a buffer memory for storing the added error correction code p I generated by the PI generation and adding mechanism, The single column contains the N + P byte P0 generating and joining mechanism, as the kappa number is added with the error correction codebook. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -18- (Please read first Note on the back then fill out this page) 579499 A8 B8 C8 D8 x, apply for patents (please read the notes on the back before filling out this page) The data blocks of P〇 are assembled, each data block is in the Column X (N + P) in the Column M is composed of (M X (N + P)) bytes to form a data block containing the sum of (K X (Μ X (N + Ρ))) bytes. , And generate one for each row in the sum data block S byte error correction code P ◦, and adds the error correction code P 0 to the row to form an error correction generation code block (ECC block); Pl error correction mechanism, as the Before the data is read from the buffer memory and transmitted, the errors in each row are corrected using the error correction code PI added to each row; and a control mechanism, as the number of correctable errors of its sensing errors has exceeded When the P I error correction mechanism performs error correction, the error correction code P I from the host computer is added again, and this data becomes the data added with the error correction code P I, and when the stored error correction code is stored, When the data of PI is in the buffer memory, a second storage area different from the first storage area in which the data was previously stored is designated. 3 4 · —A data processing device using an error correction code, including: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a PI generating and joining organization, which will send the majority of the N computers in a single row as an autonomous computer For each column in the data column, an error correction code PI (including P bytes) is generated, and the error correction code PI is added to the column; a buffer memory is used to store the information generated by the PI generation and addition mechanism. The added error correction code P I makes a single row contain N + P bytes P ◦ The generation and joining mechanism is used to add K pieces with the error correction code -19- This paper applies Chinese National Standard (CNS) A4 Specifications (210X297 mm) 579499 A8 BS C8 _______ D8 VI. Patent application scope (please read the precautions on the back and fill in this note) The data blocks of P 0 are assembled, and each data block is in column M x The (N + P) line is composed of (M X (N + P)) bytes to form a data block containing the sum of (K X (MX (N + P))) bytes. In each of the sum data blocks An S-bit error correction code P0 is generated, and the error correction code P is added to the row 'to form an error correction generation code block (ECC block); the P I error correction mechanism serves as Before the data is read from the buffer memory and transmitted, the error correction code P I added to each column is used to correct the errors in each column; and a control mechanism is provided when the error correction mechanism When the errors in the column of the error correction code P ◦ are corrected, and when the number of correctable errors is detected / exceeded, the contained (K X (Μ X (N + P))) The total data block of the byte is generally consistent in the second region in the buffer memory, and is generated and joined by the P0, and for the second region in the second region, Each row in the sum data block containing (K X (MX (N + P))) bytes generates an S-byte error correction code P0. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 5. A data processing device using an error correction code, including: When an error correction code P I is included in the (K X MX X (N + P)) byte When the sum data block and the error correction code P 0 containing (SX (N + P)) bytes are received from the transmission mechanism or the recording medium, the sum data block is suitable for the K by The data blocks composed of X Ν rows (M X Ν) bytes are put together and each row of the data block containing the total (K X (Μ X Ν)) bytes is added to the P byte error paper. Standards: China National Standards (CNS) A4 specifications (210 × 297 mm): 20- 579499 A8 B8 C8 D8 VI. Patent application range correction code P 1 'and the error correction code P ◦ The block is for including error correction Code p I is generated for each row of the total data block. (Please read the precautions on the back before filling this page.) The first mechanism is to use a buffer memory based on the error correction codes PI and P. 0 for errors in that sum data block To perform a first error correction process on the data byte; the second mechanism 'uses a small memory with a smaller capacity than the buffer memory' and according to the error correction code PI, and for the first error correction process The data in the rows, and perform a second error correction process; and _. The memory control mechanism, when the error data is sensed when stored, and the second mechanism performs error correction in the PI sequence, it will The information is stored in the memory area of the buffer memory, and when data with repeated sensing errors is stored, another memory area is used to replace the memory area in the buffer memory. 3 6 · —A data processing device using an error correction code, including: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs When an error correction generated code block (ECC block) is received from a transmission agency or recording medium, Each column of the data block formed by the (M XN) bytes of the M column XN generates a P byte error correction code P I and adds the error correction code P I to the row, and K for M The data block added with the error correction code P I formed by the (M X (N + P)) bytes in the row X (N + P) is placed together to generate a block containing (κ X (Μ XN + Ρ )) The total data block of bytes, and an (S = κ XQ) byte error correction code P is generated for each row in the total data block and added to the row, and This error correction code-21 This paper size is in accordance with China National Standard (CNS) A4 specification (21〇 × 297 mm) 579499 Α8 Β8 C8 D8 6. The scope of patent application P 0 is distributed in units of Q bytes. K data blocks with PI error correction code added, so that each data A block is a data block composed of data of a fixed frame containing (M + Q) x (N + P) bytes and an error correction code. The first mechanism is to use a buffer memory according to the error correction code. Pl and 〇 and perform a first error correction process on the erroneous data bytes in the sum data block; the second mechanism uses a small memory with a smaller capacity than the buffer memory 'according to the An error correction code PI, and execute a second error correction process for the rows in the data buried at the place where the first error correction is applied; and the 'memory control mechanism, which is stored as the data when an error is sensed Time 'and when the second mechanism performs error correction in the PI sequence, the information is stored in the memory area of the buffer memory, and when the data of repeated sensing errors is stored, another memory area is used. Replace the memory area in the buffer memory. --------------- 、 Order ------ 0 (Please read the notes on the back before filling out this page) The paper size printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Applicable Chinese National Standard (CNS) Α4 Specification (210X297 mm) _ 22-
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