579499 Α7 Β7 經濟部智慧財1局員工消费合作社印製 五、發明説明（彳） 發明背景 本發明係相關於一種有效使用將視頻資料、音頻資料 或是電腦資料記錄於一媒體（像是光碟或是磁碟）或將記 錄在媒體上之資料再生之錯誤校正碼產生方法。 本發明進一步相關一種錯誤校正碼產生方法，有效傳 送或是接收視頻資料等。 本發明進一步相關於一種記錄裝置、一再生裝置、以 及一接收裝置，其採用錯誤校正碼產生方法。 本發明特別之特徵在於使用一緩衝記億體在執行錯誤 校正處理之錯誤校正方法。 當視頻資料、音頻資料、電腦資料等被記錄在例如光 碟或是磁碟時，錯誤校正碼被加入至資料區塊。在該錯誤 校正碼加入處理中，資料區塊係暫時被儲存在一記憶體中 ，而產生資料區塊之列以及行之錯誤校正碼。 加至列之錯誤校正碼一般係稱爲內部同位（parity)且 簡稱爲P I 。加至行之錯誤校正碼一般係稱爲外部同位（ parity)且簡稱爲P 0。 在該錯誤校正碼加入處理中，當資料區塊在產生錯誤 校正碼之前，而被暫時儲存於記憶體中時，在記憶體中之 資料的一部份可能被損毀（或是可能發生一錯誤）。該損 毀可歸因於記憶體之接合狀態或是資料圖樣。此外，外部 突然之雜訊亦爲其缺點。 此時所發生之錯誤稱爲記憶體錯誤。 此時，在發生記憶體錯誤之資料區塊之錯誤校正碼（ (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） -4- 579499 A7 B7 經濟部智慧財1局員工消资合作社印製 五、發明説明（2 ) 此後稱爲經改變之資料區塊）被產生。該錯誤校正碼被加 入至經改變之資料區塊，且將所產生之區塊記錄在一記錄 媒體中。 當資料自該記錄媒體而被再生時，錯誤校正電路使用 該錯誤校正碼而在經改變之資料區塊上執行一錯誤校正處 理。即，經改變之資料區塊被正確的再生。即，包括該記 憶體錯誤之資料區塊已經被正確的再生。然而，該記憶體 錯誤對於原始資料係爲不必要的。 於是，當發生記憶體錯誤時，而無法正確回復該原始 資料。 發明之簡要敘述 於是，本發明之目的在提供一種使用可在當資料錯誤 (記憶體錯誤）發生在記憶體中時而可正確回復原始資料 之錯誤校正碼之資料處理方法，採用該方法之記錄系統或 是再生系統單元，以及使用該方法之傳輸系統以及接收系 統。 以下爲本發明之錯誤校正碼處理方法之基本觀念。 本發明之特徵在於該傳輸或是記錄系統對於具有矩陣 結構之資料區塊之每個列產生一錯誤校正碼p I ，並儲存 錯誤校正碼p I以及資料區塊於記憶體中，且當錯誤校正 碼P I加上加入之資料區塊自記憶體中而被讀取時，該錯 誤校正處理係根據錯誤校正碼PI而在資料區塊之列中而 執行。 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS )八4说格（210X：297公釐） -5- 579499 A7 B7 經濟部智慧財產局員工消资合作社印製 五、發明説明（3 ) 進一步，本發明之特徵在於當藉由資料錯誤校正碼P I而施加錯誤校正處理之矩陣結構資料區塊自記億體中而 讀取時，接收或是再生系統再次對於每個區塊之列而使用 錯誤校正碼PI而執行錯誤校正處理。 特別是，當在記憶體（第一記憶體）中儲存資料時， 本發明事先使用一分離之第二記憶體（具有不損壞資料之 結構之記憶體），而產生一錯誤校正碼PI並將所產生資 料結合該資料而寫入至該第一記憶體。 之後，在K區段（sector )之資料以及P I已經被儲存 於該第一記憶體中時，錯誤校正碼P 0對於資料以及P I 而產生，並加入至其中。當該資料自該第一記憶體中而被 讀取時，在每次取出P I系列時，而執行P I校正處理。 此可使資料回復至其原始狀態，儘管造成在第一記憶體之 資料之毀損（或是記憶體錯誤發生）。 在再生該資料時，該所再生之資料被暫時儲存在該記 憶體中，而執行該P I以及P 0錯誤校正處理。當在記憶 體中之資料在錯誤校正處理之後而被送出時，該P I錯誤 處理再次對於讀取自該第一記憶體之資料執行。此可使資 料回復至其原始狀態，儘管造成對於記憶體中之資料之傷 害（或是記憶體錯誤發生）。 進一步，本發明之目的在提供一種資料處理裝置，其 可正確回復該原始資料，儘管在記憶體中發生資料錯誤（ 或是記憶體錯誤），且藉由使用記憶體之方法而確保操作 之可靠性。 ------：ίL#--------订------#1 (请先Μ讀背面之注意事項再填寫本買) 本紙張尺度適用中國國家標準（CNS > Α4規格（210Χ297公釐） -6 - 579499 經濟部智恶財4局β工消費合作社印製 A7 _B7_五、發明説明（4 ) 特別是，本發明之特徵在於，傳輸或是記錄系統對於 具有矩陣結構之資料區塊中之每個列而產生一錯誤校正碼 P I ，並將該錯誤矯正碼P I以及資料區塊儲存在記憶體 中，而當經加入錯誤碼P I之資料區塊自該記憶體中而被 讀取時，而根據錯誤校正碼P I而在資料區塊中列而執行 錯誤校正處理。 之後，當使用錯誤校正碼P I而執行錯誤校正處理時 感應到有無法校正之錯誤時，儲存相關列或是資料區塊之 記憶體區塊將被改變，而避免記憶體錯誤之發生。且，發 生記憶體錯誤之區域經學習而不再使用。 圖形之簡要敘述 圖1展示在DVD中得到實體區段（sector )之資料處 理之解釋圖； 圖2展示在DVD之資料區塊中之組態之解釋圖； 圖3係作爲產生混合（scramble )資料之回饋移位暫存 器之解釋圖； 圖4係展示E C C區塊之解釋圖； 圖5係展示記錄區段之解釋圖； 圖6係展示使錯誤校正碼P 0交錯知E C C區塊之解 釋圖； 圖7係一方塊圖，以解釋習知記錄與再生單元中之記、 錄系統中之錯誤校正碼產生方法； 圖8係一方塊圖，作爲解釋在習知記錄與再生單元中 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 579499 A7 B7 經濟部智慈財產局員工消費合作社印製 五、發明説明（5 ) 之再生系統之錯誤校正碼產生方法； 圖9係爲一圖以解釋在習知記錄與再生單元中發生 D RAM記憶體錯誤時之錯誤校正碼； 圖1 0爲一記錄系統之方塊圖，以解釋本發明之錯誤 校正碼產生方法之實施例； 圖1 1爲展示本發明之錯誤校正碼產生方法所得之 ECC區塊之資料結構之解釋圖； 圖1 2係一再生系統之方塊圖，以解釋本發明之錯誤 校正碼產生方法而得之在E C C區塊中之中之錯誤校正方 法之一個實施例； 圖1 3係爲一記錄系統之方塊圖，以解釋本發明之錯 誤校正碼產生方法之另一實施例； 圖1 4係爲一記錄系統方塊圖，以解釋本發明之錯誤 校正碼產生方法之另一實施例； 圖15係爲本發明之錯誤校正碼產生方法而得之在 E C C區塊中校正錯誤之方法之另一實施例； 圖1 6係爲一記錄與再生系統之方塊圖，以解釋本發 明之錯誤校正碼產生方法以及使用錯誤校正碼而校正錯誤 之錯誤校正碼之實施例； 圖1 7係爲一記錄系統與再生系統之方塊圖，以解釋 本發明之錯誤校正產生方法之另一實施例； 圖1 8A以及1 8B係爲一解釋圖，以展示在藉由本 發明之錯誤校正碼產生方法而處理資料時，包括緩衝記憶 體之記憶體圖以及記憶體錯誤之E C C區塊之資料串；以 (請先閲讀背面之注意事項再填寫本頁) -訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8 - 579499 A7 B7 五、發明説明（6 ) 及 圖1 9係爲一解釋圖，以展示包括本發明之錯誤校正 碼產生方法之記憶體錯誤之E C C區塊之處理之另一個例 子0 (請先Μ讀背面之注意事項存填寫本頁) 訂 元件對 照 表 2 0 1 緩 衝記憶體（D R A Μ ) 2 0 2 區段資訊加入機構 2 0 3 Ε D C產生與加入 機構 2 0 4 混合機構 2 0 5 Ε C C記憶體（D R A Μ ) 2 0 6 Ρ I產生與加入機構 2 0 7 Ρ 0產生與加入機 構 2 0 8 調 變/同步加入機 構 發明之 詳 細描述 此 處 ，參考附圖 ，而解釋本發明 之 實 施例 經濟部智慧財產局員工消費合作社印製 使用DVD (數位多功能碟片）爲例子，而參考圖1 至圖8而解釋在記錄與再生單元中之錯誤校正電路以及錯 誤校正碼加入電路之組態。 首先，參考圖1至圖6，而解釋記錄在DVD上之資 料結構。 圖1展示資料處理之順序而在D V D中得到實體區段 。區段根據信號處理之階段而稱爲％資料區段"、、記錄 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公嫠) " - -9- 579499 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（7 ) 區段〃、或是％實體區段〃。如圖2所示，資料區段包括 2 0 4 8位元組之主要資料、4位元組之辨識資料（I D )、2位元組之ID錯誤感應碼（IED)(作爲在感應 在I D中之錯誤之碼）、6位元組之著作權管理資訊（ CPR_MAI)、以及4位元組之錯誤感應信號（ EDC)(作爲感應在此資料區段中之錯誤之信號0加入 ID、IDE、CPR — MAI以及EDC之步驟，係爲 圖1中之步驟A 1至步驟A3。在步驟A 1中ID被加入 至主要資料。在步驟S2中，IED被進一步的加入。此 外，在步驟S3中，加入CPR — MAI。 接著，而計算主要資料之EDC。該EDC被加入至 主要資料。之後混合資料被加入至資料區段中之主要資料 (包含2048位元組）（步驟A4、A5、A6)。之 後，在混合資料之後而將1 6個資料區段放一起。一橫跨 之雷德所羅門（Reed-Solomon)錯誤校正碼被產生並加入至 16個資料區段（步驟A6)。該記錄區段（ECC加入 區段）係爲加入有錯誤校正碼PI以及錯誤校正碼P〇之 資料區段（步驟A7)。該實體區段係爲一施加8/16 修正，而使同步碼（SYNC碼）加入至記錄區段中之交 錯9 1位元組之標頭處（步驟A8)。 使用圖2，而解釋DVD資料區段之結構。 資料區段包含包括有2 0 4 8位元組長之主要資料或 是有1 72位元組X 12列之2064位元組。即’一個 資料區段包括2 0 4 8位元組之主要資料、4位元組之辨 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠) ------r--I — (請先W讀背面之注意事項再填寫本頁) 訂 -10- 579499 A7 B7 經濟部智慧財1局員工消旁合作社印製 五、' 發明説明（8 ) 1 I 識 資 料（I D )、2 位元組之I D 錯誤 感 應 碼 ( I E D ) 1 1 I % 6 位元組之著作權 管理資訊（C P R Μ A I ) 以 及 4 1 1 位元組之錯誤感應碼 (E D C )。 1 I 請 1 1 圖3展示在步驟 A 4中產生作 爲混 合 主 要 資 料 ( 包 含 先 聞 1 1 讀 1 2 0 4 8位元組）之 混合資料S k 之回 饋 移 位 暫存 器 〇 例 背 1 I 如 資料區段之I D 之部分係使用 作爲 起 始値 以 產 生 混 合 注 1 I 資 料 S k。該混合資 料S k係使用 作爲 混 合 資 料 !〇□ 段 之 主 事 項 再 1 1 4 要 資 料（2 0 4 8位 元組）。結果 ，在 混 合 之 後 之 主 要 資 填 寫 本 料 D k ’係爲將S k (k爲〇至2 0 4 7 ) 與 D k 之 互 斥 頁 1 1 和 之 結果。 1 | 參考圖4而描述] E C C區塊之結構。 1 I 資料區塊經形成 而具有1 7 2 行X 1 9 2 列 9 每 個 包 1 訂 I 含 1 7 2位元組X 1 2列之1 6個 資料 區 段 〇 雷 德 所 羅 門 1 1 I 錯 誤 校正碼經產生並加成1 7 2行X 19 2 列 〇 首先 f 1 1 1 6 位元組錯誤校正 碼P 0被產生 並加 入 至 每 個 1 7 2 行 1 1 中 〇 在P 0序列之每 個行中包含1 9 2 位 元 組加 上 1 6 位 1 m 元 組 ，而爲2 0 8位 元組。接著， 10 位 元 組 之 錯 誤 校 正 1 1 I 碼 P I被產生而加入至每個包括錯誤校正碼 Ρ 〇 之 列 之 1 2 0 8列。該經加入 錯誤校正碼P I之 1 8 2 行 X 2 0 8 1 1 列 形 成一 E C C區塊 。儘管當產生 P〇 以 及 P 1 之 順 序 反 1 1 向 > 亦可得到相同之碼圖樣。 1 | 在E C C區塊之 縱向之一行係稱爲 P 0 序 列 9 而 在橫. 1 I 向 之 一列稱爲P I序 列。P 0序列 包含 1 9 2 位 元 組加 上 1 1 I 1 6 位元組，或是2 0 8位元組。 在單 一 Ρ 〇 序 列 中 > 可 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11- 579499 經濟部智慧財4局員工消費合作社印製 A7 B7_五、發明説明（9 ) 偵測最多至8位元組長之錯誤。而p 1序列包含1 7 2位 元組加上10位元組，或是182位元組。在單一PI序 列中，可校正最多爲5位7C組之錯誤。 接著，參考圖5以及6而解釋記錄區段之結構。 在由20 8列X 1 82行所構成之ECC區塊，構成 錯誤校正碼P 0之1 6列係以個別列至列而分離。該分離 列係在1 9 2列資料區段之1 2列之交錯處而被一個一個 的插入，而造成如圖6所示之建構。此稱爲P 〇之列交錯 (interleave)。因此，在列父錯之後之E C C區塊係由 1 6組1 3列X 1 8 2位元組所構成（=P I加入資料（ 對於1 2列）加上P 〇 (對於一列））° 如圖5所示，記錄區段係爲由P I加入資料資料（對 於1 2列）加上P 〇 (對於一列）所構成’即爲，1 3列 X 1 8 2位元組。在列交錯知後之E C C區塊係由1 6個 記錄區段所構成，如圖6所示。 實體區段係爲使得在1 3列X 1 8 2位元組之記錄區 段中（2 3 6 6位元組）而將同步（SYNC)碼加入至 每個列之9 1位元組之交錯處之標頭，而開始自列0而一 列一列的實施調變。藉由將S Y N C碼加入至9 1位元組 資料之標頭而得到者，係爲SYNC框。因此，實體區段 係由1 6群組X兩個SYNC框而構成。 參考圖7與8，而解釋在資料記錄單元中之錯誤校正 碼加入電路。 在圖7中，傳輸自主電腦之使用者資料係依序儲存在 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐) ' -12 - -------—Mm—— (請先閲讀背面之注意事項再填寫本筲) 訂 579499 A7 B7 經濟部智慈財產局員工消貪合作社印製 五、發明説明（1〇) 緩衝器記憶體2 0 1 ·當自緩衝器記憶體2 〇 1中讀取時 ’所儲存之使用者資料由區段資訊加入機構2 〇 2、 EDC產生與加入機構203，以及混合機構204所處 理。該處理係在2 0 4 8位元組主要資料之交錯處而執行 ，而將該資料轉換爲單一資料區段。 該區段資訊加入機構2 0 2將4位元組之辨識資料（ 1 D ) 、2位元組之I D錯誤感應碼（I e D )以及6位 元組之著作權管理資訊（CPR — ΜΑ I )加入至主要資 料中。該ED C產生與加入機構2 0 3產生並加入4位元 組之錯誤感應碼（EDC )至整個2 0 6 0位元組資料中 ，而產生整個爲2 0 6 4位元組之資料。該混合機構 2 0 4將該主要資料混合於該資料區段中。 該經混合之資料區段係依序儲存在E C C記憶體 205·在該ECC記憶體205中，而形成172行X 192列之資料區段，172位元組χ12列之16個資 料區段（sector)之集合。P I產生與加入機構2 0 6以及 P 0產生與加入機構2 0 7產生並加入錯誤校正碼至 172行X 192列資料區塊中，而產生一 ECC區塊（ block) 〇 之前所解釋之E C C區塊，係施以列交錯，且之後傳 送至調變/同步加入機構2 0 8 .該調變/同步加入機構 2 0 8將該8位元輸入資料轉換爲1 6位元碼字元而於輸 入之列交錯EC C區塊。即，產生8/1 6之調變。之後 ，SYNC碼被加入至9 1位元組之輸入資料之交錯處標 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） L0------、玎------ (請先聞讀背面之注意事項再填寫本頁) -13- 579499 經濟部智慧財產局員工消贲合作社印製 A7 B7五、發明説明（11 ) 頭，而形成一實體區段。該形成之實體區段被傳輸作爲記 錄資料並記錄於一媒體中。 現在，解釋錯誤校正碼之效果。 包括錯誤感應與感應機構之資料再生系統係再生記錄 資料。當錯誤發生在再生處理之再生實體區段中之資料時 ，此機構使用錯誤校正碼而校正在錯誤包含E C C區塊中 之錯誤。該錯誤感應與校正機構可回復該原始E C C區塊 而不會有其校正能力範圍內之錯誤。 參考圖8，解釋在資料再生側之錯誤產生方法。在自 記錄媒體處讀取之播放資料係藉由同步分離/調變機構 2 2 1而與同步碼分離之後，該8/1 6調變資料被解調 變，而解壓縮該記錄區段。因爲錯誤會由於該碟片中之瑕 疵、雜訊、顫動、串音（crosstalk)等而發生在記錄或是再 生該記錄資料，因此該播放資料將包括有些錯誤。 該讀出記錄區段係依序儲存在E C C記憶體2 0 5， 因此構成由1 6個記錄區段之1 8 2行X 2 0 8列之 已（：（：區塊。？〇校正機構2 2 2以及？1校正機構 22 3對於1 8 2行X 1 92列之ECC區塊執行錯誤校 正，而校正在播放信號中之錯誤。 該P I校正機構2 2 3對於ECC區塊之每個列計算 錯誤圖樣感應値多義字（s y n d r 〇 m e )。假如感應 出一錯誤，則執行錯誤校正。當原始資料係被再生而無錯 誤時，該多義字取得0之値。當錯誤發生在記錄或是傳輸 信號時，該多義字取得由表示錯誤發生位置之錯誤位置以 ^紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐1 "" (請先閱讀背面之注意事項再填寫本頁) -14- 579499 at _B7_ 五、發明说明（12) 及表示錯誤狀態之錯誤圖樣所決定之値。 該P0校正機構2 2 2自記憶體2 0 5中讀取在P序 列之2 0 8位元組資料，並對於該資料執行特定操作。當 同義字經操作結果而不變成0時，該P 0校正機構對於該 序列執行錯誤校正。當該經校正之資料被施以錯誤計算時 ，藉此而使在產生該錯誤校正碼時而回復該資料時，該同 義字取得0之値。上述操作係對於E C C區塊之1 8 2所 有1 8 2位元組而執行。 當長度爲8位元組或是更多之錯誤出現在一序列時， 該P0校正機構2 2 2無法校正錯誤。此時，然而因爲該 P I校正機構2 2 3可對於P I序列執行最多5位元組之 錯誤校正，假如包括在單一 P 0序列之錯誤長度，在P 0 校正執行於1 8 2行之時係爲5位元組或是更短，則錯誤 可被校正。 進一步，P 0校正與P I校正之重複將可校正單一次 P 〇校正以及單一次P I校正無法校正之錯誤。當所有同 意自具有0之値時，E C C區塊之錯誤校正被完成。 經濟部智慧財產局員工消費合作社印製 該錯誤校正E C C區塊被傳輸至混合取消機構2 2 4 。該混合取消機構2 2 4將混合資料加入（或是將該混合 資料予以互斥或）至混合資料區段中之2 0 4 8位元組長 之主要資料，而取消主要資料之混合並儲存在緩衝記憶體 2 0 1中之結果資料。 E D C錯誤感應機構2 2 5根據包括在資料區段中之 4位元組錯誤感應碼（e D C )而感應在資料區段中之錯 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 579499 經濟部智葸財產局員工消費合作社印製 A7 ___B7_五、發明説明（13 ) 誤。當錯誤被感應時，該區段被再次再生。該儲存在緩衝 記憶體2 0 1中之資料區段係被依序傳輸至該主機。 低價且大容量之DRAM (動態RAM)，係使用作 爲緩衝記憶體205，201 ·因爲DRAM之結構，其 取決於記憶體之接合狀態或是資料之圖樣，而使在記憶體 中之資料被毀壞（或是記憶體錯誤發生）。在位在記憶體 中之資料部份被毀壞時（或是記憶體錯誤發生）且該資料 區塊被改變時，當錯誤校正碼P I、P 0被產生以及加入 時，該錯誤校正碼P I、PO對於由記憶體錯誤所改變之 資料將成爲該校正錯誤校正碼。當具有對於所改變資料而 產生之錯誤校正碼之E C C區塊被記錄而之後被再生時， 該經改變之資料被再生，儘管該錯誤校正處理在再生之後 而被執行。 當記憶體錯誤3 2發生在具有1 7 2位元組X 1 9 2 列之資料區塊3 2之部分以及該區塊被改變之情形，將參 考圖9而予以描述。 首先，PO產生與加入機構9對於每個1 7 2行而產 生一錯誤校正碼P 0，並將該P 0加入至該行中。對於行 3 1之該錯誤校正碼PO 3 3 ( 1 6位元組）係根據該記 憶體錯誤3 2所改變之資料而被產生。 接著，P I產生與加入電路8產生一個1 0位元組錯 誤校正碼P I至包括該錯誤校正碼P 0之每個1 0 8列中 ，並將該P I加入至該列。該對於列3 4而產生之錯誤校 正碼P 136 (10位元組）將根據該記憶體錯誤32所 ------:---MW------、1T------ (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16 - 經濟部智慧財產局員工消旁合作社印製 579499 A7 ___B7_ 五、發明説明（14) 改變之資料而被產生。 進一步，對於1 6列之錯誤校正碼P 0所產生之錯誤 校正碼P I 3 7係根據包括由記憶體錯誤3 2而改變之資 料所產生之錯誤校正碼P 0 3 3之資料而被產生。 結果，適當之錯誤校正碼被加入至記憶體錯誤3 2所 改變之資料區塊中。此時，對於包括錯誤3 2之2 0 8列 之P I序列之所有錯誤圖樣感應値同義字以及對於1 8 2 行之P0錯誤之該同義字取得0之値，結果，該E CC區 塊被認爲係無錯誤。實際上，然而，在E C C區塊之原始 資料已經被記憶體錯誤3 2所改變。 此處，係考慮該根據所改變資料區塊而產生之E C C 區塊予以記錄至一記錄媒體並於之後自該媒體而再生該區 塊之播放資料。 該播放資料係使用錯誤校正碼而施加一錯誤校正處理 。此處，發生在再生資料中之錯誤係在該校正能力之範圍 內而被校正，藉此而回復播放資料。然而，包括記錄前之 記憶體錯誤無法被校正。即，儘管在P 0序列3 1中之錯 誤係使用錯誤校正碼P 0 3 3而被校正，包括記憶體錯誤 3 2之資料被再生，且之後該錯誤校正被適當完成，而無 法回復該原始使用資料。 假如記憶體錯誤發生在位於再生側之緩衝記憶體中之 資料時，其可使包括記憶體錯誤之資料被傳輸至主電腦。 (本發明之目標點） 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X 297公釐） ,· — ΙΦ------ΤΓ------ (請先W讀背面之注意事項再填寫本頁) -17- 579499 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（15) 如上述，當位在記憶體中之資料係被毀壞（或是當錯 誤發生），儘管錯誤校正碼根據記億體錯誤所改變之資料 而被產生，且該資料被讀取並在再生操作時而被施加一錯 誤校正處理，而記錄該資料於一記錄媒體中，該原始資料 無法被正確回復，雖然由該錯誤所改變之資料被回復。 當施加至錯誤校正之記憶體中之資料被毀壞（或是錯 誤發生），其可能使得該錯誤資料被傳輸至主電腦。 爲了避免記憶體中之資料被毀壞（或是發生錯誤）， 作爲儲存該資料之記憶體必須藉由可避免資料被毀壞之像 是S - RAM等之結構之記憶體而實施。然而此結構對於 成本考量係較不佳。 於是，本發明之目的在於提供一種方法以及裝置以產 生一錯誤校正碼而不丟失該原始資料，儘管錯誤發生在記 憶體，以及使用該方法以及裝置之記錄裝置、再生裝置、 傳輸裝置以及接收裝置。 (本發明之基本槪念） 本發明之錯誤校正碼產生系統，包含一區段記憶體（ 例如由S R A Μ所構成者），Ρ I產生與加入機構以產生 與加入Ρ I ，緩衝記憶體作爲儲存Ρ I加入資料，Ρ〇產 生與加入機構作爲產生與加入Ρ 〇，一列記憶體（例如由 SRAM構成），PI校正機構睃執行PI校正，以及 P〇校正機構作爲執行P 0校正。該系統使用該區段記憶 體以加入一錯誤校正碼P I至該資料中，儲存該P I加入 ---------a------IT------ψ n (請先w讀背面之注意事項再填寫本頁) 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •18- 579499 A7 ___B7 五、發明説明（16 ) 資料至該緩衝記憶體，在傳輸該P I加入資料或將之記錄 於記錄媒體之前而使用列記憶體而執行p I校正，藉此以 校正記憶體錯誤。 在上述處理之再生時，該P I校正係在資料被傳輸至 主電腦之前而再次執行，而可校正記憶體錯誤。 進一步，根據本發明之錯誤校正碼產生系統，包含該 區段記憶體、P I產生與加入機構、緩衝記憶體、p〇產 生與加入機構、P I校正機構、以及P0校正機構。該系 統使用區段記憶體以將錯誤校正電話號碼加入至該資料以 產生一資料區段（PI加入資料），儲存該PI加入資料 至該緩衝記憶體，在傳輸該P I加入資料或是將之記錄於 一記錄媒體之前，使用該緩衝記憶體而儲存該P I校正， 藉此而可校正記憶體錯誤。 經濟部智慧財1局員工消費合作社印製 此外，本發明之錯誤校正碼產生系統包含該P I產生 與加入機構、緩衝記憶體、P 0產生與加入機構、列記憶 體、P I校正機構、以及P0校正機構。該系統使用儲存 在緩衝記憶體中之資料而產生錯誤校正碼，產生將錯誤校 正碼P I加入至該資料（P I加入資料）之資料區塊，儲 存該區塊於該緩衝記憶體，在自緩衝記憶體中傳輸或是記 錄該P I加入資料之前而使用列記憶體而執行p I校正， 藉此而校正記憶體錯誤。 且’本發明之錯誤校正碼產生系統，包含區段記憶體 、P I產生與加入機構、P0產生與摘入機構、P I校正 機構，以及P 0校正機構。該系統將錯誤校正碼p I使用 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -19· 579499 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（17 ) 該區段記憶體而加入至該資料，以產生一資料區塊（p J 加入資料），而將p I加入資料儲存至該緩衝記憶體，自 該緩衝記憶體而傳輸或記錄該PI加入資料，之後，在傳 送資料至主電腦之前而對於在再生側之PI加入資料執行 PI校正，且藉此而校正資料之錯誤。 此後，本發明之特徵部份將參考附圖而使用其具體實 施例而將以描述。 參考圖1 0，將解釋本發明之第一實施例之資料記錄 裝置中之錯誤校正碼加入電路。傳送自主電腦之使用者資 料（主要資料）係依序儲存在區段記憶體1中。此時，區 段資訊加入機構5將4位元組之辨識資料（I D )、2位 兀組之ID錯誤感應碼（IED)、以及6位元組之著作 權管理資訊（C P R — ΜΑ I )加入至2 0 4 8位元組之 主要資料中。EDC產生與加入機構6對於總共爲 2 0 6 0位元組之資料（包括I D，I E D， c P R_MA I )而摻哼4位元組之錯誤感應碼，並將該 錯誤感應碼加入至2 0 6 0位元組之資料中。混合機構7 將混合資料加入至2 0 4 8位元組長之主要資料中（或是 以將主要資料與混合資料予以互斥或），藉此而摻哼混合 資料區段。 P I產生與加入機構8對於儲存於區段記憶體1中之 混合資料區段（或是資料區塊）之每個列（1 7 2位元組 )產生一錯誤校正碼PI(1〇位元組），並將該PI加 入至該列，藉此而產生1 8 2位元組X 1 2列P I加入資 {請先聞讀背面之注意Ϋ項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） -20- 579499 A7 B7 經濟部智慈財產局員工消費合作社印製 五、發明説明（18) 料區段（資料區塊）。 該區段記憶體1具有儲存P I加入資料區段之容量（ 1 8 2位元組X 1 2列），並係由例如S R A Μ (靜態 RAM)所構成。該SRAM具有可很少在儲存資料中發 生錯誤之結構，如此保證了使用該區段記憶體1所產生之 錯誤校正碼PI係爲使用者資料所產生之正確碼而沒有錯 誤。 該來自記憶體1之P I加入資料（或是具有1 8 2位 元組X 1 2列而稱爲資料區塊），係依序儲存於緩衝記憶 體2。在緩衝記憶體2中，具有1 8 2位元組X 1 2列之 1 6個資料區段（P I加入資料）經集結一起而構成 1 8 2位元組X 1 9 2列之總和P I加入資料（或是總和 資料區塊）。 然而，該P 0產生與加入機構9對於儲存在緩衝記憶 體2中之總和資料區塊（1 8 2位元組X 1 9 2列）中之 每一行（1 9 2位元組）產生一錯誤校正碼P0 ( 1 6位 元組），並將該P0加入至行中。結果，加入有錯誤校正 碼P I、P0之ECC區塊對於儲存在緩衝記憶體2中之 總和資料區塊而構成。 該緩衝記憶體2具有一足夠之容量，而保持多數個 E C C區塊而確保儲存傳送自主電腦之資料之儲存功能， 直到其被記錄於一記錄媒體，且係由例如DRAM所構成 。其可能發生位在記憶體中之資料被毀壞或是記憶體錯誤 發生，其取決於DRAM之接合狀態或是資料之圖樣。然 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐〉 • 21 - 579499 Α7 Β7 經濟部智慧財1局員工消費合作社印製 五、發明説明（19) 而，根據本發明之資料處理方法將如後述而移除該記億體 錯誤。 在緩衝記憶體2中E C C區塊係以一列一列而讀取（ 以1 8 2位元組爲單元），並將之儲存於列記憶體3 ·該 PI校正機構10使用該列記憶體3而執行PI校正，藉 此而校正該記憶體錯誤，而回復該原始資料（或是校正 E C C區塊）。該列記憶體3係由例如S R A Μ所構成， 並可儲存Ρ I序列之單一列（1 8 2位元組）之容量。 輸出自列記憶體3之列資料係被依序送至調變/同步 加入機構4，其處理8/1 6調變與同步碼加入，並在當 記錄資料至該記錄媒體時，而輸出該結果資料。 圖11展示輸出自緩衝記憶體2之ECC區塊之資料 部份所發生之錯誤之情形（像是由於外部雜訊所造成之錯 誤42或是上述記憶體錯誤）。 在本發明中，錯誤校正碼Ρ I係在資料儲存於緩衝記 憶體之前而使用資料記憶體1而被產生。因此，在包括列 1 4 5之所有1 9 2列中，該錯誤校正碼Ρ I係爲根據原 始資料而產生之錯誤校正碼。即，該錯誤校正碼Ρ I係對 於無錯誤4 2之資料而產生之錯誤校正碼。 另一方面，該Ρ 0產生與加入機構，與緩衝記憶體2 結合，而根據在每個行中之資料（1 9 2位元組）而產生 一錯誤校正碼Ρ 0。如此，對於行4 1之錯誤校正碼4 4 (1 6位元組）係爲根據包括記憶體錯誤4 2之資料所產 生之錯誤校正碼。 ----------------訂------ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS M4規格（210X297公釐} -22- 經濟部智慧財產局員工消費合作社印製 579499 A7 _B7_ 五、發明説明（20 ) 產生（product)碼係在錯誤校正碼之部分4 8 (以圓 圈標號標示），儘管碼PI係被首先產生與加入，之後 P〇被產生與加入，或者碼P 0被首先產生與加入且之後 電話號碼P I被產生與加入，而得到相同碼圖樣。 此處，該錯誤校正碼P I係爲在錯誤發生時加入至原 始資料之正確的錯誤校正碼。因此，被產生與加入至錯誤 校正碼P I之該錯誤校正碼P 0係爲原始資料之正確的錯 誤校正碼。且，加入至不包括17 2行中之行4 1之其他 行（171)之錯誤校正碼P0 (如圖11所示），係爲 正確的錯誤校正碼。當此E C C區塊自該緩衝記憶體2而 依序讀取，且P I校正係在列記憶體3中執行時，在列 4 5之錯誤4 2係可簡易執行P I校正。即，錯誤資料之 列3 4被回復。進一步，對於包括錯誤4 2之資料所產生 之P 0序列之每個列亦予以施加P I校正，而回復正確的 P〇序列。即，該列4 6係予以施加P I校正，而校正單 一位元組4 3 ·相同的，其他列（以三角形標示）係施加 與P I校正，而產生該正確之P0序列。 在上述處理中，P I校正係對於在列記憶體3中之 ECC區塊中之所有列而執行。該PI校正並不限於此* 而可對於標計有三角形記號之位置之每個列而發生效果， 以縮短處理時間。此係因爲該記憶體錯誤4 2可在之後被 正確校正，假如在圖中之三角形位置之P 0序列係爲正確 的錯誤校正碼® 在上述解釋中，已經使用在總和資料區塊中一列一列 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ------.---------1T------辦 (請先閱讀背面之注意事項再填寫本買) -23- 579499 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（21 ) 而分佈之P 0之E C C區塊。但是，在實際之E C C區塊 中，錯誤校正碼P0係如圖1與圖6而在總和資料區塊中 而一列一列的分佈。 圖1 2展示一再生機構，作爲在由上述處理（由圖 1 0之電路所執行之處理）而得E C C區塊上而執行一錯 誤校正處理以及自一記錄媒體而再生。 該由光學頭而自記錄媒體讀取之播放資料係被導入至 同步分離/解調變機構11·該同步分離/解調變機俊 1 1感應來自於播放資料之同步化，並將施加有8/1 6 調變之資料予以解調變。因爲由於碟片瑕疵或是在自記錄 媒體予以記錄或再生資料之雜訊而在資料上發生之錯誤， 因而該錯誤可被包括在記錄區段之資料中。 該讀出記錄區段係被依序儲存在緩衝記憶體2，且 1 6個記錄區段係被放置一起，而形成具有1 8 2行X 2 0 8列於該緩衝記憶體2中之E C C區塊。該？0校正 機構1 4以及P I校正機構1 0將具有1 8 2行X 2 0 8 列之E C C區塊施加錯誤校正。 然而，可在該P 0校正處理之前而執行P I校正處理 。其係因爲，假如係在P 0區塊中發生記憶體錯誤，P I 校正可使正確的錯誤校正碼P 0回復。 該錯誤校正E C C區塊係以資料傳輸之順序而一列一 列的自緩衝記憶體2中讀取（以182位元爲單位），並 儲存於該區段記憶體1中。該P I校正機構1 〇使用區段 記憶體1而在每個列之172位元組中執行PI校正。此 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -24 - 579499 A7 _B7_ 五、發明説明（22 ) 係因爲，當記憶體錯誤錯誤發生在緩衝記憶體2而發揮 P0校正，該P I校正將在校正該錯誤而發生功效。 (請先閲讀背面之注意Ϋ項再填寫本頁) 接著，混合取消機構1 3，將在經混合資料區段中主 要資料（2 0 4 8位元組）之經混合資料，X該混合資料 (或是將該兩資料予以互斥或），藉此而在混合之前而產 生一資料區段。之後，EDC錯誤感應機構1 2使用包括 在資料區段中4位元組錯誤感應碼（E D C )而感應在資 料區段中之錯誤β假如其感應出在資料區段中無錯誤，則 該資料區段將被傳送至主電腦。 在上述解釋中，當資料係自緩衝記憶體2而儲存至該 區段記憶體1中，該Ρ I校正機構1 0執行Ρ I校正。或 者，該Ρ I校正只有在使用EDC而感應錯誤時而執行。 經濟部智慧財產局員工消费合作社印製 進一步，在每個列之錯誤圖樣之感應値同義字（1 0 位元組），只有同義字之部分被計算以感應一錯誤，且只 有當其判斷有錯誤出現時，而執行Ρ I校正。即，在使用 錯誤校正碼Ρ I之錯誤校正處理中，只有得自Ρ位元組之 錯誤校正碼Ρ I之錯誤圖樣感應値之部分（R位元組，R < Ρ )被計算，而執行錯誤感應。只有當其判斷有錯誤出 現時，而發生錯誤校正。 圖13展示本發明之另一實施例。 此實施例係藉由移除圖1 0實施例之列記憶體3而得 。在圖1 3之實施例中，該Ρ I校正機構1 0使用緩衝記 憶體3而執行ΡI校正。因爲其他之架構係與圖10實施 例者相同，而將解釋省略。當發生記憶體錯誤時，由Ρ0 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210Χ297公釐） -25- 579499 A7 B7 五、發明説明（23 ) 產生與加入加入機構所產生之錯誤校正碼P 0變成根據包 括記憶體錯誤之資料而產生之錯誤校正碼。對於錯誤校正 碼P 0之所有列而執行P I校正，可使根據包括記億體錯 誤之資料而產生之錯誤校正碼P 0回復至根據原始資料所 產生之錯誤校正電話號碼P0。 在此實施例中，因爲在P I校正之後之E C C區塊係 出現在緩衝記憶體2中，其可包括記憶體錯誤。然而，該 錯誤校正碼P 0曾經回復至根據該原始碼而產生之錯誤校 正碼。因此，儘管該ECC區塊包括一錯誤，該錯將由 P〇校正所校正。 圖14展示本發明之另一實施例。 來自於主電腦之使用資料藉由區段資訊加入機構15 而以2 0 4 8位元組之主要資料而被加入至單一資料區段 〇 該區段資訊加入機構1 5加入4位元組之辨識資料（ ID) 、2位元組之ID錯誤感應碼（IED)、以及6 位元組之著作權管理資訊（C P R_MA I )至該主要資 料。ED C產生與加入機構1 6對於總數爲2 0 6 0位元 組之資料產生4位元組之錯誤校正碼（EDC)，並將該 磚加入至後者，藉此而產生包含總數爲2 0 6 4位元組之 資料區段。混合機構1 7將主要資料混合至該資料區段。 該經混合之資料區段被依序儲存在緩衝記憶體2中。 在該緩衝記憶體2中，將具有1 7 2位元組X 1 2列之 16個資料區段整合，而形成具有172行X192列之 本紙張尺度適用中國國家標準（CNS > Α4規格（210X297公釐） (請先《讀背面之注意事項再填寫本霣) 訂 經濟部智慧財1局員工消費合作社印製 -26- 579499 A7 B7 五、發明説明（24 ) 資料區段。 P I產生與加入機構1 8接收來自於混合機構1 7之 資料區段，之後對於每個資料列依序產生1 〇位元組之錯 誤校正碼PI ，並將該PI送至該緩衝記憶體2·結果， 在緩衝記憶體2中，具有1 8 2位元組X 1 9 2列之P I 加入區塊被建構出。此時該錯誤校正碼P I係爲根據該原 始資料而產生之錯誤校正碼。因爲剩下部份係爲於上述實 施例相同，在此而不贅述。 圖15係爲對應於錯誤校正碼產生電路之錯誤校正電 路。 此實施例幾乎與圖1 2之實施例相同，除了緩衝記憶 體2變成列記憶體3 ·該P I校正機構使用緩衝記憶體2 而對於至少包括P 0之列而執行錯誤校正，其將使該錯誤 校正碼P 0變成正確的錯誤校正碼。接著，P 0校正機構 1 4執行P 〇校正處理。在P 0校正處理之後該資料以傳 輸之順序而被送至該列記憶體3 ·該P I校正機構1 〇使 用列記憶體3而執行一校正。此可使該記憶體錯誤在列記 憶體3中被校正，儘管該記憶體錯誤在P 0校正時發生在 緩衝記憶體中。 輸出自列記憶體3之資料的混合，係由可混合取消機 構而取消，而產生一資料區段。」該資料區段藉由EDC 錯誤感應機構1 2而施加錯誤感應。 圖16展示本發明之另一實施例。 此實施例係藉由使用圖13實施例之緩衝記憶體2而 本紙乐尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） i n n ϋ u ϋ n n n (請先閱讀背面之注意事項再填寫本頁 訂 經濟部智慈財產局員工消費合作社印製 -27· 579499 經濟部智葸財產局員工消黃合作社印製 A7 B7 五、發明説明（25 ) 移除該P I校正機構1 0 ·剩下之部分係與圖1 3實施例 相同。在此實施例中，當再生系統對於建構在緩衝記憶體 2中之E C C區塊而執行錯誤校正，該P I校正機構1 〇 在P0校正之前而執行PI校正。 如上述，本發明可應用於可執行錯誤校正碼產生處理 而不丟失原始資料之信號傳輸/記錄與再生裝置，儘管當 錯誤發生在記憶體中。進一步，本發明可應用於廉價之信 號傳輸/記錄與再生裝置，其可將資料記錄於一記錄媒體 而不丟失原始資料，儘管允許有較多之記憶體錯誤，而非 簡化瑕疵記憶體之檢視而上昇產能。本發明進一步可提供 在數位傳輸領域中之各種傳輸/接收系統之裝置中。其包 括無線單元、像是手機、介於電腦之間之傳輸/接收端、 以及電視傳輸器/接收器單元。在記錄與再生系統之領域 中，本發明可應用於DVD單元、CD單元，以及進一步 應用通訊功能之記憶體裝置等。 如上述，藉由本發明，其可提供一種資料處理方法， 其使用可回復原始資料之錯誤校正碼，儘管當發生資料錯 誤（記憶體錯誤），使用該方法之一記錄或是再生系統裝 置，以及使用該方法之傳輸與接收系統。 本發明並不限於上述實施例。此後，而解釋本發明之 其他實施例。 在圖1 7中，來自於主電腦之使用者資料係藉由區段 資訊加入機構1 5而以2 0 4 8位元組爲單位而轉換成單 一資料區段。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ------：---4------1T------_ (請先閲讀背面之注意事項再填寫本頁) -28- 579499 A7 B7 五、發明説明（26 ) f請先聞讀背面之注意事項再填寫本I^ 該區段資訊加入機構1 5將4位元組辨識資料（ί d )、2位元組ID錯誤感應碼（I ED)、以及6位元組 之著作權管理資訊（CPR — MA I )加入至主要資料（ 包含2048位元組）〃EDC產生與加入機構ι6對於 包括ID，IED，與CPR_MAI之總數爲2060 位元組產生有4位元組之錯誤校正碼（EDC)。混合;^ 構1 7將可混合資料加入至主要資料（2 0 4 8位元組） 中（或是藉由將主要資料與可混合資料予以互斥或），胃 此而混合該主要資料。 P I產生與加入機構8對於在經混合資料區段（或是 資料區塊）（1 7 2位元組X 1 2列=2 0 6 4位元組） 中之每個列（172位元組）產生一錯誤校正碼PI( 經濟部智慈財產局員工消费合作社印製 1 0位元組）。之後，該所產生之錯誤校正碼P I經由記 憶體控制機構2 0而依序儲存至緩衝記憶體2，而該2 〇 係產生具有1 8 2位元組X 1 2列之P I加入資料（資料 區塊）。此資料處理被繼續，頁此而在緩衝記憶體2中構 成1 6個錯誤校正碼P I資料區塊。即，在緩衝記憶體2 中，具有1 8 2位元組X 1 2列之1 6個資料區段（P I 加入資料）被集結，而構成具有1 82位元組X 1 9 2歹[J 之總和P I加入資料（或是總和資料區塊）。 在上述處理所產生之錯誤校正碼PI係根據原始資料 而產生之正確的錯誤校正碼。 該P 0產生與加入機構9對於儲存在緩衝記憶體2中 之總和資料區塊（1 8 2位元組X 1 9 2列）中之每個行 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -29- 579499 Α7 Β7 五、發明説明（27 ) (1 9 2位元組）而產生一錯誤校正碼P0 ( 1 6位元組 )。結果，加入有錯誤校正碼PI與P0之ECC區塊對 於儲存在緩衝記憶體2中之總和資料區塊而建構。 該緩衝記憶體2具有一足夠容量以保持多數個E C C 區塊，以確保儲存傳送自主電腦之資料之功能，直到其被 記錄於記錄媒體，且係由例如D R A Μ所構成。其可能造 成由於記憶體之接合狀態或是資料之圖樣而使得在記憶體 中之資料毀壞或是有記憶體錯誤發生。當錯誤校正碼Ρ 0 在此時被產生，此錯誤校正碼Ρ 0變成根據包括記憶體錯 誤之資料所產生之錯誤校正碼。 在緩衝記憶體2中之E C C區塊係一列一列的被讀取 (以1 8 2位元組爲單位），並儲存在列記憶體3中。該 Ρ I校正機構1 0使用列記憶體3而執行Ρ I校正，藉此 而校正該記憶體錯誤，而回復該原始資料（或是正確的 E C C區塊）。該列記憶體3係由例如S R A Μ (靜態 R A Μ )所構成，而可儲存Ρ I序列之單一列（1 8 2位 元組）。 該輸出自列記憶體3中之列資料，係被依序送出至調 變/同步加入機構4，其處理8/1 6調變與同步碼加入 ，並輸出該結果資料作爲記錄資料至該記錄媒體。 此處，再次參考圖1 1，而描述上述實施例之功能。 圖1 1展示錯誤（像是上述有於外部雜訊所造成之記 憶體錯誤或是錯誤4 2 )發生在輸出自緩衝記憶體2輸出 之E C C區塊中之資料部份之情形。 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X297公釐） n nn· I, - ulm >^n — /t-hr (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財4局員工消費合作社印製 -30 - 579499 A7 B7 五、發明説明（28 ) 在本發明中，錯誤校正碼P I係在資料儲存在緩衝記 憶體2之前而使用資料記憶體1而被產生。因此，所有包 括列4 5之1 9 2列中，該錯誤校正碼P I係爲根據原始 資料而產生錯誤校正碼。即，圖11中錯誤校正碼PI係 爲對於資料慘生之錯誤校正碼而無錯誤42· 另一方面，該P0產生與加入機構9，與緩衝記憶體 2 —起，而根據在每個行（1 9 2位元組）之資料而產生 一錯誤校正碼P0。因此，對於列4 1之錯誤校正碼嘔4 (1 6位元組）係爲根據包括記憶體錯誤4 2之資料所產 生之錯誤校正碼。 錯誤碼係爲對於錯誤校正碼之錯誤校正碼之部分4 8 ，儘管該碼P I係被首先產生與加入，而之後電話號碼 P0被產生與加入，或是碼P0被首先產生與加入，且之 後碼P I被產生與加入，而得到相同之該碼圖樣。 經濟部智慧財產局員工消资合作社印製 此處，該錯誤校正碼P I係爲在錯誤發生之前而被加 入至該原始資料之正確的錯誤校正碼。因此，所產生並被 加入至錯誤校正碼P I之區塊中之錯誤校正碼P 0係爲根 據原始資料所產生之正確的錯誤校正碼。然而，加入至其 他行（1 7 1 )(不包括在圖1 1所示之1 7 2行中之行 41 )之錯誤校正碼P 0係爲正確的錯誤校正碼。 當此E C C區塊被依序自該緩衝記憶體2讀取且P I 校正在列記憶體3中被執行時，在列4 5中之錯誤4 2被 簡易施加P I校正。即，該正確資料之列4 5被回復。遒 一步對於包括錯誤之資料所產生之P 0列中之每一列亦予 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公釐> ~ -31 - 579499 A7 B7 五、發明説明（29 ) (請先閲讀背面之注意事項再填寫本頁) 以P I校正，藉此而回復成正確的P 0序列。即，該列 4 6被施加以P I校正，藉此而校正單一位元組4 3同樣 的，其他列（以三角形標號表示）以施加一 P I校正，而 產生正確的P〇序列。 在上述處理中，P I校正係使用列記憶體3而對於所 有在E C C區塊中之列而執行。該P I校正並不限於此， 而可對於標有二角形記遗之{ll置處之每個列作用，以縮 短處理時間。此係因爲該記憶體錯誤4 2可在之後被簡易 校正，假如在圖中三角形位置處之p 〇序列係爲正確的錯 誤校正碼。 在上述解釋中，係使用在總和資料區塊中一列一列分 佈之P〇區塊之E C C區塊。在時機之E C C區塊中，然 而，該錯誤校正碼P 0係如圖1與圖6所解釋在總和資料 區塊中一列一列的分佈。即，該錯誤校正碼P〇經分佈， 使得該錯誤校正碼P 0之單一列係出現在1 2列總和資料 區段中。 之後，解釋圖17之再生系統。 經濟部智慧財產局w工消費合作钍印契 而將描述記憶體控制機構2 0之功能。該記憶體控制 機構2 0接收一請求，而自P I產生與加入機構8、同步 分離/解調變機構1 1、P0產生與加入機構9、P ◦校 正機構9、P I校正機構1 〇、以及列記憶體3而讀取或 是儲存資料。根據此請求，該記憶體控制機構2 0自緩衝 記憶體2讀取資料或是將資料寫入至緩衝記憶體2。此時 ，記憶體控制機構2 0控制該資料儲存位置，使得不使用 本紙伕尺度適用中國國家標準（CNS ) A4現格（210X297公釐） -32· 579499 A7 B7 五、發明説明（31 ) 而管理，亦可以列管理。 接著，而解釋當P I校正失敗（或無法執行）時之資 料再生。 當在單一列發生6個或是更多之記憶體錯誤時，而無 法執行P I校正。當在單一 E C C區塊中之資料發生6個 或是更多之記憶體錯誤時，將使P0 ( 1 6列）之P I校 正失敗。 當於PI校正處理時感應到有超過可校正之錯誤數目 之錯誤時，而改變使用之記憶體區域，並完成再生。在該 再生中，該主電腦被請求再次傳送該資料。之後，該錯誤 校正碼P I加入資料經由記憶體控制機構2 0而被儲存在 緩衝記憶體2 0 ·此時，使用之記憶體區域係爲以錯誤發 生之錯誤區域或是不同於錯誤區域之空白區域予以取代之 區域。 當錯誤數目超過儲存錯誤校正碼P 0之區域之每個列 中之錯誤可校正數目時，該再生係以如下方法而實施。 在該再生時，儲存在緩衝記憶體2中之第一儲存區中 之1 9 2列X 1 9 2位元組之總和資料區塊（包括錯誤校 正碼PI)係被移動至緩衝記憶體2中之第二儲存區域中 。在將每列於以施加P I校正處理之後，該位在緩衝記憶 體2中之第二儲存區域係經使用以再次執行P 0產生與加 入處理。此時，該再生可在系統內執行，而不要求主電腦 再次傳送該資料。 圖19係爲一圖以幫助解釋在緩衝記憶體2中資料之 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） (請先閲讀背面之注意Ϋ項再填寫本頁) 訂 經濟部智慧財1局員工消費合作社印製 -34· 579499 A7 _ B7 _ 五、發明説明（32 ) 移動。 (請先閲讀背面之注意事項再填寫本頁) 資料移動機構2 4將開始自A 〇之所儲存E C C區塊 (η )移動至標頭位址爲A3之空白區域。此時，該移動 資料包括含在位址A 0區域中之記憶體錯誤。對於每個列 執行P I校正，將造成此些記憶體錯誤被校正。使用施加 P I校正處理之資料，而執行P0產生與加入處理。假如 此時記憶體錯誤發生之數目係爲5或是更小，該所產生錯 誤校正碼P 0可有P I校正處理而校正。 使用圖1 7，而描述在資料再生之操作。 藉由光學頭而自記錄媒體所讀取之播放資料，係被導 入至同步分離/解調變機構11·該同步分離/解調變機 構1 1感應並自該播放資料而分離同步，並將施加有8/ 1 6調變之資料予以解調變，藉此而產生一記錄區段。因 爲錯誤係由於碟片瑕疵或是雜訊而在記錄或是再生資料至 /來自該記錄媒體而發生，錯誤可包括在記錄區段之資料 中 〇 經濟部智慧財4局員工消費合作社印製 該讀出記錄區段係經由記憶體機構2 0而依序儲存在 緩衝記憶體2，且1 6個記錄區段係被放置一起，藉此而 形成具有1 8 2行X 2 0 8列之ECC區塊於緩衝記憶體 2。該P0校正機構1 4以及P I校正機構1 0對於具有 208行X182列之ECC區塊施加錯誤校正。 該錯誤校正E C C區塊係以資料傳輸之順序而一列一 列自緩衝記憶體2而讀取該緩衝記憶體2，並儲存於列記 憶體。該P I校正機構1 0使用列記憶體3而對於每個列 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -35· 579499 經濟部智慧財1局員工消費合作社印製 A7 _ B7_五、發明説明（33 ) 之1 7 2位元組執行校正。結果，儘管記憶體錯誤發生在 緩衝記憶體2中之可混合資料區段，該錯誤可藉由p I校 正而校正。 接著，可混合取消機構1 3將位在可混合資料區段中 之主要資料（2 0 4 8位元組）之經混合資料與混合資料 予以混合（或是將兩資料予以互斥或處理），藉此而在混 合之前而產生一資料區段。之後，EDC錯誤感應機構 1 2使用包括在資料區段中4位元組錯誤感應碼（E D C )而感應在資料區段中之錯誤。假如其感應其在該資料區 段中不具有錯誤時，該資料區段將被傳送至該主電腦。 如上述，本發明可應用於可執行錯誤校正碼產生處理 而不丟失遠使資料之信號傳送/記錄與再生裝置中，儘管 當錯誤發生在記憶體中。進一步，本發明可應用於可將資 料記錄至一記錄媒體而不丟失原始資料之廉價之信號傳送 /記錄與再生裝置中，儘管當允許上昇記憶體錯誤之發生 ，而非藉由簡化瑕疵記憶體之檢視而增加產生。本發明可 進一步應用於各種在數位傳輸領域之傳輸/接收系統之裝 置中β其包括無線單元，像是手機、介於電腦之間之傳輸 /接收終端機，以及電視傳輸器/接收器單元。在記錄與 再生系統之領域中，本發明可應用於DVD單元、C D單 元、以及採用通訊功能之記憶體裝置等。 如上述，在本發明中，其可提供一種使用儘管當在記 憶體中發生錯誤（記憶體錯誤）時，而可回復原始資料之 錯誤校正碼之資料處理方法，一種使用該方法之記錄或再 ：II 4—, (請先聞讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -36- 579499 A7 B7 五、發明説明（34 ) 生系統、以及使用該方法之傳輸與接收系統。 —0------1T------_ (請先閱讀背面之注意事項再填寫本頁) 經濟部智¾財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -37-579499 Α7 Β7 Printed by the Consumers' Cooperative of the Bureau of Wisdom and Finance 1 of the Ministry of Economic Affairs 5. Description of the Invention (彳) Background of the Invention The present invention relates to an effective use of recording video data, audio data or computer data in a medium (such as a CD or (Diskette) or an error correction code generation method for reproducing data recorded on a medium. The invention further relates to a method for generating an error correction code, which can effectively transmit or receive video data and the like. The present invention further relates to a recording device, a reproduction device, and a receiving device, which employ an error correction code generation method. The present invention is particularly characterized by an error correction method using a buffer memory to perform error correction processing. When video data, audio data, computer data, etc. are recorded on, for example, a disc or disk, an error correction code is added to the data block. In the process of adding the error correction code, the data block is temporarily stored in a memory, and the error correction code of the data block row and row is generated. The error correction code added to the column is generally referred to as internal parity and is simply referred to as PI. The error correction code added to the line is generally called parity and is referred to as P 0 for short. In the process of adding the error correction code, when the data block is temporarily stored in the memory before the error correction code is generated, a part of the data in the memory may be damaged (or an error may occur) ). The damage can be attributed to the joint state of the memory or the data pattern. In addition, sudden external noise is also a disadvantage. The error that occurs at this time is called a memory error. At this time, the error correction code in the data block where the memory error occurred ((Please read the precautions on the back before filling this page). The size of the paper is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) -4 -579499 A7 B7 Printed by the Consumers' Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs. 5. Description of Invention (2) (hereinafter referred to as the changed data block) was generated. The error correction code is added to the changed data block, and the generated block is recorded in a recording medium. When data is reproduced from the recording medium, the error correction circuit uses the error correction code to perform an error correction process on the changed data block. That is, the changed data blocks are correctly reproduced. That is, the data block including the memory error has been correctly reproduced. However, this memory error is unnecessary for the original data. Therefore, when a memory error occurs, the original data cannot be restored correctly. Brief description of the invention Therefore, the object of the present invention is to provide a data processing method using an error correction code that can correctly restore the original data when a data error (memory error) occurs in the memory, and records using this method The system is also a regeneration system unit, and a transmission system and a reception system using the method. The following are the basic concepts of the error correction code processing method of the present invention. The invention is characterized in that the transmission or recording system generates an error correction code p I for each row of a data block having a matrix structure, and stores the error correction code p I and the data block in a memory, and when an error occurs, When the correction code PI plus the added data block is read from the memory, the error correction process is performed in the data block column according to the error correction code PI. (Please read the precautions on the back before filling this page) The size of the paper used in this edition applies to the Chinese National Standard (CNS) of 8 and 4 (210X: 297 mm) -5- 579499 A7 B7 Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing 5. Description of the invention (3) Further, the present invention is characterized in that when the data block of the matrix structure that applies the error correction processing by the data error correction code PI is read from the memory, the receiving or regeneration system is again An error correction process is performed using the error correction code PI for each column. In particular, when data is stored in a memory (first memory), the present invention uses a separate second memory (memory having a structure that does not damage data) in advance to generate an error correction code PI and The generated data is written into the first memory in combination with the data. Thereafter, when the data of the K sector (sector) and PI have been stored in the first memory, the error correction code P 0 is generated for the data and PI and added to it. When the data is read from the first memory, the PI correction process is executed each time the PI series is taken out. This allows the data to be restored to its original state, despite the destruction of the data in the first memory (or a memory error). When the data is reproduced, the reproduced data is temporarily stored in the memory, and the PI and P 0 error correction processing is performed. When the data in the memory is sent out after the error correction processing, the PI error processing is performed again for the data read from the first memory. This allows the data to be restored to its original state, despite the damage to the data in the memory (or a memory error). Further, the object of the present invention is to provide a data processing device that can correctly restore the original data, even though a data error (or a memory error) occurs in the memory, and a method of using the memory to ensure reliable operation Sex. ------ ： ίL # -------- Order ------ # 1 (Please read the precautions on the back before filling in this purchase) This paper size applies to Chinese national standards (CNS & gt Α4 Specification (210 × 297 mm) -6-579499 Printed by the β Industrial Consumer Cooperative of the Ministry of Economic Affairs and Intellectual Property 4th Bureau A7 _B7_ V. Description of the Invention (4) In particular, the present invention is characterized by a transmission or recording system for An error correction code PI is generated for each row in a data block having a matrix structure, and the error correction code PI and the data block are stored in the memory. When it is read in the memory, the error correction process is performed in the data block according to the error correction code PI. After that, when an error cannot be corrected when an error correction process is performed using the error correction code PI The memory blocks that store related rows or data blocks will be changed to avoid memory errors. And the areas where memory errors occur are learned and are no longer used. Brief description of the figure Figure 1 is shown on DVD To obtain the data section of the physical sector (sector) An explanatory diagram of the configuration in the data block of the DVD; FIG. 3 is an explanatory diagram of a feedback shift register for generating scramble data; and FIG. 4 is an illustration of the ECC block. Explanatory diagram; Figure 5 is an explanatory diagram showing a recording section; Figure 6 is an explanatory diagram showing an error correction code P 0 interleaved with an ECC block; and Figure 7 is a block diagram for explaining a conventional recording and reproducing unit. The method of generating error correction codes in the recording and recording system; Figure 8 is a block diagram for explanation in the conventional recording and reproduction unit (please read the precautions on the back before filling this page) CNS) Α4 specification (210X297 mm) 579499 A7 B7 Printing method of the error correction code of the reproduction system of the Intellectual Property Office of the Ministry of Economic Affairs, Employees' Cooperatives 5. The invention description (5); Figure 9 is a diagram to explain Know the error correction code when a D RAM memory error occurs in the recording and reproduction unit; Figure 10 is a block diagram of a recording system to explain an embodiment of the error correction code generating method of the present invention; Figure 11 is a display of this An explanatory diagram of the data structure of the ECC block obtained by the clear error correction code generation method; Figure 12 is a block diagram of a reproduction system to explain the error correction code generation method in the ECC block An embodiment of the error correction method; FIG. 13 is a block diagram of a recording system to explain another embodiment of the error correction code generating method of the present invention; FIG. 14 is a block diagram of a recording system to explain this Another embodiment of the method for generating the error correction code of the invention; FIG. 15 is another embodiment of the method for correcting errors in the ECC block obtained by the method of generating the error correction code of the invention; FIG. 16 is a record And a reproduction system block diagram to explain the error correction code generating method of the present invention and an embodiment of the error correction code using the error correction code to correct errors; FIG. 17 is a block diagram of a recording system and a reproduction system to explain Another embodiment of the error correction generating method of the present invention; FIGS. 18A and 18B are explanatory diagrams for illustrating processing in the error correction code generating method of the present invention. At the time of the data, including the memory map of the buffer memory and the data string of the ECC block of the memory error; (Please read the precautions on the back before filling this page)-The paper size of the book applies to the Chinese National Standard (CNS) A4 Specifications (210X297mm) -8-579499 A7 B7 V. Description of the Invention (6) and Figure 19 are explanatory diagrams to show the processing of the ECC block of the memory error including the method of generating the error correction code of the present invention Another example 0 (please read the precautions on the back and fill in this page) Order component comparison table 2 0 1 Buffer memory (DRA M) 2 0 2 Section information adding mechanism 2 0 3 Ε DC generating and adding mechanism 2 0 4 Hybrid mechanism 2 0 5 Ε CC memory (DRA M) 2 0 6 P I generation and joining mechanism 2 0 7 P 0 generation and joining mechanism 2 0 8 Detailed description of the invention of the modulation / synchronization joining mechanism Here, Exemplary embodiments of the present invention will be explained with reference to the drawings. The use of a DVD (Digital Versatile Disc) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will be explained with reference to FIGS. 1 to 8 Recording and reproducing unit of the error correction circuit and the error correction code added to the circuit configuration. First, referring to Figs. 1 to 6, the structure of data recorded on a DVD will be explained. Figure 1 shows the sequence of data processing to obtain the physical section in D V D. The section is called “% data section” according to the signal processing stage. The paper size of the record applies to the Chinese National Standard (CNS) A4 specification (210X: 297 cm).--9- 579499 Intellectual Property Bureau, Ministry of Economic Affairs Employee Consumer Cooperatives printed A7 B7 V. Invention Description (7) Section 〃, or% Entity Section 〃. As shown in Figure 2, the data section includes the main data of 208 bytes, 4-byte identification data (ID), and 2-byte ID error induction code (IED) (as the Error code in the code), 6-byte copyright management information (CPR_MAI), and 4-byte error induction signal (EDC) (as a signal that senses errors in this data segment. 0 ID, IDE, The steps of CPR-MAI and EDC are steps A1 to A3 in Fig. 1. In step A1, ID is added to the main data. In step S2, IED is further added. In addition, in step S3 Add CPR — MAI. Then, calculate the EDC of the main data. The EDC is added to the main data. Then the mixed data is added to the main data (including 2048 bytes) in the data section (steps A4, A5, A6) ). Then, after mixing the data, 16 data sections are put together. A Reed-Solomon error correction code is generated and added to the 16 data sections (step A6). The The recording section (ECC adding section) is for adding the error correction code PI and The data section of the error correction code P0 (step A7). This physical section is a standard that applies 8/16 correction and adds the synchronization code (SYNC code) to the interleaved 9 1 bytes in the recording section. Head (step A8). Use Figure 2 to explain the structure of the DVD data section. The data section contains the main data including a 20-by-8-byte leader or 2064-bits with a 72-by-12 byte Tuple. That is, a data section contains the main data of 2048 bytes, and the discrimination of the 4-byte paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 cm) ------ r--I — (please read the precautions on the back before filling out this page) Order-10- 579499 A7 B7 Printed by the staff of the Ministry of Economic Affairs ’s Smart Finance 1 Bureau Cooperative, V. 'Invention Note (8) 1 I Information (ID), 2-byte ID error induction code (IED) 1 1 I% 6-byte copyright management information (CPR Μ AI), and 4 1 1-byte error induction code (EDC). 1 I Please 1 1 Figure 3 shows the main data generated in step A 4 (including the first news) 1 1 read 1 2 0 4 8 bytes) of the mixed data Sk shift register. For example, the back 1 I If the ID part of the data segment is used as the starting point to generate the mixed note 1 I data S k. This mixed data Sk is used as the main item of the mixed data! 0 □ and then 1 1 4 required data (208 bytes). As a result, the material Dk 'after the mixing is the result of the mutual exclusion of Sk (k is 0 to 2047) and Dk. 1 | described with reference to FIG. 4] The structure of the E C C block. 1 I data block has been formed to have 172 rows X 1 9 2 columns 9 per package 1 order I contains 172 bytes X 1 2 columns 16 data sections 0 Red Solomon 1 1 I The error correction code is generated and added to 172 rows X 19 2 columns. First f 1 1 1 6 byte error correction code P 0 is generated and added to each 172 rows 1 1. In the sequence of P 0 Each row contains 192 bytes plus 16 bits and 1 m bytes, and it is 208 bytes. Next, a 10-byte error correction 1 1 I code P I is generated and added to each of the 128 columns including the column of the error correction code P 0. The 182 rows X 2 0 8 1 1 columns added with the error correction code P I form an E C C block. Although when P0 and P1 are generated in the reverse order of 1 1 > the same code pattern can be obtained. 1 | A vertical row in the E C C block is called P 0 sequence 9 and horizontal. The 1 I to one column is called the PI sequence. The P 0 sequence contains 192 bytes plus 1 1 I 16 bytes, or 208 bytes. In a single P 〇 sequence> can be 1 1 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -11- 579499 Printed by A7 B7 of the Consumer Finance Cooperative of the Bureau of Wisdom and Finance of the Ministry of Economic Affairs Explanation (9) Detect errors up to 8 bytes. The p 1 sequence contains 172 bytes plus 10 bytes, or 182 bytes. In a single PI sequence, errors of up to five 7C groups can be corrected. Next, the structure of the recording sector is explained with reference to FIGS. 5 and 6. In the ECC block composed of 20 8 columns X 1 82 rows, 16 columns constituting the error correction code P 0 are separated by individual columns to columns. The separated rows are inserted one by one at the interleaving positions of the 12 rows of the 192 rows of data sections, resulting in the construction shown in FIG. 6. This is referred to as the interleaving of P0. Therefore, the ECC block after the parent error is made up of 16 groups of 13 columns X 1 8 2 bytes (= PI added data (for 12 columns) plus P 〇 (for one column)) ° such as As shown in FIG. 5, the recording section is composed of PI adding data (for 12 columns) plus P 0 (for one column), that is, 13 columns X 1 8 2 bytes. The E C C block after the column interleaving is composed of 16 recording sectors, as shown in FIG. 6. The physical section is such that a SYNC code is added to the 91 bytes of each column in the record section of 13 columns X 1 8 2 bytes (2 3 6 bytes). Interleave the header, and start to adjust from column 0 and column by column. The one obtained by adding the S Y N C code to the header of the 91-byte data is the SYNC box. Therefore, the physical section is composed of 16 groups X two SYNC boxes. Referring to Figs. 7 and 8, the error correction code adding circuit in the data recording unit is explained. In Figure 7, the user data transmitted by the autonomous computer are sequentially stored in this paper. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) '-12--------— Mm—— (Please read the notes on the back before filling in this card.) Order 579499 A7 B7 Printed by the Anti-Corruption Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs V. Description of the invention (1〇) Buffer memory 2 0 1 When the data is read in the body 2 01, the stored user data is processed by the section information joining organization 2 02, the EDC generating and joining organization 203, and the hybrid organization 204. The processing is performed at the interleaving of the main data of 2048 bytes, and the data is converted into a single data section. The information in this section is added by the institution 202 to the 4-byte identification data (1 D), the 2-byte ID error sensing code (I e D), and the 6-byte copyright management information (CPR — ΜΑ I ) To the main profile. The ED C generation and joining mechanism 203 generates and adds a 4-byte error sensing code (EDC) to the entire 060-byte data, and generates the entire 206-byte data. The mixing mechanism 204 mixes the main data in the data section. The mixed data sections are sequentially stored in the ECC memory 205. In the ECC memory 205, a data section of 172 rows x 192 rows is formed, and 16 data sectors of 172 bytes x 12 rows ( sector). PI generation and joining mechanism 206 and P 0 generation and joining mechanism 207 generate and add error correction codes to 172 rows x 192 columns of data blocks, and generate an ECC block. ECC explained before Block, which is interleaved by columns, and then transmitted to the modulation / synchronization joining mechanism 208. The modulation / synchronization joining mechanism 208 converts the 8-bit input data into 16-bit code characters and interleaves EC C blocks in the input column. That is, a modulation of 8/1 6 is generated. After that, the SYNC code was added to the staggered portion of the input data of 91 bytes. The paper size of the specimen is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) L0 ------, 玎 ------ (Please read the notes on the back before filling out this page) -13- 579499 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the A7 B7 V. Invention Description (11) header to form a physical section. The formed physical section is transmitted as recording material and recorded in a medium. Now, the effect of the error correction code will be explained. A data reproduction system including error sensing and sensing mechanisms reproduces recorded data. When an error occurs in the data in the reproduction entity section of the reproduction process, this mechanism uses an error correction code to correct the error in the error containing the E C C block. The error sensing and correction mechanism can recover the original E C C block without errors within its correction capability. Referring to Fig. 8, an error generation method on the data reproduction side is explained. After the playback data read from the recording medium is separated from the synchronization code by the synchronization separation / modulation mechanism 2 21, the 8/16 modulation data is demodulated and the recording section is decompressed. Because errors may occur in recording or regenerating the recorded data due to defects, noise, chatter, crosstalk, etc. in the disc, the playback data will include some errors. The read-out recording sections are sequentially stored in the ECC memory 205. Therefore, the read-out recording sections are composed of 182 rows and 208 columns of 16 recording sections (: (: block.?) Correction mechanism. 2 2 2 and? 1 correction mechanism 22 3 performs error correction on ECC blocks of 1 8 2 rows X 1 92 columns, and corrects errors in the playback signal. The PI correction mechanism 2 2 3 for each of the ECC blocks Column calculation error pattern induction 値 polysemes (syndr omme). If an error is detected, error correction is performed. When the original data is reproduced without errors, the polysemes get 0 to 0. When errors occur in the record or When transmitting a signal, the ambiguous word is obtained from the error position indicating the position where the error occurred. ^ Paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm 1 " " (Please read the precautions on the back before filling in this (Page) -14- 579499 at _B7_ V. The description of the invention (12) and the error pattern determined by the error state. The P0 correction mechanism 2 2 2 reads from the memory 2 0 5 in the P sequence 2 0 8 Byte data and perform specific operations on that data When the synonym does not turn to 0 after the result of the operation, the P 0 correction mechanism performs error correction on the sequence. When the corrected data is subjected to an error calculation, the error correction code is generated to recover When the data, the synonym gets 0 to 0. The above operation is performed on all 182 bytes of ECC blocks. When the length is 8 bytes or more, errors occur in a sequence. At this time, the P0 correction mechanism 2 2 2 cannot correct errors. At this time, however, because the PI correction mechanism 2 2 3 can perform error correction of up to 5 bytes on the PI sequence, if the error length is included in a single P 0 sequence, When the P 0 correction is performed on lines 182 or shorter, the error can be corrected. Further, the repetition of the P 0 correction and the PI correction will correct a single P 0 correction and a single correction. Errors that cannot be corrected by PI correction. When all consents have a value of 0, the error correction of the ECC block is completed. The error correction ECC block printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is transmitted to the hybrid cancellation agency 2 2 4. The mixing cancellation mechanism 2 2 4 adds the mixed data (or the mixed data is mutually exclusive or) to the main data of the 20 48-bit leader in the mixed data section, and cancels the mixing of the main data and stores it in the buffer Result data in memory 2 01. EDC error sensing mechanism 2 2 5 According to the 4-byte error sensing code (e DC) included in the data segment, the error in the data segment is sensed. The paper size is applicable to China. National Standard (CNS) A4 Specification (210X297 mm) -15- 579499 A7 printed by Employee Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs ___B7_5. The invention description (13) is incorrect. When an error is sensed, the segment is regenerated. The data segments stored in the buffer memory 201 are sequentially transmitted to the host. Low-cost and large-capacity DRAM (Dynamic RAM) is used as buffer memory 205, 201. Because of the structure of DRAM, it depends on the connection state of the memory or the pattern of the data, so that the data in the memory is Destroyed (or memory error occurred). When the data part in the memory is destroyed (or a memory error occurs) and the data block is changed, when the error correction code PI, P 0 is generated and added, the error correction code PI, For data changed by a memory error, the PO will become the correction error correction code. When an EC C block having an error correction code generated for the changed data is recorded and then reproduced, the changed data is reproduced, although the error correction process is performed after the reproduction. When the memory error 32 occurs in a part of the data block 32 having a column of 172 bytes X 192 and the situation where the block is changed, it will be described with reference to FIG. 9. First, the PO generation and joining mechanism 9 generates an error correction code P 0 for each 172 rows, and adds the P 0 to the row. The error correction code PO 3 3 (16 bytes) for line 31 is generated based on the data changed by the memory error 32. Next, the PI generating and adding circuit 8 generates a 10-byte error correction code P I into each 108 column including the error correction code P 0, and adds the PI to the column. The error correction code P 136 (10 bytes) generated for column 3 4 will be based on the memory error 32 ------: --- MW ------, 1T ---- -(Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 size (210X297 mm) -16-Printed by the staff of the Intellectual Property Bureau of the Ministry of Economy 579499 A7 ___B7_ 5. Description of the invention (14) The changed information is generated. Further, the error correction code P I 3 7 generated by the error correction code P 0 of 16 rows is generated based on the data including the error correction code P 0 3 3 generated by the data changed by the memory error 32. As a result, an appropriate error correction code is added to the data block changed by the memory error 32. At this time, for all error patterns of the PI sequence including the error 32 2 to 0 8 sequence, the synonym and the synonym for the P 0 error of the 18 2 line are obtained, and as a result, the E CC block is I think there is no error. Actually, however, the original data in the E C C block has been changed by memory error 32. Here, it is considered that the E C C block generated according to the changed data block is recorded to a recording medium and then the playback data of the block is reproduced from the medium. The playback data uses an error correction code to apply an error correction process. Here, the error occurred in the reproduced data is corrected within the range of the correction capability, and the playback data is restored by this. However, memory errors, including before recording, cannot be corrected. That is, although the error in the P 0 sequence 31 is corrected using the error correction code P 0 3 3, the data including the memory error 3 2 is reproduced, and then the error correction is properly completed, and the original cannot be restored. Use of information. If the memory error occurs in the data in the buffer memory on the reproduction side, it can cause the data including the memory error to be transferred to the host computer. (Target point of the present invention) This paper size is applicable to Chinese National Standard (CNS) A4 wash case (210X 297 mm), ... ⅠΦ ------ ΤΓ ------ (Please read the back Note: Please fill in this page again) -17- 579499 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (15) As mentioned above, the data in the memory is destroyed (or when an error occurs ), Although the error correction code is generated based on the data changed by the record error, and the data is read and subjected to an error correction process during the reproduction operation, and the data is recorded in a recording medium, the original The information cannot be correctly restored, although the information changed by the error is restored. When the data applied to the error correction memory is destroyed (or an error occurs), it may cause the error data to be transferred to the host computer. In order to prevent the data in the memory from being destroyed (or an error occurs), the memory that stores the data must be implemented by a structure that prevents the data from being destroyed, such as S-RAM. However, this structure is less suitable for cost considerations. Therefore, an object of the present invention is to provide a method and an apparatus for generating an error correction code without losing the original data, although an error occurs in a memory, and a recording apparatus, a reproduction apparatus, a transmission apparatus, and a receiving apparatus using the method and the apparatus . (Basic idea of the present invention) The error correction code generating system of the present invention includes a section of memory (for example, constituted by SRA M), a PI generating and adding mechanism for generating and adding PI, and a buffer memory as The PI adding data is stored, and the PO generating and joining mechanism is used to generate and join PI, a row of memory (for example, composed of SRAM), the PI correcting mechanism 睃 performs PI correction, and the PO correcting mechanism is used to perform PO correction. The system uses the segment memory to add an error correction code PI to the data, and stores the PI to add --------- a ------ IT ------ ψ n ( Please read the precautions on the back before filling out this page.) The scale of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) • 18- 579499 A7 ___B7 V. Description of the invention (16) Information to this buffer memory, Prior to transmitting the PI-added data or recording it on a recording medium, a p I correction is performed using a bank memory to correct a memory error. When the above processing is reproduced, the PI correction is performed again before data is transferred to the host computer, and memory errors can be corrected. Further, the error correction code generating system according to the present invention includes the segment memory, a PI generating and adding mechanism, a buffer memory, a po generating and adding mechanism, a PI correcting mechanism, and a PO correcting mechanism. The system uses segment memory to add the error correction phone number to the data to generate a data segment (PI addition data), stores the PI addition data to the buffer memory, and transmits the PI addition data or transfers it Before recording on a recording medium, the buffer memory is used to store the PI correction, thereby correcting the memory error. Printed by the Consumer Cooperative of the Bureau of Intellectual Property 1 of the Ministry of Economic Affairs In addition, the error correction code generation system of the present invention includes the PI generation and joining mechanism, buffer memory, P 0 generation and joining mechanism, column memory, PI correction mechanism, and P0 Calibration mechanism. The system uses the data stored in the buffer memory to generate an error correction code, generates a data block that adds the error correction code PI to the data (PI adds data), stores the block in the buffer memory, and self-buffers Before the PI is transmitted in the memory or recorded, the PI memory is used to perform p I correction to correct memory errors. And, the error correction code generating system of the present invention includes a segment memory, a PI generating and joining mechanism, a PO generating and extracting mechanism, a PI correcting mechanism, and a PI correcting mechanism. This system uses the error correction code p I to use this paper. The size of the paper applies to the Chinese National Standard (CNS) A4 (210X297 mm) -19. 579499 A7 B7. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (17) This Segment memory and add to the data to generate a data block (p J adds data), and store p I added data to the buffer memory, and transfer or record the PI added data from the buffer memory, After that, before transmitting the data to the host computer, PI correction is performed on the data added to the PI on the reproduction side, and data errors are corrected by this. Hereinafter, the characteristic parts of the present invention will be described with reference to the drawings using specific embodiments thereof. Referring to Fig. 10, an error correction code adding circuit in the data recording apparatus of the first embodiment of the present invention will be explained. User data (main data) transmitted from the autonomous computer are sequentially stored in the section memory 1. At this time, the section information adding mechanism 5 adds the 4-byte identification data (ID), the 2-digit ID error induction code (IED), and the 6-byte copyright management information (CPR-ΜΑ I) To the main data of 208 bytes. The EDC generates and joins the organization 6 for the data of a total of 260 bytes (including ID, IED, c P R_MA I), and mixes the error induction code of 4 bytes, and adds the error induction code to 2 0 6 0 byte data. The mixing mechanism 7 adds the mixed data to the main data of the 2048-bit leader (or to mutually exclusive the main data and the mixed data), thereby mixing the mixed data sections. The PI generating and adding mechanism 8 generates an error correction code PI (10 bits) for each row (172 bytes) of the mixed data section (or data block) stored in the section memory 1. Group), and the PI is added to the column, thereby generating 182 bytes X 12 columns of PI joining funds {please read the note on the back before filling this page) This paper size applies to China Standard (CNS) A4 Washer (210X297 mm) -20- 579499 A7 B7 Printed by the Employee Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs V. Invention Description (18) Material section (data block). The segment memory 1 has a capacity (18 bytes X 1 2 rows) for storing PI added data segments, and is composed of, for example, SR A M (static RAM). The SRAM has a structure in which errors can be rarely generated in the stored data. This ensures that the error correction code PI generated by using the sector memory 1 is the correct code generated by the user data without errors. The PI added data from the memory 1 (or the data block having 18 bytes X 1 2 rows is called a data block) are sequentially stored in the buffer memory 2. In the buffer memory 2, 16 data segments (PI adding data) having 182 bytes X 1 2 rows are grouped together to form a total of 182 bytes X 1 92 rows. PI joining Data (or sum data block). However, the P 0 generation and joining mechanism 9 generates one for each row (192 bytes) of the total data block (18 2 bytes X 1 92 columns) stored in the buffer memory 2. Error correction code P0 (16 bytes), and add this P0 to the line. As a result, the ECC block to which the error correction codes P I and P0 are added is constituted for the total data block stored in the buffer memory 2. The buffer memory 2 has a sufficient capacity, and maintains a plurality of E C C blocks to ensure the storage function of data transmitted from the autonomous computer until it is recorded on a recording medium and is composed of, for example, DRAM. It may happen that the data located in the memory is destroyed or a memory error occurs, depending on the connection state of the DRAM or the pattern of the data. Ran (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 size (210X29 * 7mm>) • 21-579499 Α7 Β7 Printed by the Employees ’Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs System 5. Description of the invention (19) Moreover, the data processing method according to the present invention will remove the billion-body error as described later. In the buffer memory 2, the ECC block is read in a row by a row (by 1 8 2 Bytes as a unit), and store it in row memory 3. The PI correction mechanism 10 uses the row of memory 3 to perform PI correction, thereby correcting the memory error and restoring the original data (or (Corrected ECC block). This row of memory 3 is composed of, for example, SRA M, and can store the capacity of a single row (182 bytes) of the PI sequence. The data output from row 3 is Sequentially sent to the modulation / synchronization adding mechanism 4, which processes 8/1 6 modulation and synchronization code addition, and outputs the resulting data when recording data to the recording medium. Figure 11 shows the output from the buffer memory Error in the data part of ECC block 2 Situation (such as error 42 due to external noise or the above-mentioned memory error). In the present invention, the error correction code PI is generated using data memory 1 before the data is stored in the buffer memory. Therefore, in all 192 columns including column 1 45, the error correction code PI is an error correction code generated based on the original data. That is, the error correction code PI is for data without error 42. On the other hand, the P 0 generation and joining mechanism is combined with the buffer memory 2, and an error correction code P is generated based on the data in each row (192 bytes). 0. Thus, the error correction code 4 4 (16 bytes) for line 4 1 is an error correction code generated based on the data including the memory error 4 2. ----------- ----- Order ------ (Please read the notes on the back before filling out this page) This paper size applies to Chinese national standards (CNS M4 specification (210X297 mm) -22- Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative 579499 A7 _B7_ V. Description of the invention (20) The product code is Part of the error correction code 4 8 (indicated by a circle), although the code PI is first generated and added, and then P0 is generated and added, or the code P 0 is generated and added first, and then the phone number PI is generated and added The same code pattern is obtained. Here, the error correction code PI is the correct error correction code added to the original data when an error occurs. Therefore, the error correction code P 0 is generated and added to the error correction code PI. It is the correct error correction code of the original data. In addition, the error correction code P0 (shown in FIG. 11) added to the other line (171) of line 4 1 of line 17 2 is a correct error correction code. When the E C C block is sequentially read from the buffer memory 2 and the PI correction is performed in the column memory 3, the error 4 2 in the column 4 5 can simply perform the PI correction. That is, columns 3 to 4 of the erroneous data are replied. Further, each column of the PO sequence generated from the data including the error 42 is also subjected to PI correction, and the correct PO sequence is returned. That is, the column 4 6 is subject to the P I correction, and the correction unit is a single byte 4 3. Similarly, the other columns (indicated by triangles) are subject to the P I correction and the correct P 0 sequence is generated. In the above processing, the PI correction is performed for all the columns in the ECC block in the column memory 3. The PI correction is not limited to this *, but can be applied to each column marked with a triangle mark to shorten the processing time. This is because the memory error 4 2 can be correctly corrected afterwards. If the P 0 sequence in the triangle position in the figure is the correct error correction code ® In the above explanation, it has been used in the sum data block. This paper size applies to China National Standard (CNS) A4 (210X297 mm) ------. --------- 1T ------ Office (please read the precautions on the back before filling in this purchase) -23- 579499 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (21) And the distributed ECC blocks of P 0. However, in the actual E C C block, the error correction code P0 is distributed one by one in the sum data block as shown in Fig. 1 and Fig. 6. Fig. 12 shows a reproduction mechanism for performing an error correction process on the E C C block obtained by the above-mentioned process (the process performed by the circuit of Fig. 10) and reproduction from a recording medium. The playback data read from the recording medium by the optical head is imported to the synchronous separation / demodulation unit 11 · The synchronous separation / demodulation unit Jun 1 1 senses the synchronization from the playback data and applies the 8/1 6 The modulated data is demodulated. The error can be included in the data of the recording section because of an error occurring in the data due to a disc defect or noise that is recorded or reproduced from a recording medium. The read-out recording sections are sequentially stored in the buffer memory 2, and 16 recording sections are put together to form an ECC having 182 rows X 2 0 8 columns in the buffer memory 2. Block. What? The 0 correction mechanism 14 and the PI correction mechanism 10 apply error correction to the E C C block having 182 rows and X 2 0 8 columns. However, the PI correction process may be performed before this PI correction process. The reason is that if a memory error occurs in the P 0 block, the P I correction can recover the correct error correction code P 0. The error correction E C C block is read from the buffer memory 2 (in 182-bit units) row by row in the order of data transmission, and is stored in the section memory 1. The PI correction mechanism 10 uses the segment memory 1 to perform PI correction in 172 bytes of each column. This (please read the precautions on the back before filling this page) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -24-579499 A7 _B7_ V. The description of the invention (22) is because the memory The error error occurs in the buffer memory 2 and exerts the P0 correction. The PI correction will effect the error when correcting the error. (Please read the note on the back before filling this page.) Next, the hybrid cancellation mechanism 1 3 will include the mixed data of the main data (2 0 4 bytes) in the mixed data section, X the mixed data. (Or the two data are mutually exclusive or), thereby generating a data section before mixing. After that, the EDC error sensing mechanism 12 uses a 4-byte error sensing code (EDC) included in the data sector to sense the error in the data sector. If it senses that there is no error in the data sector, the data The session will be transferred to the host computer. In the above explanation, when the data is stored in the segment memory 1 from the buffer memory 2, the PI correction mechanism 10 performs PI correction. Or, the PI correction is performed only when an error is sensed using EDC. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed further. In each column of the error pattern, the synonym (10 bytes) is detected. Only the part of the synonym is counted to detect an error, and only if its judgment is correct. When an error occurs, PI correction is performed. That is, in the error correction process using the error correction code PI, only the portion of the error pattern induced by the error correction code PI of the P byte (R byte, R < P) is calculated, and error sensing is performed. An error correction occurs only when an error occurs in its judgment. FIG. 13 shows another embodiment of the present invention. This embodiment is obtained by removing the memory 3 in the embodiment of FIG. 10. In the embodiment of FIG. 13, the PI correction mechanism 10 performs the PI correction using the buffer memory 3. Since the other structures are the same as those of the embodiment of Fig. 10, explanations will be omitted. When a memory error occurs, the paper size of P0 is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -25- 579499 A7 B7 V. Description of the invention (23) Error generation caused by joining and joining the organization The code P 0 becomes an error correction code generated based on data including memory errors. Performing PI correction on all the columns of the error correction code P 0 can return the error correction code P 0 generated based on the data including the memory error, to the error correction telephone number P 0 generated based on the original data. In this embodiment, since the EC C block after PI correction appears in the buffer memory 2, it may include a memory error. However, the error correction code P 0 was once returned to the error correction code generated based on the original code. Therefore, although the ECC block includes an error, the error will be corrected by the Po correction. FIG. 14 shows another embodiment of the present invention. The use data from the host computer is added to the single data section with the main data of 2048 bytes by the section information adding mechanism 15. The section information adding mechanism 15 adds 4 bytes. Identification data (ID), 2-byte ID error sensing code (IED), and 6-byte copyright management information (CP R_MA I) to the main data. The ED C generation and joining organization 16 generates a 4-byte error correction code (EDC) for a total of 260 bytes of data, and adds the brick to the latter, thereby generating a total number of 20 containing 6 4-byte data section. The mixing mechanism 17 mixes the main data into the data section. The mixed data segments are sequentially stored in the buffer memory 2. In this buffer memory 2, 16 data segments with 172 bytes X 1 2 columns are integrated to form a paper size with 172 rows and X 192 columns, which is applicable to Chinese national standards (CNS > Α4 specifications ( 210X297 mm) (Please read the “Notes on the reverse side before filling in this card”) Order the printed by the Consumer Cooperatives of the 1st Bureau of Smart Finance of the Ministry of Economic Affairs -26- 579499 A7 B7 V. Description of the invention (24) Information section. PI generation and The joining organization 18 receives the data segment from the hybrid organization 17 and then sequentially generates a 10-byte error correction code PI for each data column and sends the PI to the buffer memory 2. Results, In the buffer memory 2, a PI joining block having a column of 182 bytes X 192 is constructed. At this time, the error correction code PI is an error correction code generated based on the original data. The lower part is the same as the above embodiment, and is not repeated here. Fig. 15 is an error correction circuit corresponding to the error correction code generating circuit. This embodiment is almost the same as the embodiment of Fig. 12, except for the buffer memory 2 becomes column memory3. The PI correction mechanism Using the buffer memory 2 to perform error correction for at least a column including P 0 will cause the error correction code P 0 to become a correct error correction code. Then, the P 0 correction mechanism 14 performs a P 0 correction process. At P 0 After the correction process, the data is sent to the bank of memory 3 in the order of transmission. The PI correction mechanism 10 uses the bank of memory 3 to perform a correction. This allows the memory error to be corrected in the bank of memory 3. Correction, although the memory error occurred in the buffer memory during the P 0 correction. The mixing of the data output from the memory 3 is canceled by the mixable cancellation mechanism, and a data section is generated. "The data area The segment applies error sensing by the EDC error sensing mechanism 12. Figure 16 shows another embodiment of the present invention. This embodiment uses the buffer memory 2 of the embodiment of Figure 13 and the paper scale is adapted to Chinese national standards ( CNS) A4 Washer (210X297 mm) inn ϋ u ϋ nnn (Please read the notes on the back before filling out this page. Order printed by the Employees ’Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs-27 · 579499 Intellectual Property of the Ministry of Economic Affairs A7 B7 printed by the employee elimination cooperative. V. Invention description (25) Remove the PI correction mechanism 1 0. The rest is the same as the embodiment in FIG. 13. In this embodiment, when the regeneration system is constructed in the buffer The ECC block in the memory 2 performs error correction, and the PI correction mechanism 10 performs PI correction before P0 correction. As described above, the present invention can be applied to a signal that can perform error correction code generation processing without losing original data. Transmission / recording and reproduction device, even when errors occur in memory. Further, the present invention can be applied to an inexpensive signal transmission / recording and reproduction device, which can record data on a recording medium without losing original data, although it allows more memory errors instead of simplifying inspection of defective memory While increasing production capacity. The present invention can further be provided in devices of various transmission / reception systems in the field of digital transmission. It includes a wireless unit, such as a mobile phone, a transmitting / receiving end between computers, and a TV transmitter / receiver unit. In the field of recording and reproduction systems, the present invention can be applied to DVD units, CD units, and memory devices to which communication functions are further applied. As described above, with the present invention, it is possible to provide a data processing method that uses an error correction code that can recover the original data, although when a data error (memory error) occurs, use one of the methods to record or reproduce the system device, and Transmission and reception system using this method. The invention is not limited to the embodiments described above. Hereinafter, other embodiments of the present invention will be explained. In Fig. 17, the user data from the host computer is converted into a single data segment by using 2048 bytes as a unit by the segment information adding mechanism 15. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ------: --- 4 ------ 1T ------_ (Please read the precautions on the back first (Fill in this page again) -28- 579499 A7 B7 V. Description of the invention (26) f Please read the notes on the back before filling in this I ^ The section information is added to the organization 1 5 The 4-byte identification data (ί d ), 2-byte ID error induction code (I ED), and 6-byte copyright management information (CPR — MA I) are added to the main data (including 2048 bytes) 〃 EDC generation and joining institutions ι6 The total number of ID, IED, and CPR_MAI is 2060 bytes. A 4-byte error correction code (EDC) is generated. Blend; ^ Structure 17 Add the miscible data to the main data (208 bytes) (or by mutually exclusive of the main data and the miscible data), and the stomach mixes the main data. PI generation and joining mechanism 8 for each column (172 bytes) in the mixed data section (or data block) (172 bytes x 1 2 rows = 2 0 64 bytes) ) Generate an error correction code PI (10 bytes printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs). After that, the generated error correction code PI is sequentially stored in the buffer memory 2 through the memory control mechanism 20, and the 20 generates PI addition data with 182 bytes X 1 2 rows (data Block). This data processing is continued, and 16 data blocks of the error correction code PI are formed in the buffer memory 2. That is, in the buffer memory 2, 16 data segments (PI-added data) having 18 2 bytes X 1 2 rows are aggregated to constitute 1 82 bytes X 1 9 2 歹 [J The sum PI is added to the data (or the sum data block). The error correction code PI generated in the above process is a correct error correction code generated based on the original data. The P 0 generation and joining mechanism 9 applies the Chinese National Standard (CNS) A4 for each row and paper size of the total data block (18 2 bytes X 192 rows) stored in the buffer memory 2. Specifications (210X297 mm) -29- 579499 Α7 Β7 5. Description of the invention (27) (192 bytes) and an error correction code P0 (16 bytes) is generated. As a result, the ECC block added with the error correction codes PI and P0 is constructed for the total data block stored in the buffer memory 2. The buffer memory 2 has a sufficient capacity to hold a plurality of ECC blocks to ensure the function of storing and transmitting data of the autonomous computer until it is recorded on a recording medium, and is composed of, for example, DRAM. It may cause the data in the memory to be destroyed or a memory error to occur due to the joint state of the memory or the pattern of the data. When the error correction code P 0 is generated at this time, the error correction code P 0 becomes an error correction code generated based on the data including the memory error. The E C C block in the buffer memory 2 is read row by row (in units of 182 bytes) and stored in the row memory 3. The PI correction mechanism 10 uses the column memory 3 to perform PI correction, thereby correcting the memory error and recovering the original data (or the correct E C C block). The bank of memory 3 is composed of, for example, SR A M (static RAM), and can store a single row (182 bytes) of a PI sequence. The output data from the column memory 3 is sequentially sent to the modulation / synchronization adding mechanism 4, which processes 8/1 6 modulation and synchronization code addition, and outputs the result data as record data to the record media. Here, referring to FIG. 11 again, the functions of the above embodiment will be described. Figure 1 1 shows the situation where errors (such as the above-mentioned memory errors or errors caused by external noise 4 2) occur in the data portion of the E C C block output from buffer memory 2. This paper size applies Chinese National Standard (CNS) M specification (210X297 mm) n nn · I,-ulm > ^ n — / t-hr (Please read the precautions on the back before filling this page) Order the wisdom of the Ministry of Economic Affairs Printed by the Finance 4 Bureau Consumer Cooperative -30-579499 A7 B7 V. Description of the Invention (28) In the present invention, the error correction code PI is generated using data memory 1 before data is stored in buffer memory 2. Therefore, the error correction code PI in all the columns including 45 to 192 is an error correction code generated based on the original data. That is, the error correction code PI in FIG. 11 is an error correction code for the miserable data without error 42. On the other hand, the P0 generation and addition mechanism 9 and the buffer memory 2 are based on each line. (192 bytes) data to generate an error correction code P0. Therefore, the error correction code for column 4 1 (16 bytes) is an error correction code generated based on the data including the memory error 4 2. The error code is part 4 8 of the error correction code for the error correction code, although the code PI is first generated and added, and then the phone number P0 is generated and added, or the code P0 is first generated and added, and thereafter The code PI is generated and added to obtain the same code pattern. Printed by the Intellectual Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Here, the error correction code PI is the correct error correction code added to the original data before the error occurred. Therefore, the error correction code P 0 generated and added to the block of the error correction code P I is a correct error correction code generated based on the original data. However, the error correction code P 0 added to other lines (1 7 1) (not included in line 41 of line 1 72 shown in FIG. 11) is a correct error correction code. When the E C C block is sequentially read from the buffer memory 2 and the P I correction is performed in the column memory 3, the error 4 2 in the column 4 5 is simply applied with the P I correction. That is, the correct data list 4 5 is replied. Next step: For each of the P 0 rows generated by the incorrect data, the paper size is also applied to the Chinese National Standard (CNS) A4 specification (210X: 297 mm > ~ -31-579499 A7 B7 V. Description of the invention (29) (Please read the precautions on the back before filling this page) PI correction to restore the correct P 0 sequence. That is, the column 4 6 is applied with PI correction to correct a single bit. Group 4 3 is the same, the other columns (indicated by triangles) are applied with a PI correction to generate the correct P0 sequence. In the above processing, the PI correction uses column memory 3 and for all the ECC blocks The PI correction is not limited to this, but can be applied to each column marked with a sigma of the triangle to shorten the processing time. This is because the memory error 4 2 can be later Simple correction, if the p 0 sequence at the triangle position in the figure is the correct error correction code. In the above explanation, the ECC block of the P 0 block distributed one by one in the sum data block is used. At the timing In the ECC block, then The error correction code P 0 is a row-by-column distribution in the total data block as explained in Fig. 1 and Fig. 6. That is, the error correction code P 0 is distributed so that a single column of the error correction code P 0 is derived. Now it is in the 12-column data section. After that, the reproduction system of FIG. 17 will be explained. The Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperation Agreement will describe the function of the memory control mechanism 20. The memory control mechanism 20 Receive a request, and read from PI generation and joining mechanism 8, synchronous separation / demodulation mechanism 1 1, P0 generation and joining mechanism 9, P ◦ correction mechanism 9, PI correction mechanism 10, and column memory 3 Or store data. According to this request, the memory control mechanism 20 reads data from the buffer memory 2 or writes data to the buffer memory 2. At this time, the memory control mechanism 20 controls the data storage location Therefore, the standard of Chinese paper (CNS) A4 (210X297 mm) -32 · 579499 A7 B7 is applied without using this paper scale. 5. Invention description (31) and management can also be listed. Then, the explanation will be explained when PI correction Failed (or none Data reproduction during execution. When 6 or more memory errors occur in a single row, PI correction cannot be performed. When 6 or more memory errors occur in data in a single ECC block In this case, the PI calibration of P0 (16 columns) will fail. When an error exceeding the number of correctable errors is sensed during the PI calibration process, the used memory area is changed and the regeneration is completed. In this regeneration , The host computer is requested to transmit the data again. After that, the error correction code PI added data is stored in the buffer memory 20 through the memory control mechanism 20. At this time, the used memory area is caused by an error. An error area or a blank area different from the error area is replaced. When the number of errors exceeds the error correctable number in each column of the area where the error correction code P 0 is stored, the regeneration is performed in the following manner. At the time of the regeneration, the total data block (including the error correction code PI) of 192 rows X 1 92 bytes in the first storage area in the buffer memory 2 is moved to the buffer memory 2 In the second storage area. After each column is subjected to the P I correction process, the second storage area of the bit in the buffer memory 2 is used to perform the P 0 generation and addition process again. In this case, the regeneration can be performed within the system without requiring the host computer to transmit the data again. Figure 19 is a diagram to help explain the paper size of the data in the buffer memory 2 applicable to the Chinese National Standard (CNS) A4 wash (210X297 mm) (Please read the note on the back before filling this page) Order Printed by the Employees' Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs-34 · 579499 A7 _ B7 _ V. Description of Invention (32) Mobile. (Please read the precautions on the back before filling this page) The data moving mechanism 24 will start to move from the stored E C C block (η) of A 〇 to the blank area of the header address A3. At this time, the mobile data includes a memory error contained in the address A 0 area. Performing PI correction for each column will cause these memory errors to be corrected. The data using the PI correction process is applied, and the P0 generation and addition processes are performed. If the number of memory errors at this time is 5 or less, the generated error correction code P 0 can be corrected by PI correction processing. The operation of data reproduction will be described using FIG. 17. The playback data read from the recording medium by the optical head is introduced to the synchronization separation / demodulation mechanism 11 · The synchronization separation / demodulation mechanism 1 1 senses and separates synchronization from the playback data, and The data to which 8/16 modulation is applied is demodulated, thereby generating a recording section. Because the error occurred due to disc defects or noise while recording or reproducing data to / from the recording medium, the error can be included in the data in the recording section. The read-out recording sections are sequentially stored in the buffer memory 2 through the memory mechanism 20, and 16 recording sections are put together to form an ECC having 18 2 rows X 2 0 8 columns. Block in buffer memory 2. The P0 correction mechanism 14 and the PI correction mechanism 10 apply error correction to an ECC block having 208 rows and X182 columns. The error correction E C C block reads the buffer memory 2 row by row from the buffer memory 2 in the order of data transmission and stores it in the bank memory. The PI correction mechanism 10 uses column memory 3 and applies the Chinese National Standard (CNS) A4 specification (210X297 mm) for each column paper size -35 · 579499 Printed by A7 of the Consumer Finance Cooperative of the 1st Bureau of Smart Finance of the Ministry of Economic Affairs _ B7_V. The invention explains (33) that 1 72 bytes perform correction. As a result, although a memory error occurs in the miscible data section in the buffer memory 2, the error can be corrected by p I correction. Then, the blendable cancellation mechanism 13 mixes the blended data and the blended data of the main data (204 bytes) in the blendable data section (or mutually excludes or processes the two data) , Thereby generating a data section before mixing. After that, the EDC error sensing mechanism 12 uses a 4-byte error sensing code (EDC) included in the data sector to sense an error in the data sector. If it senses that it has no errors in the data section, the data section will be transferred to the host computer. As described above, the present invention can be applied to a signal transmission / recording and reproduction apparatus that can execute error correction code generation processing without losing data, even when an error occurs in the memory. Further, the present invention can be applied to an inexpensive signal transmission / recording and reproduction device capable of recording data to a recording medium without losing original data, although it allows rise in memory errors to occur instead of simplifying defective memory Increased by inspection. The present invention can be further applied to various transmission / reception system devices in the digital transmission field. It includes wireless units such as mobile phones, transmission / reception terminals between computers, and television transmitter / receiver units. In the field of a recording and reproducing system, the present invention can be applied to a DVD unit, a CD unit, and a memory device using a communication function. As described above, in the present invention, it can provide a data processing method using an error correction code that can recover the original data even when an error (memory error) occurs in the memory, and a method of recording or reusing the method. ： II 4—, (Please read the precautions on the back before filling this page) The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -36- 579499 A7 B7 V. Description of the invention (34) System, and transmission and reception system using the method. —0 ------ 1T ------_ (Please read the notes on the back before filling out this page) The Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumer Cooperatives, printed this paper to apply Chinese National Standards (CNS) A4 size (210X297 mm) -37-