577140 A7 五、發明説明（ j务明領域 本發明是有關一種加強低介電材質（Low K Die|ectrjc) 層的結構強度的製造方法，且特別是適用於半導體製程之 上，可以解決後段封裝製程所遭遇的問題。 發明背景 在超大型積體電路（ULSI)的製程上，可以在]至2平 方公分面積的矽表面上配置數量多達數十萬個電晶體。並 且，為了增加積體電路的積集度，將提高連接各個電晶體 或是其他元件的金屬線之密度。所以，以往單一金屬層的 設計，將無法完成整個積體電路的連線工作，兩層以上的 金屬層設計，便逐漸成為許多積體電路製造所必需採用的 方式。以邏輯電路為例，目前積體電路所使用的金屬已達 六層。 隨著元件尺寸的縮小，相鄰導線的間距亦隨之縮小， 若無法有效降低做為導線間電性隔離的介電層之介電常 數，在窄小的空間中，平行的導線會在相鄰接^導線間產 生不必要的電容式（capacitive)與電感式（jnduct•丨ve)耦接 (⑶upling)，造成導線之間相互干擾，導致導線之間的電阻 -電容時間延遲（RC Time Delay)増加。特別是在經由平行導 線進行較高的傳輸資料速率時，電容式與電感式麵接將降 低資料的傳輸速率。而以此方式增加能量的耗損量，同時 2 本紙G度適用巾關家標準(CNS)A4規格(21Qx297公复y (請先閲讀背面之注意事項再填寫本頁) -訂· 線 經濟部智慧財產局員工消費合作社印製 577140 A7 B7 五、發明説明（） 亦限制了元件的效能。為此，一些低介電係數的材質被發 展出來以適用於形成内金屬介電層，例如黑鑽石（Black577140 A7 V. Description of the Invention (Field of the Invention) The present invention relates to a manufacturing method for enhancing the structural strength of a low dielectric material (Low K Die | ectrjc) layer, and is particularly suitable for use on a semiconductor process, and can solve the post-stage packaging. Problems encountered in the manufacturing process. BACKGROUND OF THE INVENTION In the ultra-large integrated circuit (ULSI) process, up to hundreds of thousands of transistors can be arranged on a silicon surface with an area of 2 to 2 square centimeters. In addition, in order to increase the number of integrated circuits The accumulation degree of the circuit will increase the density of the metal lines connecting the transistors or other components. Therefore, the design of a single metal layer in the past will not be able to complete the wiring work of the integrated circuit, and the design of more than two metal layers , It has gradually become a necessary method for the manufacture of many integrated circuits. Taking logic circuits as an example, the metal used in integrated circuits has reached six layers. With the shrinking of the component size, the distance between adjacent wires has also decreased. If the dielectric constant of the dielectric layer used as the electrical isolation between the wires cannot be effectively reduced, in a small space, parallel wires will be adjacent to each other. Unnecessary capacitive (capacitive) and inductive (jnduct • 丨 ve) coupling (CDupling) occurs between the wires, causing mutual interference between the wires, leading to an increase in the resistance-capacitance time delay (RC Time Delay) between the wires. Especially When the data transmission rate is higher through parallel wires, the capacitive and inductive surface connection will reduce the data transmission rate. In this way, the energy consumption is increased, and 2 paper G degrees are applicable to the household standard (CNS) ) A4 specification (21Qx297 public reply y (please read the precautions on the back before filling this page)-Order · Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 577140 A7 B7 5. The invention description () also limits the performance of the component For this reason, some materials with low dielectric constant have been developed to be suitable for forming inner metal dielectric layers, such as black diamond (Black Diamond).
Diamond’BD)，黑鑽石材質係以三甲基石浅與氧氣為前 驅物質經化學氣相沉積而形成的。低介電係數材質形成的 介電層可以降低電容式與電感式耦接，因而增加元件的效 能。 除了適用於銅製程的黑鑽石材質外，若需要更低介電 係數的材質，一般會將空氣導入介電層中而在介電層中形 成氣泡’其原理係藉用空氣的低介電係數（約為1 )來達成 降低導線間的電容式與電感式耦接，而減少導線之間的電 阻-電谷時間延遲，因而增加元件的效能的目的。現今在使 用低介電材質時會碰到以下的問題，低介電材質本身的硬 度不足，在加入氣泡之後，硬度更差，在後續化學機械研 磨及封裝的製程中，容易發生介電層滑動變形的情形。 習知解決這個問題的方法係在在形成低介電材質層後 再加上一次後處理（post Treatment)製程，後處理製程會在 低介電材質層表面產生較高比例的氧化狀態，可以提高低 介電材質層的硬度，使後續的化學機械研磨較易進行，但 是這個方法仍然無法使低介電材質層的強度增加而足以抵 抗後續封裝製程打線（Wire Bonding)時的機械力。常常 在後續封裝打線時，低介電材質層因為打線的機械力而嚴 重變形，而造成元件的失敗。 3 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) #· 訂· 經濟部智慧財產局員工消費合作社印製 577140 A7 ___ B7 五、發明説明（） 在半導體製程上’在晶片（Chip )上具有密集導線區 及獨立導線區’ 一般雄、集導線區均位於核心區（C〇「e Region )而獨立導線區均位於周邊區（perjphera| Region)，請參照第1圖，第1圖係繪示密集導線區及獨立 導線區之導線和插塞分佈密度之示意圖。密集導線區102 及獨立導線區104位於基底100之上。密集導線區1 〇2係 為元件，例如NM〇S、CMOS、記憶體記憶胞等等之所在， 而獨立導線區104則是適用於晶片在封裝時和導線連接的 位置。邊、集導線區102的元件（未繪示於圖上）經由内連 線（未繪示於圖上）和位於獨立導線區彳〇4的導線（插塞） 106連接。密集導線區1 〇2因為高集積度的設計，具有相 當多的元件（未繪示於圖上）’因此其導線（插塞）108相 當密集，而獨立導線區104的導線（插塞）1〇6則相當稀 疏’導線（插塞）106和108均為於低介電材料層彳1 〇之 内。在進行封裝時，將導線（未緣示於圖上）和插塞1 〇4 利用打線接合。在打線機械力的敲擊之下，獨立導線區1 〇4 低介電材質層108的強度不足以耐受打線機械力的敲擊因 而嚴重變形。因此，如何解決低介電材質層機械強度不足 成為一重要的課題。 發明目的與概述 有鑑於此，本發明的目的就是在提供一種加強低介電 (請先閲讀背面之注意事項再填寫本頁) #· 線一 經濟部智慧財產局員工消費合作社印製 4Diamond'BD). The black diamond material is formed by chemical vapor deposition using trimethyl spar and oxygen as precursors. A dielectric layer made of a low dielectric constant material can reduce the capacitive and inductive coupling, thereby increasing the performance of the device. In addition to the black diamond material suitable for the copper process, if a material with a lower dielectric constant is required, air is generally introduced into the dielectric layer to form bubbles in the dielectric layer. The principle is to borrow the low dielectric constant of air (About 1) to achieve the purpose of reducing the capacitive and inductive coupling between the wires, and reducing the resistance-electric valley time delay between the wires, thereby increasing the efficiency of the device. At present, when using low-dielectric materials, the following problems are encountered. The low-dielectric material itself has insufficient hardness. After adding bubbles, the hardness is worse. In the subsequent chemical mechanical polishing and packaging processes, the dielectric layer is prone to slip. Deformation. The conventional method to solve this problem is to add a post treatment process after the low dielectric material layer is formed. The post treatment process will generate a higher proportion of oxidation state on the surface of the low dielectric material layer, which can improve the The hardness of the low-dielectric material layer makes subsequent chemical-mechanical polishing easier, but this method still cannot increase the strength of the low-dielectric material layer and is sufficient to resist the mechanical force during subsequent wire bonding of the packaging process. Often, in the subsequent packaging and bonding, the low-dielectric material layer is severely deformed due to the mechanical force of the bonding, causing component failure. 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) # · Order · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 577140 A7 ___ B7 5 2. Description of the invention () In the semiconductor process, 'the chip has a dense wire area and an independent wire area' Generally, the male and collector wire areas are located in the core area (Co e) and the independent wire areas are located in the peripheral area. (Perjphera | Region), please refer to FIG. 1. FIG. 1 is a schematic diagram showing the distribution density of the wires and plugs in the dense conductive area and the independent conductive area. The dense conductive area 102 and the independent conductive area 104 are located on the substrate 100. The dense wire area 102 is the component, such as NMOS, CMOS, memory cells, etc., while the independent wire area 104 is suitable for the position where the chip is connected to the wire during packaging. Side and collecting wire areas The components of 102 (not shown in the figure) are connected via interconnects (not shown in the figure) and the wires (plugs) located in the independent wire area 彳 04. The dense wire area 1 〇2 is because of the high concentration the design of It has quite a lot of components (not shown), so its wires (plugs) 108 are quite dense, while the wires (plugs) 106 of the separate wire area 104 are quite sparse. The wires (plugs) 106 and 108 are all within the low-dielectric material layer 彳 10. When packaging, the wires (not shown in the figure) and the plug 104 are bonded by wire bonding. Under the impact of the mechanical force of the wire bonding, The strength of the low-dielectric material layer 108 is not strong enough to withstand the impact of the mechanical force of the wire and the deformation is severe. Therefore, how to solve the lack of mechanical strength of the low-dielectric material layer has become an important issue. Purpose and Summary of the Invention In view of this, the purpose of the present invention is to provide a low dielectric strength (please read the precautions on the back before filling out this page) # · Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4
五、發明説明（） 材質層結構強度的製造方法，依此方法可以增強低介電材 質層的結構強度。 本發明的另一目的是在提供一種加.強低介電材質層結 構強度的製造方法，依此方法可以使低介電材質層可以耐 受封裝製程時打線的機械力的敲擊。 根據本發明之上述目的，提出一種加強低介電材質層 結構強度的製造方法，係在獨立導線區的金屬導線兩側， 形成擬線（Dummy line)或擬插塞（Dummy p丨ug)等擬層 (Drn^my Layer)，形成擬線或擬插塞的材質可以為機械^ 度較高的介電材質，例如氧化矽、氮化矽及氮氧化矽等等。 形成擬線的方法係先在低介電材料層上形成一光阻層，圖 案化光阻層形成開口，開口暴露出位於獨立導線區金屬導 線兩側之低介電材料層。 經濟部智慧財產局員工消費合作社印製 以圖案化光阻層為罩幕，蝕刻低介電材料層而形成溝 渠或介層窗’溝渠或介層窗暴露出位於低介電材料异下方 之材質層。接著，沉積一高機械強度的介電材質而在獨立 導線區的金屬導線兩側，形成擬線或擬插塞。擬線或擬插 塞因為具有高機械強度，因此在封裝製程時可耐受打線的 機械力的敲擊，如此低介電材料層將不會因為打線的機械 力的敲擊而嚴重變形。 # 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 577140 A7V. Description of the invention () The manufacturing method of the structural strength of the material layer, according to which the structural strength of the low-dielectric material layer can be enhanced. Another object of the present invention is to provide a manufacturing method for increasing the structural strength of a strong low-dielectric material layer. According to this method, the low-dielectric material layer can withstand the impact of the mechanical force of the wire during the packaging process. According to the above object of the present invention, a manufacturing method for enhancing the structural strength of a low-dielectric material layer is proposed, which is formed on both sides of a metal wire in an independent wire region to form a dummy line or a dummy plug. Drn ^ my Layer. The material forming the pseudo-line or pseudo-plug can be a dielectric material with a higher mechanical degree, such as silicon oxide, silicon nitride, and silicon oxynitride. The method of forming a pseudo-wire is to first form a photoresist layer on the low-dielectric material layer, and the patterned photoresist layer forms an opening, which exposes the low-dielectric material layer on both sides of the metal wire in the independent wire region. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a patterned photoresist layer as a mask, and etched a low-dielectric material layer to form a trench or a dielectric window. The trench or the dielectric window exposed the material below the low-dielectric material. Floor. Next, a high mechanical strength dielectric material is deposited to form a pseudo-wire or pseudo-plug on both sides of the metal wire in the independent wire region. The pseudo-wire or pseudo-plug has high mechanical strength, so it can withstand the impact of the mechanical force of the wire during the packaging process. Such a low dielectric material layer will not be seriously deformed by the mechanical force of the wire. # This paper size applies to China National Standard (CNS) A4 (210X297 mm) 577140 A7
五、發明説明（） 經濟部智慧財產局員工消費合作社印製 現以一銅金屬鑲嵌製程為例，來說明本發明所提供的 銅金屬層的製造方法實際的應用。 第1圖至第3圖所示，為根據本發明一較佳實施例之 一種雙金屬鑲嵌内連線的製造方法。 請參照第1圖，第1圖係繪示晶片上密集導線區及 獨立導線區導線及插塞分佈密度之示意圖。密集導線區1 〇2 及獨立導線區104位於基底1〇〇之上。一低介電係數材質 層110形成於基底100之上。基底彳00上具有已經完成的 各種電路及元件結構（未繪示於圖上）。密集導線區1〇2係 為兀件，例如NMOS、CMOS、記憶體記憶胞等等（未繪 示於圖上）之所在，而獨立導線區1〇4則是適用於晶片在 封裝時和導線連接的位置，亦即所謂的打線區 (Wire-bonding Region)。密集導線區1〇2的元件（未繪 示於圖上）經由内連線（未繪示於圖上）和位於獨立導線 區彳04的導線（插塞）1 〇6連接。密集導線區1 〇2因為高 集積度的設計，具有相當多的元件（未繪示於圖上），因此 其導線（插塞）108相當密集，而獨立導線區1 〇4的導線 (插塞）106則相當稀疏，導線（插塞）1 〇6和彳〇8均為 於低介電材料層110之内。 睛參照第2圖’在低介電材料層11 〇上形成一光阻層 112，形成光阻層112的方法包括一旋塗塗佈製程。以一圖 6 本紙張尺度適用中國國家標準(CNS)A4規格(21〇χ297公楚) (請先閲讀背面之注意事項再填寫本頁) P· 訂· 線一 577140 A 7 ___________ B7 五、發明説明（） 案化光罩·（未繪示於圖上）為罩幕對光阻層進行曝光，經 顯影製程形成圖案化光阻層而在光阻層彳彳2形成開口 114。開口 114暴露出位於獨立導線區彳〇4導線（插塞） 106兩側之低介電材料層彳1〇。 請參照第3圖，以圖案化光阻層112為罩幕，以一非 均像蝕刻製程蝕刻開口 114所暴露出的低介電材料層1) 〇 至低介電材料層110下方的材質層（未繪示於圖上）暴露 出來為止而形成溝渠（介層窗）彳18,溝渠（介層窗）118 暴露出位於低介電材料層110下方之材質層。 請繼續參照第3圖，形成一介電材質填滿溝渠（介層 窗）118並覆蓋於低介電材料層1彳〇之上，接著，以一平 坦化製私移除位於低介電材料層11Q上表面上方之介電材 質而形成擬線（插塞）116於溝渠（介層窗）118之内。形 成擬線（插塞）116的介電材質可以為機械強度較高的介 電材質，例如氧化矽、氮化矽及氮氧化矽或其任意之組合 等等。 在獨立導線區的金屬導線兩側，形成擬線或擬插塞。 擬線或擬插塞因為係由高機械強度的介電材質所形成，因 此在後續封裝製程時可耐受打線的機械力的敲擊，如此低 介電材料層將不會因為打線的機械力的敲擊而嚴重變形。 7 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) .......%: (請先閲讀背面之注意事項再場寫本頁) 訂· 線 經濟部智慧財產局員工消費合作社印製 577140 A7 --B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 形成彳疑線（插塞）116的材質除了介電材質外也可以 使用導體材質，例如多晶矽或是金屬。使用導體材質來形 成擬線（插塞）116 ’特別是使用金屬當然可以提高低介電 材料層的機械強度，但是卻會增加額外的電容和電感，另 外，若發生誤對準容易使應該絕緣的位置導通，因此，對 準的精確度必須相當的高，反而會提高製程上的難度。導 體材質¥然也可用來形成擬線（插塞）116，但其整體的效 益比不上使用介電材質所形成的擬線（插塞）彳彳6。 在進行封裝時，打線的動作會將外部導線和晶片的接 點接合，而一般而言，晶片的接點即位於獨立導線區1〇4。 在打線機械力的敲擊之下，低介電材質層110的強度不足 以耐受打線機械力的敲擊因而嚴重變形，但在獨立導線區 104的低介電材質層11〇加上擬線（插塞）116可以強化低 介電材質層110的結構強度。形成擬線（插塞）116的位 置較佳是位於導線（插塞）的兩側或是周圍，但是這需依 金屬導線的設計而定。在最上層的低介電材質層中擬線（插 塞）當然係位於導線（插塞）的兩側或是周圍，但是在下 層的低介電材質層中則需將擬線（插塞）設置於晶片的接 點的下方，來增強低介電材質層的結構強度，此時，擬線 (插塞）就不需要設置於導線（插塞）的兩側或是周圍了。 另外，獨立導線區104並非均位於周邊區，也有可能 位於核心區，為了增強介電材質層的結構強度，也可以在 8 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再場寫本頁) ^•. -訂· 線:··V. Description of the invention () Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Take a copper metal inlay process as an example to illustrate the practical application of the copper metal layer manufacturing method provided by the present invention. FIG. 1 to FIG. 3 show a method for manufacturing a bimetal mosaic interconnection line according to a preferred embodiment of the present invention. Please refer to FIG. 1. FIG. 1 is a schematic diagram showing the distribution density of the wires and plugs in the dense wire area and the independent wire area on the chip. The dense conductive line region 102 and the independent conductive line region 104 are located on the substrate 100. A low dielectric constant material layer 110 is formed on the substrate 100. Various circuits and component structures have been completed on the base 彳 00 (not shown in the figure). The dense wire area 102 is a component such as NMOS, CMOS, memory cells, etc. (not shown in the figure), while the independent wire area 104 is suitable for chip and wire during packaging. The location of the connection is the so-called wire-bonding region. The components (not shown in the figure) of the dense lead area 102 are connected via interconnects (not shown) and the leads (plugs) 106 located in the separate lead area 彳 04. Dense wire area 1 〇 Because of the high integration design, there are quite a lot of components (not shown in the figure), so its wires (plugs) 108 are quite dense, while the wires of the independent wire area 104 (plugs) ) 106 is quite sparse, and the wires (plugs) 106 and 108 are both within the low-dielectric material layer 110. Referring to FIG. 2 ', a photoresist layer 112 is formed on the low-dielectric material layer 110. A method of forming the photoresist layer 112 includes a spin coating process. Take a picture 6 This paper size applies the Chinese National Standard (CNS) A4 specification (21〇297297) (Please read the precautions on the back before filling this page) P · Order · Line 1 577140 A 7 ___________ B7 V. Invention Explanation () A patterned photomask (not shown in the figure) exposes the photoresist layer for the mask, forms a patterned photoresist layer through the development process, and forms an opening 114 in the photoresist layer 彳 彳 2. The opening 114 exposes a low-dielectric material layer 10 on both sides of the independent-conducting-region area 104 (plug) 106. Referring to FIG. 3, the patterned photoresist layer 112 is used as a mask, and the low-dielectric material layer exposed by the opening 114 is etched by a non-uniform etching process. 1) The material layer below the low-dielectric material layer 110 (Not shown in the figure) trenches (dielectric windows) 彳 18 are formed until they are exposed, and the trenches (dielectric windows) 118 expose the material layer under the low-dielectric material layer 110. Please continue to refer to FIG. 3 to form a dielectric material to fill the trench (dielectric window) 118 and cover the low dielectric material layer 1 彳 〇, and then remove the low dielectric material by a planarization process. The dielectric material above the upper surface of the layer 11Q forms a pseudo-line (plug) 116 within the trench (dielectric window) 118. The dielectric material forming the pseudo-line (plug) 116 may be a dielectric material with high mechanical strength, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. On both sides of the metal wire in the independent wire area, a pseudo wire or pseudo plug is formed. The pseudo-wire or pseudo-plug is formed by a dielectric material with high mechanical strength, so it can withstand the impact of the mechanical force of the wire during the subsequent packaging process. Such a low dielectric material layer will not Percussion and severe deformation. 7 This paper size applies to China National Standard (CNS) A4 (210x297 mm) .........%: (Please read the notes on the back before writing this page) Staff of the Intellectual Property Bureau of the Ministry of Economics Printed by the Consumer Cooperative 577140 A7 --B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Forming suspicious lines (plugs) 116 In addition to dielectric materials, conductor materials can also be used, such as polycrystalline silicon or It's metal. Using conductor materials to form pseudo wires (plugs) 116 'Especially the use of metal can certainly improve the mechanical strength of the low-dielectric material layer, but it will add additional capacitance and inductance. In addition, if misalignment occurs, it should be insulated. The position is turned on, so the accuracy of the alignment must be quite high, which will increase the difficulty of the process. The conductor material ¥ can also be used to form a pseudo-line (plug) 116, but its overall benefit is not as good as a pseudo-line (plug) 彳 彳 6 formed using a dielectric material. During packaging, the bonding operation will bond the external wires with the contacts of the chip. Generally, the contacts of the chip are located in the independent wire area 104. Under the impact of the bonding mechanical force, the low dielectric material layer 110 is not strong enough to withstand the impact of the bonding mechanical force and is severely deformed. However, the low dielectric material layer 11 of the independent wire region 104 plus a pseudo wire (Plug) 116 can strengthen the structural strength of the low-dielectric material layer 110. The position where the pseudo-line (plug) 116 is formed is preferably on both sides or around the wire (plug), but this depends on the design of the metal wire. In the upper layer of low-dielectric material, the pseudo-lines (plugs) are of course located on the sides or around the wires (plugs), but in the lower-layer low-dielectric material layer, the pseudo-lines (plugs) are required. It is arranged below the contacts of the chip to enhance the structural strength of the low-dielectric material layer. At this time, the pseudo-line (plug) does not need to be provided on both sides or around the wire (plug). In addition, the independent lead areas 104 are not all located in the peripheral area, but may be located in the core area. In order to enhance the structural strength of the dielectric material layer, the Chinese National Standard (CNS) A4 specification (210X297 mm) can also be applied on 8 paper sizes ( (Please read the notes on the back before writing this page) ^ •. -Order · Line: ··
導線的兩側設置擬線（插塞）。 、=然本發明已以一較佳實施例揭露如上，然其並非用 以限疋本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 遵圍當視後附之申請專利範圍所界定者為準。 式之簡覃說明 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： (請先閲讀背面之注意事項再填寫本頁) i·. 、一-吞 第1圖至第3圖所示，為根據本發明一較佳實施例之 種加強低介電材質層結構強度的製造方法。 圖式之標記說明 1〇〇:基材 102 ··密集導線區 104 ··獨立導線區 106、108 :導線（插塞） :低介電係數材質層 112 :光阻層 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 線 經濟部智慧財產局員工消費合作社印製 577140 A7 B7 五、發明説明（) 114 :.光阻開口 116 ··擬線（插塞） 11 8 :溝渠（介層窗） (請先閱讀背面之注意事項再填寫本頁) έ·· -訂· 線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)Phantom lines (plugs) are provided on both sides of the wire. The present invention has been disclosed as above with a preferred embodiment, but it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. Therefore, the warranty of the present invention shall be determined by the scope of the appended patent application. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with a preferred embodiment and the accompanying drawings, as follows: (Please read first Note on the back page, please fill in this page again) i .., I-Thumb. As shown in Figures 1 to 3, this is a manufacturing method for enhancing the structural strength of a low-dielectric material layer according to a preferred embodiment of the present invention. Explanation of markings on the drawing 100: Base material 102 · Dense wire area 104 · Independent wire area 106, 108: Wire (plug): Low dielectric constant material layer 112: Photoresist layer This paper is applicable to China Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 577140 A7 B7 V. Description of the invention () 114: Photoresistive opening 116 ·· Pseudo-line (plug) 11 8: Ditch (Interlayer window) (Please read the precautions on the back before filling in this page.) ·· -Order · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to China National Standard (CNS) A4 (210X297) (Centimeter)