471147 6767twf.doc/006 A7 五、發明說明（/ ) 本發明是有關於一種晶片焊墊結構及其製程，且特 別是有關於一種應用於銅導線製程之焊墊結構及其製程。 當積體電路的積集度增加，使得晶片的表面無法提 供足夠的面積以製作所需的內連線時，爲了配合金氧半導 體(MOS)電晶體縮小後所需增加的內連線需求，多重金屬 化製程便逐漸成爲許多積體電路元件所採用的方式。通 常，M〇S電晶體各極與金屬層之間，係以介電層加以隔離， 並藉由接觸窗插塞(contact plug)連接；而各個金屬層之間， 亦使用介電層隔離。並以介層窗插塞(via plug)進行連接。 然而，爲增加接觸窗插塞與電極（或金屬層）之間和介層窗 插塞與各金屬層之間的附著能力，以及避免金屬插塞與矽 介面的尖峰（spike)現象，一般會於插塞形成之前，先形成 一層阻障層（barrier layer)的導電材料。 對半導體元件後段(backend)製程而言，隨著金屬線寬 (width of metal line)的日漸縮小’金屬線所承受之電流密度 (cmrent density)，相對地逐漸增大，使得傳統以鋁金屬爲 主所形成之金屬線’遭受到電遷移(electr〇n migrati〇n，EM) 效應的影響，進而導致元件之可靠度(reUablllty)降低。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 爲解決上述半導體元件進入深次微米製程時所遭遇 之課題’使用電遷移效應極小之銅金屬，就成了所有半導 體元件製造者一致的選擇。 然而’銅金屬本身具有不易被一般蝕刻氣體所飩刻 的特性，因此銅金屬導線的製作，就不能再以傳統之製造 方法來完成。針對此課題，一種金屬鑲嵌的製程於是被提 3 本紙張尺度適用中國國$票準（CNS)A4 ^lT(2j〇 __ 297公釐） 4V114 Λ7 B7 6767twf. doc/006 五、發明說明（2) 出。 第1A-1C圖係繪示傳統銅金屬鑲嵌結構之製程剖面 示意圖。 請參照第1A圖，形成一層介電層110 ’而此介電層 110形成在一基底100上。此介電層110可以是內層介電 材料（丨nter-layer dielectric)，也可以是內金屬介電層（intermetal dielectric ， IMD) 。 接著 ，利用 微景多 倉虫亥 U 技術 ，在此 介電層110中形成開口 112。形成一層阻障層114，共形 地覆蓋開口 112與介電層110。然後，形成一銅金屬層(未 繪示於圖）覆蓋此阻障層且塡滿開口 112。 接著請參考第1B圖，使用化學機械硏磨法（chenncal mechanical polishing，CMP)將覆蓋於介電層110表面之阻 障層114及銅金屬層去除，以形成銅導線116及阻障層 114，如此便完成銅金屬鑲嵌結構的製造。最後，再覆蓋 一層介電層120，形成如第1B圖所示之結構。 接著，視電路佈置的需要，可以上述之方式形成多層 銅鑲嵌結構。在本具體實施例裡，係以三層內連線之結構 作例示性說明，其中各個銅金屬導線層116，132，152分 別由阻障層114，134，154所圍繞，其間的介電層120，140 中亦形成介層窗插塞123，143(vh plug)作爲銅金屬導線層 116，132，152間之電性連接，如第1C圖所示◦介層窗插 塞123，143的材料通常爲導電金屬，例如鋁、銅或鎢， 亦可以藉由形成銅金屬導線層116，132，152時，利用雙 金屬鑲嵌製程（dual damascene)同時形成於介電層120， 4 本紙張尺度適用中國國家標準（CNS)M規格（210 X 297公髮） (請先閲讀背面之注意事項再填寫本頁) 訂---------線— 經濟部智慧財產局員工消費合作社印製 47114? A7 B7 6767twf. doc/00 6 五、發明說明（彡） 140 中。 最後，在所得之多層銅鑲嵌結構上形成一保護層161。 該保護層161的材料例如是氮化物。然後保護層161中定 義出開口 163,暴露出部分銅金屬導線層152,並塡入一 金屬層，其材質比如是鋁，而經由定義形成銲墊170，以 作爲對外之接點。 在傳統的銅鑲嵌製程裡，多半利用低介電係數材質， 例如旋塗式玻璃（SOG)作爲介電層的材料形成於導線間， 以避免導線過於接近而產生電容效應。由於低介電係數材 質本身質地很軟’因此其在封裝打線時承受打線力量的能 力不佳，容易造成下陷或變形。再加上銅與低介電係數材 質之間的黏著性不好，所以當低介電係數材質受到封裝打 線力量下陷或變形時，因爲與金屬銅黏著性不佳而導致其 界面處剝離或物理性接觸不良，造成可靠性降低。 有鑑於此’本發明人爲了係提出一種晶片焊墊結構及 其製程，可以應用於銅導線之晶片中，以提高晶片封裝的 可靠性。 依照本發明上述及其他目的，提出一種晶片銲墊結構， 在銅導線的佈局上，底部銅鑲嵌金屬層配置於元件區域及 焊墊區域，其餘之銅鑲嵌金屬層僅配置於元件區域，而焊 墊區域的介電層形成一開口以露出部份底部銅鑲嵌金屬 層，而形成一焊墊於開口中與底部銅鑲嵌金屬層電性連 接。藉由本發明之晶片焊墊結構，封裝的打線製程中，直 接受力於底部銅鑲嵌金屬層’而非銅鑲嵌金屬層間的介電 5 本紙張尺度適用中國國家標準（CNS)/\4規格（210 X 297公釐） ------------*.<·-------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 471147 6767twf.doc/006 Λ7 B7 經濟部智建財產局員工消赀合作社印^^ 五、發明說明（4) 層，可以解決介電材料與金屬之間因兩者黏著性不佳，在 後段製程裡受到打扯力量而在其界面處發生剝離或物理性 接觸不良的問題。亦可以解決因爲介電層柔軟，造成打線 困難的問題。 因此，本發明亦提出一種對應上述結構之製程，其 包括提供一基底，其具有銲墊區域及元件區域；接著形成 多個元件配置於元件區域。形成一金屬內連線結構於元件 上，並與元件電性連接，其中金屬內連線結構至少由多層 圖案化銅金屬層及多層介電層交替疊合形成，介電層分別 具有多個介層窗插塞，使得圖案化銅金屬層彼此電性連 接，底部圖案化銅金屬層，其配置於元件區域及該焊墊區 域，其餘之圖案化銅金屬層僅配置於元件區域。然後定義 介電層，於焊墊區域形成多個開口，用以暴露出部分底部 圖案化銅金屬層。形成一金屬層於金屬內連線結構表面， 並定義金屬層以形成多個銲墊，分別配置於開口及開口附 近的區域，且焊墊分別與底部圖案化銅金屬層電性連接。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1A到1C圖係示意地顯示一種習知鑲嵌結構之製法； 第2A-2D圖係爲示意地顯示根據本發明之一較佳具體 實施例的鑲嵌結構之製法；及 第3圖係爲根據本發明之一較佳具體實施例，顯示具 6 (請先閱讀背面之注意事項再填寫本頁) -------訂·-------- 丨 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 471147 6767twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（爻） 有元件區域與銲墊區域之積體電路元件的槪示圖。 圖式標號說明 100、200、300 :基底 110 、 120 、 140 、 220 、 230 、 240 、 330 、 332 、 334 、 336 、 338 :介電層 112、163、214、260、344 ·•開口 114、134、154、216 :阻障層 116、132、152 :銅金屬導線層 161、250、340 :保護層 123、143、316、318、342 :介層窗插塞 170、270、350 :焊墊 202、302 :焊墊區域 204、304 :元件區域 212、320 :底圖案化銅金屬層 210 第一介電層 306 元件 308 隔離結構 310 圖案化導電層 312、314 :內介電層 322、324 :圖案化銅金屬層 實施例 第2A到2E圖係爲繪示根據本發明之一較佳具體實施 例，一種結構之製法的槪略流程剖面圖。 請參考第2A圖，首先提供一基底200，其具有元件區 7 本紙張尺度適用中國國家標準（CNS)A^丨規格（2丨〇 X 297公楚） I i I I--I I I I I I I «—III— — — ---I I I I I I - (請先閱讀背面之注意事項再填寫本頁) 471147 6767twf.doc/〇〇6 Λ7 B7 五、發明說明（6) 域204及焊墊區域202，而在元件區域形成由多個元件(未 繪示），比如金氧半電晶體(MOS)。接著在元件上形成一多 層金屬內連線結構，此金屬內連線結構可以由多層圖案化 銅金屬層及介電層構成，以可以由多晶矽形成之多層圖案 化導電層及內~介電層，與多層圖案化銅金屬層及介電層所 共同構成。關於多晶矽內連線製程，爲熟習該技術者所知 悉，在此不再贅述。對於底圖案化銅金屬層的製程爲，在 基底200上形成一第一介電層210。在第一介電層210內， 利用例如光微影技術形成一開口 214。在已形成開口 214 的第一介電層210上形成一阻障層216，其材質比如是氮 化鈦，並形成一銅金屬層。利用化學機械硏磨技術（CMP) 第一介電層210表面的阻障層216及銅金屬層，形成一底 圖案化銅金屬層212。而此底圖案化銅金屬層212之佈局 配置於元件區域204及焊墊區域202。 請參考第2B圖，在底圖案化銅金屬層212上形成多層 介電層及圖案化銅金屬層，然而底圖案化銅金屬層212上 方的圖案化銅金屬層佈局僅配置於元件區域204,而不配 置於焊墊區域202。因此，焊墊區域202中底圖案化銅金 屬層212上僅覆蓋介電層。由於本發明主要針對焊墊結構， 所以僅繪示焊墊區域202之結構進行說明。然而圖案化銅 金屬層可以藉由介電層中的介層窗插塞及線路佈局，與底 圖案化銅金屬層212電性連接。在此，以三層介電層爲例 作說明，亦即在焊墊區域202中底圖案化銅金屬層212上 形成介電層220，230及240，而在介電層220，230及240 8 (請先閱讀背面之注意事項再填寫本頁)471147 6767twf.doc / 006 A7 V. Description of the Invention (/) The present invention relates to a wafer pad structure and a process therefor, and more particularly to a pad structure and a process used in a copper wire process. When the accumulation degree of the integrated circuit is increased, so that the surface of the wafer cannot provide enough area to make the required interconnects, in order to meet the increased interconnect requirements required after the reduction of metal oxide semiconductor (MOS) transistors, Multiple metallization processes have gradually become the approach adopted by many integrated circuit components. Generally, the MOS transistors are separated from the metal layer by a dielectric layer and connected by a contact plug; the metal layers are also isolated by a dielectric layer. And connect via via plug. However, in order to increase the adhesion between the contact window plug and the electrode (or metal layer) and the interlayer window plug and the metal layers, and to avoid the spike phenomenon between the metal plug and the silicon interface, Before the plug is formed, a barrier layer is formed. For the backend process of semiconductor devices, as the width of metal line is shrinking, the current density (cmrent density) of the metal line is gradually increasing, making the traditional use of aluminum metal as The metal line formed by the main body suffers from the effect of electromigration (EM), which leads to a decrease in the reliability (reUablllty) of the device. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) To solve the above-mentioned problems encountered when the semiconductor components enter the deep sub-micron process, using copper metal with minimal electromigration effect, This results in a consistent choice for all semiconductor component manufacturers. However, the 'copper metal itself has a characteristic that it cannot be easily etched by a general etching gas, so the production of a copper metal wire cannot be completed by a conventional manufacturing method. In order to solve this problem, a metal inlaying process was drawn. 3 paper sizes are applicable to China's national standard (CNS) A4 ^ lT (2j〇__ 297 mm) 4V114 Λ7 B7 6767twf. Doc / 006 5. Description of the invention ( 2) Out. Figures 1A-1C are schematic cross-sectional views of the manufacturing process of a traditional copper metal mosaic structure. Referring to FIG. 1A, a dielectric layer 110 'is formed, and the dielectric layer 110 is formed on a substrate 100. The dielectric layer 110 may be an inner-layer dielectric (inter-layer dielectric) or an intermetal dielectric (IMD). Next, an opening 112 is formed in the dielectric layer 110 by using the micro-view multi-cylinder U-U technology. A barrier layer 114 is formed to cover the opening 112 and the dielectric layer 110 conformally. Then, a copper metal layer (not shown) is formed to cover the barrier layer and fill the opening 112. Next, referring to FIG. 1B, a chemical mechanical honing method (chenncal mechanical polishing (CMP)) is used to remove the barrier layer 114 and the copper metal layer covering the surface of the dielectric layer 110 to form a copper wire 116 and a barrier layer 114. This completes the manufacture of the copper metal mosaic structure. Finally, a layer of dielectric layer 120 is covered to form the structure shown in FIG. 1B. Then, depending on the needs of the circuit layout, a multilayer copper damascene structure can be formed in the manner described above. In this specific embodiment, a three-layer interconnect structure is taken as an illustrative illustration, in which each copper metal wire layer 116, 132, 152 is surrounded by a barrier layer 114, 134, 154, and a dielectric layer therebetween. 120, 140 also formed via window plugs 123, 143 (vh plug) as electrical connection between copper metal wire layers 116, 132, 152, as shown in Figure 1C. The material is usually a conductive metal, such as aluminum, copper, or tungsten. It can also be formed on the dielectric layer 120 at the same time by using a dual metal damascene process when the copper metal wire layers 116, 132, and 152 are formed. Applicable to China National Standard (CNS) M specification (210 X 297) (Please read the precautions on the back before filling out this page) Order --------- Line — Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives System 47114? A7 B7 6767twf. Doc / 00 6 V. Description of the invention (彡) 140. Finally, a protective layer 161 is formed on the obtained multilayer copper damascene structure. The material of the protective layer 161 is, for example, a nitride. Then, an opening 163 is defined in the protective layer 161, a part of the copper metal wire layer 152 is exposed, and a metal layer is inserted, the material of which is, for example, aluminum, and a pad 170 is formed through the definition as an external contact. In the traditional copper damascene process, materials with a low dielectric constant are mostly used, for example, spin-on-glass (SOG) as the material of the dielectric layer is formed between the wires to avoid the capacitive effect caused by the wires being too close. Because the low-dielectric-constant material itself is very soft ', its ability to withstand the bonding force during packaging and bonding is not good, and it is easy to cause sag or deformation. In addition, the adhesion between copper and the low-dielectric constant material is not good. Therefore, when the low-dielectric constant material is sunken or deformed by the packaging wire, the interface is peeled off or physically due to the poor adhesion to the copper metal. Poor sexual contact reduces reliability. In view of this, the present inventor proposes a wafer pad structure and a manufacturing process thereof, which can be applied to a copper wire wafer to improve the reliability of the chip package. According to the above and other objectives of the present invention, a wafer bonding pad structure is proposed. On the layout of copper wires, the bottom copper damascene metal layer is arranged in the component area and the pad area, and the remaining copper damascene metal layer is only arranged in the component area, and the bonding The dielectric layer in the pad area forms an opening to expose a portion of the bottom copper damascene metal layer, and a solder pad is formed in the opening to be electrically connected to the bottom copper damascene metal layer. With the wafer pad structure of the present invention, during the packaging process, the substrate is directly stressed by the copper inlay metal layer at the bottom, rather than the dielectric between the copper inlay metal layers. 5 This paper size applies the Chinese National Standard (CNS) / \ 4 specifications ( 210 X 297 mm) ------------ *. ≪ · ------- Order --------- (Please read the notes on the back before filling (This page) Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 471147 6767twf.doc / 006 Λ7 B7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the cooperatives’ seals ^^ 5. Description of the invention (4) layer, which can solve dielectric materials and metals Due to the poor adhesion between the two, peeling or poor physical contact occurred at the interface due to the pulling force in the subsequent process. It can also solve the problem of difficult wiring due to the soft dielectric layer. Therefore, the present invention also proposes a process corresponding to the above structure, which includes providing a substrate having a pad region and an element region; and then forming a plurality of elements to be disposed in the element region. A metal interconnect structure is formed on the component and electrically connected to the component. The metal interconnect structure is formed by at least multiple layers of patterned copper metal layers and multiple dielectric layers alternately stacked, and the dielectric layers each have multiple dielectric layers. The layered window plugs electrically connect the patterned copper metal layers to each other. The bottom patterned copper metal layer is disposed in the element region and the pad region, and the remaining patterned copper metal layers are disposed only in the element region. Then, a dielectric layer is defined, and a plurality of openings are formed in the pad area to expose a portion of the bottom patterned copper metal layer. A metal layer is formed on the surface of the metal interconnect structure, and the metal layer is defined to form a plurality of solder pads, which are respectively disposed in the opening and the area near the opening, and the solder pads are electrically connected to the bottom patterned copper metal layer respectively. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments and the accompanying drawings in detail, as follows: Brief description of the drawings: Figures 1A to 1C A method for manufacturing a conventional mosaic structure is shown schematically; Figures 2A-2D are schematic views for manufacturing a mosaic structure according to a preferred embodiment of the present invention; and Figure 3 is a preferred method according to the present invention Specific embodiment, display 6 (Please read the precautions on the back before filling out this page) ------- Order · -------- 丨 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 471147 6767twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (爻) A schematic diagram of integrated circuit components with component area and pad area. 100, 200, 300: substrates 110, 120, 140, 220, 230, 240, 330, 332, 334, 336, 338: dielectric layers 112, 163, 214, 260, 344 134, 154, 216: barrier layers 116, 132, 152: copper metal wire layers 161, 250, 340: protective layers 123, 143, 316, 318, 342: via window plugs 170, 270, 350: solder pads 202, 302: pad regions 204, 304: element regions 212, 320: bottom patterned copper metal layer 210, first dielectric layer 306, element 308, isolation structure 310, patterned conductive layer 312, 314: inner dielectric layers 322, 324 FIG. 2A to 2E of the embodiment of the patterned copper metal layer are schematic cross-sectional views illustrating a method for manufacturing a structure according to a preferred embodiment of the present invention. Please refer to FIG. 2A. First, a substrate 200 is provided, which has a component area of 7. The paper size is applicable to China National Standard (CNS) A ^ 丨 specifications (2 丨 〇X 297). I i I I--IIIIIII «—III — — — --- IIIIII-(Please read the notes on the back before filling this page) 471147 6767twf.doc / 〇〇6 Λ7 B7 V. Description of the invention (6) Domain 204 and pad area 202, and in the component area Formed by a plurality of elements (not shown), such as metal-oxide-semiconductor (MOS). Next, a multilayer metal interconnect structure is formed on the device. The metal interconnect structure can be composed of multiple patterned copper metal layers and dielectric layers, and a multilayer patterned conductive layer and internal dielectric can be formed of polycrystalline silicon. The layer is composed of a plurality of patterned copper metal layers and a dielectric layer. The polysilicon interconnect process is known to those skilled in the art and will not be repeated here. For the bottom patterned copper metal layer, a first dielectric layer 210 is formed on the substrate 200. An opening 214 is formed in the first dielectric layer 210 using, for example, a photolithography technique. A barrier layer 216 is formed on the first dielectric layer 210 where the opening 214 has been formed. The barrier layer 216 is made of, for example, titanium nitride, and a copper metal layer is formed. A barrier metal layer 216 and a copper metal layer on the surface of the first dielectric layer 210 are formed by chemical mechanical honing (CMP) to form a bottom patterned copper metal layer 212. The layout of the bottom patterned copper metal layer 212 is disposed in the device region 204 and the pad region 202. Please refer to FIG. 2B, a multilayer dielectric layer and a patterned copper metal layer are formed on the bottom patterned copper metal layer 212. However, the patterned copper metal layer layout above the bottom patterned copper metal layer 212 is only arranged in the device region 204. It is not disposed in the pad region 202. Therefore, only the dielectric layer is covered on the midsole patterned copper metal layer 212 in the pad region 202. Since the present invention is mainly directed to the pad structure, only the structure of the pad region 202 is illustrated for illustration. However, the patterned copper metal layer can be electrically connected to the bottom patterned copper metal layer 212 through the dielectric window plugs and wiring layout in the dielectric layer. Here, a three-layer dielectric layer is used as an example for description. That is, dielectric layers 220, 230, and 240 are formed on the patterned copper metal layer 212 in the pad region 202, and dielectric layers 220, 230, and 240 are formed. 8 (Please read the notes on the back before filling this page)
• - i *1 ϋ n n u 入：口、_ n n 1! n n n I I 經濟部智慧財產局貞工消f合作社印製 本紙張尺度適用中國國家標準（CNS)yVi規格（21ϋ x 297公釐） 471147 6767twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 之上形成一保護層250 ◦ 請參考第2C圖，接著以一圖案化光阻（未示出），利 用微影触刻技術在該保護層250、該些介電層220，230及 240裡面形成一開口 260，露出底圖案化銅金屬層212的部 份表面。 本發明所用之介電層220、230、240爲低介電係數材料， 例如氧化矽，氮化矽，氧氮化矽，磷矽玻璃（PSG)，硼磷 砂玻璃（BPG )’砂酸鹽及砂氧院等。其中，本發明介電層 的材料較佳爲矽酸鹽及矽氧烷等旋塗式玻璃（S〇G)的低 介電係數材料。該些介電層中相鄰介電層的材料可相同或 不同。形成該介電層的方法包括化學氣相沈積法（CVD)， 熱氧化方法及旋塗法。 保護層250的材質係爲質地較硬的材料，例如氮化石夕 及PSG等。該保護層可利用APCVD或PECVD等方式沈積 於該些介電層上。 保護層250、介電層220、230、240中形成開口 260的 步驟係可以利用一般常用的微影蝕刻技術進行。触刻方法 包括濕蝕刻方法，例如使用氫氟酸或氫氟酸混合溶液的濕、 蝕刻，及乾蝕刻方法，例如反應性離子蝕刻方法（rie)。 其中，較佳使用乾蝕刻方法，更佳使用反應性離子蝕刻方 法。 請參考第2D圖，去除該圖案化光阻之後，於該所得之 結構上沈積一金屬層（未示出）’其材質比如是鋁。接著 於預定位置上覆蓋一光阻（未示出）。在去除不要的金屬 9 本紙張尺度適用中國國家標準（CNS)A4規格（2.1〇 X 297公釐） -------------Ά--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 471147 6767twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（π ) 層部份後’得到一*婷塾270以利於最後兀件測試與構裝的 進行，其中，銲墊270位於開口 260及開口 260附近的保 護層250表面，且與底圖案化銅金屬層212電性連接。 實務上，在進行沈積之前可視需要先進行淸潔，以去 除蝕刻殘留物〜。淸潔晶片表面的方法係爲熟習此項技藝者 所知，故在此不再贅述。另外可以利用濕蝕刻或乾蝕刻方 式去除上述不要的銲墊材料。該濕蝕刻與乾蝕刻方式請參 考上述者。 第3圖係爲根據本發明之一較佳具體實施例，顯示具 有元件區域與銲墊區域之積體電路元件的槪示圖。 請參考第3圖，基底300具有元件區域304及焊墊 區域302，元件區域304具有元件306，且元件306間由隔 離結構308電性隔離。而內金屬內連線由多晶矽所形成之 圖案化導電層310構成，並以內介電層312、314形成電性 隔離，而圖案化導電層310係以介電層312中的介層窗插 塞316電性連接兀件306。而外金屬內連線，則由多層圖 案化銅金屬層320、322、324所構成，其間配置有介電層 330、332、334、336、338，而圖案化銅金屬層 320、322、 324皆以金屬鑲嵌的方式形成於介電層330、334、338中， 其結構如上述實施例所述，在此不再贅述。而圖案化銅金 屬層320、322、324間的電性連接，則藉由介電層332、336 中的介層窗插塞342達成；圖案化銅金屬層320、322、324 亦藉由內介電層314中的介層窗插塞318與內金屬內連線 電性連接。如圖所示’底圖案化銅金屬層320配置於元件 10 本紙張尺度適用中國國家標準（CNS)Al規格（210x297公釐） (請先閱讀背面之注意事項再填寫本頁) '4--------訂-------—線— 471147 6767twf. doc/00 6 Λ7 B7 五、發明說明（C| ) 區域304及焊墊區域302,而其他圖案化銅金屬層322、324 僅配置於元件區域304,因此底圖案化銅金屬層320在焊 墊區域302僅覆蓋介電層330、332、334、336、338。而開 口 344則貫穿介電層330、332、334、336、338及保護層340， 而暴露出焊墊區域302的底圖案化銅金屬層320。焊墊350 則配置於開口 344及其附近區域，並與底圖案化銅金屬層 320電性連接。 本發明中，保護層可以形成於焊墊層之前，亦可以在 定義完焊墊之後形成於焊墊之上，並藉由定義暴露出焊墊 表面。 由上述實施例可知’本發明之特徵在於針對金屬內連 線中銅導線的部分，在佈局上僅底部的銅導線層配置於焊 墊區域，而焊墊開口直接貫通其上方的介電層，焊塾則是 直接與底部銅導線層連接。當進行封裝打線時，由於直接 受力於底部銅導線層，其下方並無低介電材料，可避免車^ 墊效應(cushion effect)，提高打線良率，且可以提高焊墊與 焊線之結合性與打線可靠度。 經濟部智慧財產局P、工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 綜上所述’雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明’任何熟習此技藝者，在不脫離本 發明之精神和範圍內，當可作各種之更動與潤飾，因T此本 發明之保護範圍當視後附之申請專利範圍所界定者爲ρ。 11 本紙張尺度適用中國國家標準（CNS)A1規格⑵〇x的7公釐）•-i * 1 ϋ nnu Entry: 口, _ nn 1! Nnn II Printed by the cooperative organization of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Cooperative Society This paper is printed in accordance with the Chinese National Standard (CNS) and yVi specifications (21ϋ x 297 mm) 471147 6767twf .doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. A description of a protective layer 250 on top of the invention description (q) ◦ Please refer to Figure 2C, followed by a patterned photoresist (not shown), An lithography technique is used to form an opening 260 in the protective layer 250, the dielectric layers 220, 230, and 240 to expose a portion of the surface of the bottom patterned copper metal layer 212. The dielectric layers 220, 230, and 240 used in the present invention are low-dielectric-constant materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), and borophosphate sand glass (BPG). And sand oxygen hospital. Among them, the material of the dielectric layer of the present invention is preferably a low dielectric constant material of spin-on glass (SOG) such as silicate and siloxane. The materials of adjacent dielectric layers in the dielectric layers may be the same or different. Methods for forming the dielectric layer include a chemical vapor deposition (CVD) method, a thermal oxidation method, and a spin coating method. The protective layer 250 is made of a harder material, such as nitride nitride and PSG. The protective layer may be deposited on the dielectric layers by means of APCVD or PECVD. The steps of forming the openings 260 in the protective layer 250, the dielectric layers 220, 230, and 240 can be performed by a commonly used lithographic etching technique. The etching method includes a wet etching method such as wet, etching using a hydrofluoric acid or a mixed solution of hydrofluoric acid, and a dry etching method such as a reactive ion etching method (rie). Among them, a dry etching method is preferably used, and a reactive ion etching method is more preferably used. Please refer to FIG. 2D. After removing the patterned photoresist, a metal layer (not shown) is deposited on the obtained structure. The material is, for example, aluminum. Then, a photoresist (not shown) is covered on the predetermined position. Unwanted metal 9 This paper size applies Chinese National Standard (CNS) A4 specification (2.1〇X 297 mm) ------------- Ά -------- Order- -------- (Please read the notes on the back before filling out this page) 471147 6767twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (π) layer 'Obtain a Ting Ting 270 to facilitate the final component testing and assembly. The pad 270 is located on the opening 260 and the surface of the protective layer 250 near the opening 260 and is electrically connected to the bottom patterned copper metal layer 212. In practice, cleaning can be performed as needed to remove etching residues ~ before depositing. The method of cleaning the surface of the wafer is known to those skilled in the art, so it will not be repeated here. In addition, the above-mentioned unnecessary pad materials can be removed by wet etching or dry etching. Please refer to the above for wet and dry etching methods. Fig. 3 is a schematic diagram showing a integrated circuit element having a component region and a pad region according to a preferred embodiment of the present invention. Referring to FIG. 3, the substrate 300 has a device region 304 and a pad region 302, the device region 304 has a device 306, and the devices 306 are electrically isolated by an isolation structure 308. The inner metal interconnect is composed of a patterned conductive layer 310 formed of polycrystalline silicon, and is electrically isolated by the inner dielectric layers 312 and 314. The patterned conductive layer 310 is formed by a dielectric window plug in the dielectric layer 312. 316 电 连接 臂 件 306。 316 electrically connected to the element 306. The outer metal interconnect is composed of a plurality of patterned copper metal layers 320, 322, and 324, with dielectric layers 330, 332, 334, 336, and 338 disposed therebetween, and the patterned copper metal layers 320, 322, and 324. They are all formed in the dielectric layers 330, 334, and 338 in a metal damascene manner, and their structures are as described in the above embodiment, which will not be repeated here. The electrical connection between the patterned copper metal layers 320, 322, and 324 is achieved through the dielectric window plugs 342 in the dielectric layers 332 and 336; the patterned copper metal layers 320, 322, and 324 are also internally connected. The dielectric window plug 318 in the dielectric layer 314 is electrically connected to the inner metal interconnect. As shown in the figure, 'The bottom patterned copper metal layer 320 is arranged on the element 10. This paper size applies to the Chinese National Standard (CNS) Al specification (210x297 mm) (Please read the precautions on the back before filling this page)' 4-- ------ Order --------- Line — 471147 6767twf.doc / 00 6 Λ7 B7 V. Description of the invention (C |) area 304 and pad area 302, and other patterned copper metal layer 322 And 324 are disposed only in the element region 304, so the bottom patterned copper metal layer 320 covers only the dielectric layers 330, 332, 334, 336, and 338 in the pad region 302. The opening 344 penetrates the dielectric layers 330, 332, 334, 336, 338 and the protective layer 340, and exposes the bottom patterned copper metal layer 320 of the pad region 302. The soldering pad 350 is disposed in the opening 344 and its vicinity, and is electrically connected to the bottom patterned copper metal layer 320. In the present invention, the protective layer may be formed before the pad layer, or may be formed on the pad after the pad is defined, and the pad surface is exposed by definition. It can be known from the above embodiments that the present invention is characterized in that for the portion of the copper wire in the metal interconnect, only the bottom copper wire layer is arranged in the pad area in the layout, and the pad opening directly penetrates the dielectric layer above it. The solder pad is directly connected to the bottom copper wire layer. When packaging and wiring, because it is directly stressed by the bottom copper wire layer, there is no low-dielectric material underneath it, which can avoid the cushion effect, improve the yield of wiring, and improve the bonding pads and bonding wires. Combinability and reliability. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives (please read the precautions on the back before filling out this page). In summary, 'Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in this art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined as the scope of the appended patent application as ρ. 11 This paper size applies to China National Standard (CNS) A1 size 7 × 7 mm)