TW575910B - Film or layer of semiconducting material, and process for producing the film or layer - Google Patents

Abstract

Semiconductor film or layer is made by: producing structures of repeating recesses (2) of prescribed geometry on a semiconductor material surface; thermally treating until a layer with periodically repeating hollow chambers (3) forms below a closed layer (4) on the material surface; and separating the closed layer on the surface along the layer of hollow chambers from the rest of the material. Preferred Features: The semiconductor material is made from silicon, silicon-germanium, gallium arsenide, silicon carbide or indium phosphide, preferably doped with foreign materials. The semiconductor material is monocrystalline.

Description

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5. Description of the invention (1) The content of the present invention relates to a thin film or thin layer of a semiconductor material and a method for manufacturing the thin film or thin layer. The published silicon insulator (SOI) wafer has a thin layer structure. The ancient Hai thin layer structure usually includes: a carrier (such as a silicon wafer), a thin oxide layer and an oxide hidden under the surface. Silicon thin layer above the thin layer: for the manufacture of electronic components (such as memory and microprocessors), this thin layer structure is much better than commonly used silicon wafers: 9 °

Can achieve better electronic functional characteristics, coupled with high switching speed and low power consumption of component parts. Furthermore, components fabricated on a silicon insulator wafer base are more suitable for operating at lower voltages than conventional components. For these reasons, 'Shixi insulator wafers will be used significantly in future generations of components. The quality requirements for silicon insulator wafers are extremely high, especially regarding the uniformity of the thickness of the thin layer and the stricter defect density in the silicon thin layer and the oxide thin layer. In this regard, there are also differences in various manufacturing methods and products according to the existing technology: For example, in the case of the conventional oxygen ion implantation method (s I Μ0χ), the surface of the wafer is exposed to oxygen ions. Implanted into a two-layer 疋 / Zhu Du 'determined by the energy of oxygen ions can cause a thin layer of one or two oxygen contents (He Quan et al., Electronic Communication

14 (1 8) (1 978), p. 5 93). After the heat treatment, the thin silicon layer is turned into a silicon thin layer, and the silicon thin layer above it is separated from the silicon wafer below it; depression (Yu Guang: gas separation. T, the implantation of oxygen ions produces a junction in the silicon thin layer). ^ Interpretation that Benu ’s damage had a negative effect on Shi Xijui ’s limbs and Japanese yen during the subsequent manufacturing of electronic components. Y 'Normally, a' Shixi Insulator Wafer System uses a thin layer of Shixi from

575910 V. Description of the invention (2) The wafer (substrate wafer) is transferred to the second wafer (carrier wafer). -Usually 'both wafers are composed of silicon. For example, a thin layer of silicon is connected to a carrier wafer via an insulating silicon oxide layer. Many methods that can be used to transfer a thin layer of silicon from a first wafer to a second wafer to form a silicon insulator wafer have been disclosed: In the conventional SMARTCut method (US Pat. No. 5,374,564; Wei _ Dun et al., Journal of People's Vacuum Science and Technology, B 1 5 (4) (1 997), pp. 1 0 65 to 1 073), the separation layer is made by implanting hydrogen, after the two wafers are bonded The implementation of its separation effect is handled by means of heat. As a result, the surface is rough and has many defects, which must then be smoothed by polishing or heat treatment (annealing). In this method, irreparable defects (holes) are also formed in the thin layer above the silicon, which is commonly referred to as HF defects, with a density of 0 · 1 / cm2 to 0.5 / cm2. Furthermore, the implantation work, the separation layer used, the separation method, and the method form defects in the upper layer of silicon. After the scorch etching step (Secret etch 'etch defects), these defects became visible, and the number was 1 · 丨 〇 2 /-cm 2 to about 1 · 10 4 / cm 2 (Parker, “Silicon Performance of Inner Surface Defects in Insulator Wafers: Oxygen Ion Implantation for Bonding Silicon Insulator Wafers, JSPS, 3. International Conference on Advanced Technology of Shixi Materials, 2000, Gona, USA. Known in ELTRAN In the method (U.S. Patent No. 5,854, 1 23; Mihara et al., Journal of the Chemical Society 99-3 (1 99 9), pp. 111-116), the separation layer is prepared by means of anode anode engraving, and forms a Porous surface layer. Later, a thin layer of silicon epitaxial layer is formed and deposited on many porous surfaces. The separation is performed by heating or mechanical methods, in the surface and in the upper layer of silicon.

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trap. Moreover, # 论 如何 'epitaxially grows on a porous surface. Depending on the layer of Shi Xi,

Following the hole) is. The mouth density is 2 and the upper surface is etched with a defect density of 5 X 10V cm 2 to J A cm 2. The surface roughness after separation is very high, the root mean square value is 5 millimeters; the area of 22 is 1 micrometer X 1 micrometer; and subsequent smoothing is required (Sakaguchi et al., Π field state technology 43 (6) (2 0 0 0). 88 to 92).

^ Another method is the femto-separation method developed by the American Siegen Company (Carsan et al./European Semiconductors, 22 (2) (20 0 0) pp. 25-27) to obtain a low of 0.2 mm. Micron root-mean-square roughness value, this method requires another smoothing step after separation (Tierdeke Fest et al., Shixi Insulator Symposium, Institute of Electrical and Electronics Engineers, 2000, Wakefield , United States). Therefore, in order to make up for the above disadvantages, more complicated processing steps must be implemented. For example, according to European patent EP 9 0 5 7 6 7, the defect layer caused by separating the silicon wafer along the hydrogen bubble layer is etched by means of vapor phase. It can be removed from the silicon insulator wafer. If necessary, this method also allows the thickness of the silicon layer to be reduced. As described in the European patent Ep 1 0 4 5 4 4 8 'the surface will be thermally oxidized and subsequently reduced by reduction The same effect can be achieved by removing silicon oxide. To smooth the surface of the silicon thin layer and temper the crystal defects, it is also possible to apply Shi Xi insulator wafers in a hydrogen-containing environment

Heat treatment effect (EP 1 045448). Therefore, the object of the present invention is to provide (1) a thin film or thin layer of a semiconductor material that is substantially free of crystal defects and has a smooth surface, and (2) a method of manufacturing the thin film or thin layer. The inner valley of the present invention is a thin film or thin layer of semiconductor material,

Page 7 575910 V. Description of the invention (4) The density of HF defects in the layer is lower than 0.1 / cm 2 and the density of etch defects is lower than 10 / cm 2. Furthermore, another aspect of the present invention is a Shi Xi insulator wafer including a carrier wafer and a Shi Xi thin layer. After separation, the surface roughness of the silicon thin layer is less than 0.2 nm, and its HF defects The density is lower than 0.1 / cm 2 and the density of SEG's remaining defects is lower than 10 / cm 2. Another aspect of the present invention is a silicon insulator wafer including a carrier wafer and a silicon thin layer, wherein the thickness of the silicon thin layer is 20 nm or less and the chemical conversion rate is 5% or less. ·, Thin a) period b) shape c) add a good cast layer semi-transparent, the separation of the schedule is unnecessary in another method of the present invention, the conductor material table is reproduced, with surface structure, including periodic surface closure The edge of the layer in the present invention is, for example, the coarseness of the center of the product which degrades the performance of the product. The sub-injection process requires any solid semiconductor layer contained in the pore layer. The content is a method for manufacturing a thin film of semiconductor material or a predetermined thickness of the material on the surface. In particular, the manufacturing of dry structures produced by micro-injection and separation of these structures, the shape of these structures, depressions, and heat treatment until the thin layer of the surface of the material sealed holes, the layer from the rest of the semiconductor material 'can be avoided: will cause: For crystal high step or ultra-high temperature step and defects in the thin layer, there can be no defects caused by radiation of defective particles in the thin layer. The element (that is, hydrogen ion or oxygen ion) does not cause stress. Minor crystal damage is minimal. The half includes: the separation below the periclusium. The separation and processing of the degree of damage is novel, and it is a thin layer of the invention. Intention of method

575910 V. Description of the invention (6) Limited application to silicon. Advantages of the method of the invention Silicon is described as an example. ^ 3 specific embodiments are based on the substrate may also include a region of different material specifications, the region on the semiconductor layer products ^ near the surface of the conductor material film or thin layer is formed from the substrate table = big impact, the use of half a factor The substrate is formed as a layer having a flat surface. It is better to use single crystal wafers. · CZ or FZ wafers (m-shaped wafers are preferred. Especially, single crystals made by the method or floating zone method are used to make p. (Eg, #nitrogen wafers), wafers with any expected heat treatment and wafers without significant voids and gap U-second epitaxial layers, silicon or perfect silicon) or pure-isotope silicon (28si). Material of Λ body (The new development trend of Wukongci is ... In addition to the known "polishing" quality, it is also possible to use wafers without clear polishing, especially double-sided polishing "on the surface. Japanese yen, finely polished crystals In step a), using conventional photolithography, trench etching using ion beam etching σ =, hood and exposure technique or similar processing (, ultra-large scale integrated circuit technology, brush etching, etc. Hu, International Standard Book No. 0—9616? 2 ¥ Silicon Processing ”, a depression 2 (the first and second figures 6 ~) was prepared in the wall layer, and the thickness, diameter, depth, shape, and Interval. 2. These depressions (ditches) 2 are canals or other regular or irregular geometries ^ = to be precisely defined. Holes and trenches are better, especially circular or square holes are more likely = regular shapes The high-density depressions 2 are distributed on the surface * ° It is better to distribute on the entire surface of the substrate 1. Part of the surface, especially

For example, in the case of the crystal circle II 575910 V. Description of the Invention (7) '--- ^ In the example of the film, it is good that all of the depressions on one or both surfaces of the shell are concave, such as the name of the depression. Produced in a suitable manner, the osmium can be formed to include periodic reproduction of a structure having a desired geometry. The geometrical dimensions of these depressions (ie, mainly the cross section, depth, and spacing) are appropriately selected. A thin layer of semiconductor material (formed during the continuation of the method) can achieve the expected thickness D. For this reason, the diameter (if (Round holes) or side length (if it is a square hole), select D / 5 to 2 · D (especially D / 3 to D), and the depth of the ditch is selected!) To 4 · D and ditch interval Choose D / 2 to 3 · D. For example, the geometric dimensions of the depressions are appropriately selected. During the subsequent heat treatment in step b), the holes 3 formed by the depressions can be combined to form larger holes 3. (The holes shown in the first and second pictures represent individual holes and larger holes). In this case, it is preferable that the depressions to be manufactured are located precisely at a small number of locations and a large distance, after step d), the mesh 3a remains in the cavity 3. ’But’ if all holes with the same geometric shape are made according to a rule (such as a square or hexagon) with a constant distance from each hole, it is better to avoid some parts with larger distances. In this case, the geometric dimensions of the holes such as the & and the distance between the holes are most appropriately selected. ^ In the process of performing heat treatment according to step b), the surface is blocked by a smoothing layer, < ^ Individual cavities formed by individual depressions have not been fused together to form larger cavities. In the subsequent step b), the substrate is subjected to heat treatment. A ^^ > 5 ^ surface movement causes the depression 2 to be closed, so a seal is formed. The shavings ^ ^ Ma π Shi, 曰, and Yue simultaneously create holes 3 under this layer. While processing continues, do n’t a > the seal above the cavities

Page 11 575910 V. Description of the invention (8) ^ ------- Closed layer 4: To form a semiconductor thin layer or film. Shima's Literature: A Review of Electrochemical Techniques in Wangdao, Sato, and Water Step w is best added to Journal 17 (2 000), pp. 532-545. A continuous hole is formed at each place, and the remaining part of the substrate 1 is fixed by a deliberately constructed mesh at the interval of the closed layer above the cave 3 which is caused by the inner path of $ ::: 卢 俾 in step a). ^ ^ ^ ^ ^ ^ ^ Together. Iso- = formed in the place where a large distance is maintained between the depressions in the heart of the step. Nat = ‘People ^ of the thin layer 4 of the heat treatment of the heat treatment of the thin layer 4 without proper distance between the depressions caused by the person (the acoustic surface 彳 f t Γ + 'step b). Chu Er, but the individual holes formed by the individual depressions 3 are not reflected by the microscope; Figure Ξ: Ϊ: f corresponds to the scanning surface of the cross section of the treated surface 2) 1 ^ Q -¾ a Μ ~ Yes: the closed thin layer 4 above the thin layer of the individual cavity 3 formed by the individual depression. Depending on the special material, the heat treatment is performed at a temperature of 200 to 150 001 = to: ^ 3: and bell to 6 hours, used to control the processing time and duration according to Γ, since ΛΛ formula. Λ can be implemented in any environment where oxide // I layer is formed on the surface of the semiconductor (especially reducing gas or gas mixture or, better: gas and gas mixture). An environment containing hydrogen or argon or a lice mixture is preferred. The heat treatment can be carried out at atmospheric or decompressed October conditions. The processing conditions are properly selected. It is expected that the highest possible surface activity. If the bovine conductor material uses Shixi as the substrate, step b) is set according to the following number · Temperature 7.0 to 1371TC, but preferably 90 to 1251TC, especially 95 to 1150 ° C, pressure To 100 Torr, but preferably from j to 50 Torr,

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5 to 20 minutes is the best, which lasts from 3 seconds to 6 hours, and more preferably 1 minute to 3-0 minutes. The non-oxidizing environment in which the heat treatment is performed preferably contains hydrogen or argon or a mixture of the two gases. In step b), the processing conditions are preferably selected appropriately. The crystalline cavities (COP) and hollow cohesive aggregates in the substrate and especially in the film or layer 4 above the cavity 3 are annealed simultaneously. If the semiconductor material is silicon, as described in European Patent EP 82 9 5 5 9 A1 or US Patent 5, 93 5, 320, the required temperature exceeds 100 000. (:…… In addition, in this step, ..., by the slight impact of low-energy ions, the surface mobility of the semi-bulk atoms can be increased, thus causing these depressions to close more quickly or allow lower temperatures and shorter times In addition to this, it is also possible, if the temperature of the micro-surface gram is different, the heat treatment with a suitable thickness of chemistry, chemical or chemical thickness may be within the range that can shorten the extension layer of the substrate. The homogeneous industry uses Zimuk, PV2000, which saves the assembly's subsequent processing of the thin conductor, and deposits an epitaxial layer on the closed surface as part of the heat treatment. After heat treatment, it needs to be not smooth enough and may be useful for joining If the selected deposition temperature is a thickness < 0.5 micron epitaxial layer is disclosed (Belda, Mertons, Acta Sinica 39 (2 0 0 0) L841; Sior Kruger, Aimon, Lamba -17 (2000) 3). In order to repeat and control, the size of the layer produced by this combination can be reduced. It can be divided into heat treatment. For example, if the adverse effects of joints are to be implemented later, Shen in Apertures formed in the light effective to compensate, black Burns, Ximu Koh Mook, Breeds, Japanese, Gela Fu, electric and allows the use of the below exceed the target

57591Q__ 5. Description of the invention GO) Due to its thin thickness, the stability of the machine is weak. As shown in the second figure, the thin layer or the thin film 4, the surface of the substrate is best (= the place: at the other step, the Λ plane of the iT plane is connected (bonded). The carrier material 俜 -4 layer) The material from the same group as the carrier, the carrier material of this family is preferably selected from gallium, quartz, plastic, glass or ceramics; Shi Xi η Shi Xi 'fault, sanding If the carrier material is Shi Xi, the surface is the most: Wei = Suitable carrier material. Substrate surface and carrier connected together = electrical insulation layer. Even if it is even ;: the body r carrier material, which is a crystal-circular geometry, and the size of the element is doped with an "absorptive body, which is connected to the active area. The semiconducting ^ μ, hybrid doped and separated from the element are disclosed in the disclosed method (Dong Yige = The connection system uses the existing technology quasi-book number 0 ~ 471 ^ 748 Bu 3). + Conductor wafer processing ", compared with the international standard method, the material is eight / special layer. Because of these holes, it is not With the addition of square 1, the knife separation is very gentle. This separation work is best used to reduce the pressure. In this case, the holes are merged. Therefore, the separation machine is rounded and stabilized S 7. In order to ensure this operation, The small crystal holes in the substrate must be inserted in a right way. In the individual processing formed by trenches, these: and. The heating is performed after or during the bonding process. 4 The individual small holes are preferably fused together. Formation of large pores. 575910 V. Description of the invention (11) Two bases and two stone eves: In order to achieve the second heating step of separation, heat treatment is performed at _ to 137G ° C (especially _ to 12㈣). ^ Is in seconds to 4 Hours (especially! Eight shovel 5,) / ware degrees, and lasted 3 hours to borrow you 20 minutes is better). For example, I use a vertical furnace or a RTA device (rapid heating and annealing furnace 1). The heat treatment is carried out at atmospheric pressure or reduced pressure. Better environment, especially containing

= The environment of the mixture is better. In order to make the thin layer more uniform, U can extend the heat treatment time.卞 月 机械 U 有 ί: Known, the method can be used to separate along the fusion hole. In person \ 1, it should be mentioned that: separation by fluid jet (Sakaguchi et al. Stupidity! Tragedy deduction f (6) (20 0 0), pages 88 to 92), using shear force (card = , S shallow contact or ultra-thin silicon insulator? ,, solid-state technology, 2000 9 Separating method (using ultrasonic or megasonic). It is also possible to use suitable liquids (such as hydrofluoric acid or nitric acid and fluorinated acid). (Mixture) First, remove the nets left between the holes to achieve chemical dissociation. Combinations of various methods are also possible. Step C) combining semiconductor # 22 with an epitaxial layer in an epitaxial reactor is even more complicated. As appropriate, it is therefore possible to form a thin layer or film of the desired thickness. The method of 'Er Yu' is particularly to make a silicon insulator structure. Twenty-seven cases spoke. In other words, it is possible to use Shixi wafers (rounded) made of single crystals drawn from hangma as substrates. According to the existing technology, these Shixi wafers can cause crystalline depressions that appear in silicon circles to appear in thin layers of silicon made of silicon insulators, which can cause problems during component fabrication. Therefore, according to the prior art, if the substrate wafer used is a silicon wafer, the silicon wafer

V. Description of the invention (12) Disaster drawing and utilization of floating zone. If you fail to comply with this requirement, single crystals (FZ wafers) will be included. The particles of the crystalline cause must be mixed with silicon insulators, and it is better to implement them in a thin silicon environment. On the contrary, annealing is performed in heat treatment, especially in the use of CZ wafers with no problem in hydrogen, cavities, and in accordance with the method of the present invention, it is also possible that the surface is heated in step b). Feng is especially suitable. H can be annealed at the same time because of this depression. The reason for this is that Lebecco's brother has another advantage of the method of the present invention: the use of steps: the depression, the appropriate configuration, and the shape, and may even be made with ί: A silicon insulator crystal with a micron or thinner ultra-thin layer of silicon. The principle is also as follows :: The person who keeps the depth / width ratio of individual depressions, the smaller the cross section of the depressions and the distance between them, the thinner the silicon wafer will be and the more the geometry parameters will be changed. The geometric parameters of the depression and the silicon to be produced: P method, electron beam stone carving, X-ray stone carving or ultimate ultraviolet stone carving, to achieve the periodic structure required by the thickness range below 50 nm. Furthermore, the step (a further update method is being researched and developed), that is, within the range of you = $ m and below, the periodic structure may be implemented in a high and high manner, so the thickness variation of such thin layers can be reduced to A few lines below :: Now the above method can achieve geometric shape tolerances, but it is better at $ 5%, especially 1%. . The tighter the tolerance of 3, the better the uniformity of the thickness of the obtained thin layer. Generally, tolerances are lower than those of individual geometric structures. This will allow ‘layer uniformity to reach 5% or less. Official 4

Page 16 575910 V. Description of the invention (13) The silicon thin layer is substantially defect-free and eliminates other complicated processing steps, because the cost is greatly reduced. After the silicon insulator wafer is manufactured, the thickness of the silicon thin layer 4 is increased or decreased), and an epitaxial silicon layer may be deposited. Known for the polishing process', but it is better to use 蒗, and then the force is retained by the reduction of the silicon oxide layer, so that a full layer thickness of 20 nm or less can be obtained. After that, if necessary, it may also require a polishing step or further thermal reduction or inert environment, the ^^ mixture 'under atmospheric pressure or reduced pressure, which lasts from 10 seconds to 60 minutes, in batch firearms, RTA). The batch furnace system has a vertical furnace volume of 50 to 2 50 silicon wafers. The operation mode of the E box is as follows: The special excellent performance of the method of the present invention is as follows: If an FZ wafer is used as the substrate crystalline silicon insulator wafer, the wafer is not only free of fine defects on the surface, but also oxygen deposits. However, if the substrate wafer used is a high-quality, high-quality surface that may reduce or completely result in the manufacture of silicon insulator wafers, it may be adjusted if necessary (also. For example, to increase the thickness of the thin layer and reduce the thickness of the thin layer) It may be removed using customary-phase etching or surface oxidation. Thin layer thickness uniformity Thickness uniformity with a thickness uniformity of 5% or less reduces the thickness of the thin surface. This work can be handled. The work is carried out in a Preferably contains hydrogen or argon or hydrogen and argon in a temperature range of 1000 to 1250 ° C, in a furnace or lamp furnace (quick-force heat retreat or horizontal furnace, each time the wafer boat is an annealing lamp furnace) The box is always a wafer. The embodiment can achieve a silicon insulator wafer, which can produce a cavity with a thin layer of silicon and no fine defects on the surface. The cavity is a cohesive body of the crystal gap. Nitrogen CZ wafer, which may be And 575910 V. Description of the invention (14) The resistance achieved by the formation of dislocations is greater than that of traditional cz wafers. High nitrogen doping content of 1 x 1014 to 5 x 10] 5 / cubic centimeter cz wafers. Helmets T Compared with the nitrogen wafer, the heating-induced slip and position of the highly nitrogen-doped wafer is greatly increased and the density of fine defects on the surface is higher (Journal of Graf Chemical Society PV2 0 0 0-1 7, 319 to 33 33; Amman 2 Journal of the Chemical Society 9 4-10 p. 136; Sueoka et al., Electrochemical Package PV2 0 0 0-17 (pp. 164 to 179). Another possible use of the Journal of Yokai is the use of single crystals. Not made of silicon: polycrystalline silicon, glass, and ceramics. Ν Ah jiao, for example, this method can also be used particularly advantageously for thin film structures. To achieve this, the method is at least land:; Therefore, in the figure of the figure: brother-layer system, re-experimental example: coat one or more layers on the first layer. 5 steps of the native method, a periodical (ditch and wafer 1 smooth) The surface is flat. The trenches have a square cross-section of about 0.5 micrometers, and the distance between the trenches is about U micrometers. The trenches such as Mii are arranged in a regular, square pattern. The trenches are based on the existing technology by ion beams, and the proper method is adopted, and the depth is 3 microns. The sexual surface is closed in step b) by means of thorium treatment. The heat treatment lasts 10 minutes. It is in a pure hydrogen environment, under pressure, hydrogen flow rate of 10 cubic centimeters per minute and temperature ^ 2. Implementation. In this method, the cavity 3 formed by the ditch 2 is Wei Yanping.

Page 18 575910 V. Description of the invention (15) Relax in the direction of the wafer sealing surface 4 by about 0.25 micron. The third picture shows a scanning electron microscope image of (1) the cavity 3 and (2) a closed, perfect and smooth layer 4 above it. Due to its smoothness, according to the second figure, the closed surface is particularly suitable for attaching a carrier wafer (bonding). Then, in another step be), the silicon wafer produced in step b) is connected to a carrier wafer 5 by means of its surface 4b. The carrier wafer 5 is also composed of silicon and is attached with a silicon wafer. Thin layer of silicon oxide 6, commercially available cement used by EVG, Schadinger, Austria. In step c), the silicon wafer connected through the silicon oxide layer 6 is heat-treated. To perform this heat treatment, the same conditions were selected as those used for the closed surface in step b). This heat treatment causes the holes 3 shown in the third figure to fuse together, thus forming a continuous hole 7 (fourth picture), and the silicon layer 4 still covering the hole 3 in the third picture is separated. The newly formed surface la of the substrate silicon wafer 1 shown in the fourth figure has a continuous hole 7 above the surface. The hole 7 completely separates the silicon thin layer 4 made of the silicon wafer 1. Now the silicon thin layer 4 is only connected to the oxide layer 6 of the carrier Shixi wafer 5 (5 and 6 as shown). The thickness of the thin layer 4 is about 1 micron, and it stands loosely on the rest of the substrate 1. Unlike the surface la of the rest of the substrate, the surface 4a of the thin layer 4 of the stone, which has been separated, is already very smooth. The focus of the fourth figure is on the surface 4a, which is used for the production of electronic components.

Page 19 575910 V. Description of the invention (16) Description of component numbers: 1 Substrate (semiconductor material) 1 a Substrate surface 2 Depression (ditch) 3 Holes 3 a Mesh 4 Sealing layer (silicon layer) 4a Silicon thin layer Layer surface 4 b Broken wafer surface ·, 5 Carrier material (carrier silicon wafer) 6 Electrical insulation layer (oxide layer) 7 Continuous hole

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Claims (1)

575910 w .: Q v. Patent application scope A method for manufacturing a thin layer i of a semiconductor material film, including a) the surface of the semiconductor material is reproduced periodically with a predetermined geometry; The state =, 'These structures include · Zhouli, until the surface of the material is below the sealing layer ... Sealing layer 2 = =: = = 2. Such as the separation of the remaining part of the scope of the patent application. A group comprising:, / /, the medium semiconductor material is selected from indium indium. Broken germanium, gallium carbide, carbonized carbide, and ^ If the scope of the patent application is the second Gan Shi L t If the scope of the patent application is the third party: China / conductor material is Shi Xi. Early crystals. The pilot method, in which the semiconductor material is a trench. The method of No.1 Confinement of the Moon, 'where the depressions are holes or the substance is the same as the method of item 5 of the above-mentioned March or Fan Zhengwei's method', where the depressions are cross-sections, Often not; = Law :: The geometric shape of the hole is the same. The choice of size is based on the method of making: 2 methods, in which the geometry of the depression is 8. According to the scope of the patent application; or / the expected thickness of the layer changes. The dimensions and the distance between the depressions are 3 J. The method, in the geometry of the depressions, 'the formation of the depression in the depressions' is selected. Step b) The individual holes are insoluble in the soil during the heat treatment: 4 can be formed above the hole layer-a closed surface , Forming a larger hole together. A page 21 575910 6. Scope of applying for patent 9. If the method of applying for item 1 of the scope of patent application, the belt in 1 is tied to a semiconductor material which can prevent semiconductors. Σ = heat treatment. Middle Besch. And / or argon. The heat in step b) is contained in each environment, and the heat in step b) lasts from 3 seconds to 6 hours. If the method of patent application scope 1 or 2 is processed at atmospheric pressure or Implementation under reduced pressure12. If the method of patent application scope item 1 or 2 is processed, it is carried out at a temperature of 200 to 15 0 t.13.If the patent scope of application scope is 1 or 2 In the selection, the Quine depression system was annealed simultaneously. The method of item 1, in which the internal thermal place of step b) appears in the semiconductor material. 14. The method of item 1 or 2 in the scope of patent application, the treatment is combined with low-energy ion impact on the surface. VIII v 〃 之 ， 15. 15. If the method of the scope of application for patents}, the steps a) and b) are made-the surface of the thin layer of the cavity, before the rest of the body 2 has been separated in accordance with 2 —Surface phase of the carrier material 16 · If at least one carrier material has been applied one or two more times in the manner of applying for a patent application. The method of item 15 is carried out twice, so that it is used as the carrier material by itself. This method is based on the first layer of a semiconductor material layer, which is suitable for additional coating. For example, according to the method of claim 15 in the scope of patent application, it is recommended that the carrier material is i. Dai nationality includes: silicon, silicon-germanium, silicon carbide, gallium arsenide 575910 6. Scope of patent application, quartz, plastic, glass and ceramics. 18. The method according to item 17 of the scope of patent application, wherein the carrier material is Shi Xi 0 19. The method according to item 7 or 18 of the scope of patent application, wherein the surface of the carrier material has an electrically insulating layer. 2 0. If the method of the scope of patent application, the separation effect in the implementation step (:) is by means of mechanical, chemical or heat treatment or a combination of these methods. The heat treatment in step c) results in the fusion and separation of the holes made in step b). 2. 2 If the method according to item 21 of the scope of patent application, wherein the heat treatment in step c) is carried out at a temperature of 80 to 1 370 ° C and atmospheric pressure or reduced pressure, which lasts from 3 seconds to 4 hours. !! · For example, the method of claim 20 in the scope of patent application, wherein the mechanical treatment is selected from Liqun ’. This group includes: application of shear force, fluid spray treatment, and sonic treatment of wave or million sound waves. 1 4. If the method of claim 1 or 2 is made of two layers, after the semiconductor material is applied to the 1, the thickness of the layer is reduced by reducing the surface group including polishing after selecting from a group of measures , Gas phase or liquid etching, and surface oxidation and the method as described in item 1 of the scope of patents, wherein the semiconductor material layer 26.4 is applied by polishing or heat treatment Smooth. The method of item 25 of the 4: 7 patent, ... smoothness is carried out in an environment containing hydrogen and / or argon. Page 23 575910 6. Scope of Patent Application 27. For the method of applying for item 1 or 2 of the patent scope, the semiconductor material is in the form of a wafer. 28. The method of claim 15 or 16, wherein the carrier material is in the form of a wafer. 2 9. The method according to item 15 or 16 of the scope of patent application, wherein the surface of the interconnected substrate and the surface of the carrier material have the same geometric shape and size. Page 24