TW567565B - Chip-on-board module, and method of manufacturing the same - Google Patents

Abstract

A chip-on-board module has a multilayer interconnection board having die mount sections; dies mounted on respective die mount sections such that a single die is mounted on each die mount section or two or more dies are being stacked and mounted there; bonding pads provided on the multilayer and connected to single dies or uppermost dies; contact pads provided on the multilayer board and connected to corresponding bonding pads; jumper pads provided in proximity to the contact pads and connected to edge terminals of the multilayer board, circuit elements mounted on the multilayer interconnection board, or through holes formed so as to extend across layers of the multilayer board; and molding resin for molding the dies and the pads. The uppermost dies of the respective die mount sections where dies are stacked in two or more layers have passed an electric property test.

Description

567565 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to mounting a semiconductor chip (die) such as a memory chip, a microcomputer chip, an AS IC chip, and the like on a multilayer wiring board. On-board connected wafer of substrate and manufacturing method thereof. [Knowledgeable technology] An example of a memory module is used to indicate the knowledge. Figure 11 is a schematic diagram _____ ,,, a .............. ^ ^ ^ ^ (Hereinafter referred to as COB), (a) is a perspective view showing the overall structure, (b) shows two adjacent I c in the structure shown in (a), and is mounted on a multilayer wiring board structure. In these figures, the component number i is a multilayer wiring substrate, and 2 is 1 (: lead pads, used to connect and fix the leads of multiple ICs provided on the multilayer wiring substrate, thereby assembling the IC in a multilayer On the wiring substrate j, 3 is a wiring pattern electrically connected between the jc lead pads 2, and the surface of the substrate is fixed in a specified pattern. In addition to the interconnection of the IC, it is used to install the resistance on the multilayer wiring substrate. Connection of circuit elements (not shown in the figure) such as capacitors and fuses, or connection with through-holes (for connection between the various wiring substrates) formed across the multilayer wiring substrate, or outside the multilayer wiring substrate It becomes the connection of the edge terminal 4 of the connection terminal. 5 gC is further fixed on the multi-layer wiring substrate 1 by fixing the lead: ^ to the above 1 (: lead pad 2 Λ). Figure 12 is a flow chart 'for矣 + circle 1 1 (, a ^ ^. ^ Po * ^ shows the system k Y step of the memory module not shown in Figure 11 (a). That is, 'show the memory at step 81) is linked to the known Lead Pivot (not shown). Second, Y step 7 S2, for wafer and lead frame Performs line coupling. Then at step paste, so that the grain quenched

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The sheet and the lead frame become Xe # # 在 丨 & + Step S4, thereby forming 1C5 for each 3 entities. Then ’discard it at step S5; two = try! When the unqualified condition is in the case of Δ ^ D field, it is slaved to the multilayer wiring substrate i in step S6 as shown in FIG. 11. Then, an electrical characteristic test is performed as a memory module in step S7, and then the manufacturing step is ended. FIG. 13 and FIG. 18 (Summarization) are used to show the circuit structure and the arrangement method of 1C when the old assembly is performed on the wiring board 1 at step%.

FIGS. 13 and 14 show the case of assembling 9 ，, FIG. 15 and FIG. 16 show the case of assembling 1C, and FIG. 17 and FIG. 18 show the case of assembling 36 1 (:. f When assembling 9 ICs, each 1C As shown in Fig. 14, it is arranged and mounted on a multilayer wiring substrate. This figure shows an example where the multilayer wiring substrate is two layers, (a) represents the wiring substrate u which is the} th layer on the surface, and (b) represents The second layer wiring board lb on the back side. The 9 ICs are divided into 4 and 5 2 groups, and the 4 group (5 a 1 to 5 a 4) is arranged as shown in the figure. The wiring board 1a on the first layer is composed of 5 groups (5bl to 5b5) as shown in the wiring board 1b on the second layer, and the connection between the two substrates is not shown in the figure. Hole for connection. Wiring board of the first layer 丨 a

The component number 50 is I C ′ for connection to an external circuit via the edge terminal 4. The circuit structure is shown in Fig. 13 'It is constructed to supply the clock signals (add, CKE 0, / S0-3, etc.) and I / 〇 signals (DQO. · ·, Etc.) individually and in parallel to a group consisting of 4 Each IC of the group (5al to 5a4) and each IC of the group of 5 (5bl to 5b5). The situation shown in the figure is for example formed via IC5al

C: \ 2D-CODE \ 92-Ol \ 9in4366.ptd Page 6 567565 V. Description of the invention (3) Clock signal is supplied to IC5a2, but it can also be supplied to 1 (: 532 without IC5ai's the same as IC5a3). , Connected so as not to be supplied with 丨 and 1 (: 532. The same is true for other ICs. In addition, it is the same for 丨 / Q signals. In addition, in the case of assembling 18 ICs, each 丨 c is as shown in 丨As shown in Fig. 6, the multilayer wiring substrates a and 1 b are arranged and mounted. That is, the wiring substrates 1 a on the first layer and the wiring substrates 1 b on the second layer are respectively arranged. The connection IC50 and The through-hole (not shown) is the same as that in FIG. 14, so its description is omitted. The circuit structure is shown in FIG. 15. The supply method of each signal to each ic is the same as that in FIG. 13, but the only difference is The number of 1Cs in each group is 9, so the explanation is omitted. In addition, in the case of assembling 36 1 (:, 4 ICs of each IC are shown in Fig. 18). It is mounted on each base mb. That is, two wiring boards 1a and 2 f lb on the i-th layer are respectively arranged in two groups of 18 boards. ) Because it is the same as the situation in FIG. 14, its description is omitted. As shown in FIG. 17 "quoted the number of circuits connected in parallel / series / SO ΛΛίί, the clock signal (Add, CKE0 / = -3 夺) The supply method for each group is the same as @ i3. ⑽ f HDQ0 .... etc.) It is also supplied in parallel to 1C, the electrical aspect is the same as in Figure 13. In the figure group, and via The K5MmC5dl supply 1/0 signal is also used by the brother 'for example, it is formed by IC5bUfIC5dl supply. For: ― 疋 is also connected to connect without 1C is the same. IL5al and 5cl are the same, for other

567565 V. Description of the invention (4) [Problems to be solved by the invention] Since the self-knowledge memory module has the above-mentioned square frame, it will have an X structure with a high material cost, so it needs leads and a chip connection In y 5: In addition, in the manufacturing step, I c is assembled on the wiring substrate for the module, which is a step to form an IC, and the problem of increasing the manufacturing cost. In addition, 1 = 2 steps, so it may be disqualified, because the result of the electrical characteristics test is becoming a problem, and the mold resin and lead frame are rejected. 1c

In addition, when assembling I c to the wiring, the number of circuit boards and the number of layers is two. Because 1C is assembled, it is necessary to prepare a variety of multi-layer wiring substrates, which is different. The present invention is used to cope with the above problems. Straight-made, not two Putian W began to expand the power of its purpose is to provide the structure of the COB 3¾ > 1 ^ α ^ ^ ^ It is said / / 1 k α 1 e) 罝 mounters on the multilayer wiring substrate. The purpose of the invention is to provide the following: When assembling a wafer to multiple layers =; r Even if the number of wafers varies, the same multilayer wiring substrate can be used, so the number of types of multilayer wiring substrates can be reduced. »In addition, the object of the present invention is to provide a manufacturing method of COB, which performs an electrical characteristic test before molding. When it becomes a good condition for a failed wafer, it is only necessary to remove the connection between the failed wafer and the multilayer wiring substrate. The 'line' does not require dismantling the defective wafers for the manufacturing steps. [Means for Solving the Problem] The COB of the present invention is provided with a multi-layer wiring substrate having a plurality of wafer cracks; a plurality of wafers are worn in a single or two or more overlapping manners ~

567565 V. Description of the invention (5) On each of the above-mentioned multi-layer wiring boards, the formation and pads, and the above-mentioned wire substrates, are formed close to the above-mentioned edge terminals or each of the wafers and wafers across the above-mentioned layers are electrically connected. In addition, in addition to the uppermost part of the hair, the wafer of the hair mounting part of the hair is not received through the jumper wiring. In addition, the hair of the wiring board is fixed on the other side of each of the main surfaces of the breakout substrate. Corresponding to the wafer, it is provided on each wafer mounting portion of the above substrate; a plurality of connection pads and the toilet mounting portion are correspondingly provided on the above-mentioned multilayer arrangement ^: the wafer of the body or the uppermost wafer connection; contact Each connection pad of the lining is correspondingly arranged in the above mentioned multiples to be connected with the corresponding connection pad; skip pads, two # contact pads, which are used to connect the above-mentioned multiple layers, and are assembled in the above-mentioned multiple layers Circuit element ΐ of wiring board or each layer of wiring board; and molding resin to mold each of the above-mentioned pads; overlapping two or more crystals that passed the uppermost test sheet. COB of Ming is a wafer in which two or more of the above-mentioned wafers are overlapped, and the wafer is a wafer that failed the electrical characteristics test. Sun ^ is a day-to-day film that is mounted on the above-mentioned multi-layer wiring substrate. The area is divided into multiple groups. = Wiring receives signals. The other groups of crystal JVs have multi-layer wiring substrates. The main surface side wiring board of Ga Xian ΐ A f and the other 1 ☆ Don't have multiple wafer mounting parts; don't install the device on the U • side and the other side side Z u 2 σ A plurality of connection pads are respectively arranged on the wiring board t side wiring substrate to be connected to the wafers of each of the above t: 彳 mesh I; a plurality of contact pads are respectively on the main side and the other side. The wiring board becomes the same as above «

C: \ 2D-CODE \ 92-01 \ 91124366.ptd f page 9 567565 V. Each of the description of the invention (6), the junction pad corresponds to form a connection with the corresponding connection pad; the through-hole is set by π to span The above-mentioned main surface side and the other side of the wiring board and the skip pad are respectively disposed on the above main surface side and the other side: the line Ϊ Ϊ Ϊ is close to the above-mentioned contact pad, and $ is used to connect the above. Pass through its two crickets, and are arranged on the main side and the other side of the above wiring: for 2ti side, used to connect the above-mentioned through-holes; and molded tree slices Each crystal moon and each liner of the wiring substrate on the other side are molded. ί:: ί t Mingzhi is to make the above chip ▲ a memory chip. A piece of wear: The manufacturing method of the method includes the steps of: connecting each wafer and each pair on a substrate of a multilayer wiring substrate having a plurality of wafer facing portions; and connecting a multilayer wiring substrate. And the corresponding contacts; each of the above-mentioned contact pads is used to test the wafer connected to the above-mentioned test to become unqualified :: = 'cut off and overlap the test wafer on the unqualified wafer again ^ Each wafer and each pad are molded. σ Βθ, σ for the manufacturer of the above-mentioned film η: The steps are included. Each of the chip loaders has a plurality of wafers, which has a wafer mounting section, and Wash each of the above-mentioned I-layer wiring boards :: The contact pads corresponding to the respective connection pads are connected to the wafer substrates, and the wafers are connected to each other: the above-mentioned night layer is arranged on the corresponding connection pads, and connected

567565 V. Description of the invention (7) ΐίΐΐΐΐ and the contact pads corresponding to these; * Skip the pad to set the next day ^ corresponding to the wafer _ 塾 and close to the 晶 should contact the lining for the specified crystal connection, Use specified wafers connected to each of the contact pads and adjacent wafers to connect; make test characteristics; contact pads are used to test the connection of the electrical junction pads of each wafer and: "if 不 ί 的 板" And the corresponding wafers. The wafers on the opposite side and the f-mouth plate are reloaded with the test pass "yi" # each of the above wafers and each pad are fabricated [implementation mode of the invention]施 形 形 熊 1 The following will be used to explain Embodiment 1 of the present invention based on the drawings. Figure 1 is a schematic diagram, an example of a memory module is used for epicenter = structure '(a) is a perspective view, To represent the structure of the memory 2 '' heart lining, etc., (c) is the side "touch the 塾, skip ^^^^ k; 1 Λ / (b) ^ ^ ". ,, / 主 在 eHAI In the figure, element number 1 is a multilayer wiring board. A plurality of wafers are mounted on the surface, and are fixed to each of the above. The nine memories of the wafer mounting section (• e) 'are not directly connected to the lead frame as in the conventional way: they are directly fixed to the f multilayer wiring board. In addition, the wafer] 〇 As shown in the figure] ′ The single-layer vibration is applied to the multilayer wiring board i. As shown by the right hand side, it can be mounted so that two wafers 丨 〇χ and 丨 γ overlap, and 4 wafers can also be made more than two. The detailed part will be followed

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5. Description of the invention (8) Description. The element number 1 0A is a pad provided on each wafer, and π is a connection wiring board i corresponding to each wafer mounting portion and is provided on the multilayer wiring substrate 1. A 12 ′ wire is used to connect the wafer 1 0 (to When two or more overlapping forms are mounted, the pad 10A on the upper wafer 10) and the connection pad u, and the element number 13 疋 are contact pads, which are provided on the multilayer wiring board i corresponding to the connection pads. The upper '1 4 is a wiring pattern used to connect the connection pad 丨 丨 and the contact pad 塾 1 3' 1 5 is a skip pad, which is set to be close to the contact pad 丨 3, 6 is a wiring pattern. To make the skip pattern 丨 5 connected to each other, a finger = _ pattern is used to connect to the second and fourth connection terminals outside the multilayer wiring substrate, or to a capacitor assembled on the multilayer wiring substrate 1, The connection of circuit elements (not shown in the figure) such as resistors, dazzling wires, and the like constitutes a plurality of wiring substrates that constitute a multilayer wiring substrate for connection between the wiring substrates). Fig. 2 is a flowchart showing the memory module generation shown in Fig. 1. ~ Clothing: ^ Step In step S11, nine wafers 10 are connected to the multilayer wiring board i. _ Next, the wafer pads 丨 0A and the connection pads 丨 丨 ^ are knotted in step S12. Then, in step S13, the tester (not shown in the figure) is connected to the substrate ^ • Pad 1 3, Xiao to implement the wafer! 〇 Electrical characteristics test. By using this test, for example, when the wafer of FIG. 1 (c) is unqualified, step m4 is used to remove the connection between m and the connection pad u ′ (not shown), which is used to transfer the wafer J 0x cuts off the circuit. However, the wafer 10X has not been removed, but remains in multiple layers as shown in the figure.

567565

On the wiring board 1. The person, in step s 15, prepares another implementation only for wafers 丨 0 = wafers that have passed the electrical test / battery test. The wafers that pass in step 31.6 are weighted as unqualified. Wafer 10X. After the defect, in step S1 ?, the pad of the qualified wafer 'wafer 10Υ of the uppermost wafer of the overlapping wafer and the f-pad 11 are connected by wire, and the qualified wafer 11 is connected instead of the unsuitable wafer: wafer 10X, This constitutes the circuit. Next, in step S18, the wire 12 is used to wire-connect the contact pad 13 and the skip pad 15. Then, in step S19, using the molding resin 18, the respective wafers 1 0, 1 ox, 1 y and the bonding pads 11, the contact pads 13, the skip pads 15, the wires 12 and The wiring patterns 14, 16 are molded.

Then, an electrical characteristic test is performed as a memory module in step S20, and then the manufacturing steps are ended. The t-shaped bear L will be used to explain the second embodiment of the present invention based on the drawings. 3 to 9 are schematic diagrams showing an example of the structure of the second embodiment with an example of a memory module. The figure shows the case where the wafer is mounted on the multilayer wiring board 1 in the above-mentioned step s1. Circuit structure and method of arranging the wafer i 0 'Fig. 3 and Fig. 4 show a case where 36 wafers are mounted, Fig. 6 and Fig. 7 show a case where Λ 8 wafers are mounted, and Fig. 8 and 圊 9 show 9 wafers are mounted Situation. First, when 36 wafers 10 are mounted, each wafer is arranged and mounted on a multilayer wiring board 1 as shown in FIG. 4. This figure shows an example in which the multilayer wiring substrate 1 has two layers. (A) shows the first layer wiring substrate 1a '(b) shows the second layer wiring substrate 1b on the back surface. 3 of 6 chips

567565

10 groups are formed every 4 or 5 groups and divided into a total of 8 groups & group ~ h group). Group a (i0ai ~ 10a5), group b (i0bl ~ l10b4), and group c (i0cl ~ 1〇c4) * d group ( l〇dl ~ 10d5) of the four groups of wafers, the e-group (l〇ei ~ i〇e5), f group (1〇fl ~ 1〇f4) are arranged on the second layer of the wiring substrate. , G group ~ 10 g 4) and h group (10 h 1 ~ 10 h 5) of the four groups of wafers. FIG. 5 is a schematic diagram showing the cross-sectional structure of the first-layer wiring substrate 1 a and the second-layer wiring substrate 1 b of the portion surrounded by 0 in FIG. 4 (a), and a schematic representation and The connection between the through-holes 7 connecting the two wiring substrates is closed. In the figure, the same component numbers are added to the parts corresponding to those in FIG. 1 (c), and the description of each of them is omitted. In addition, the setting position of the through holes 17 in the figure is only an example, and is not limited to this position. The circuit structure is shown in Figure 3. It is constructed to supply the clock signals (Add, CKE0, / S0-3, etc.) and I / 0 numbers (DQ 0. · ·, etc.) to the chips of each group in parallel. . In the case shown in the figure, for example, it is in the form of supplying a clock signal to the wafer 10a 3 via the wafers 10a1 and 0a2, but it may also be connected to these without passing through the wafers 10a1 and 10a2. Wafers are supplied in parallel. For other wafers • Same. The same applies to I / O signals. In addition, the clock signal is directly connected to the wafers of group a (10al to 10a5) and the wafers of group b (10bl to 10b4) without being connected via the jumper wiring 2; It is supplied to each wafer of group c to group h.

V. Description of the invention (11) In addition, for the I / 0 signal, connect each chip of the one group to the d group for supply, and directly pass through the wiring 20 to each of the crystals of the a group to the e group to the h group. , Chip; ^ But it is the type 20 through the jumper wiring, so that the multilayer chip is mounted on the multi-layer wiring substrate: ^ That is, as described below, the number of chips in a group of parts = the number of chips is reduced, and only connected Road, 1 distant; & Make-up AA > / ,, the electric ridge without the part of the chip is installed, the connection is sad and becomes a twist and the A twist # use the jumper wiring part will not be installed with a ; ,,, the reason for the action of block B, so Lidou times, especially in the I · I have the circuit part of the film. Bingjiu, the installer has 18 chips and 2 0 ^ ^ is identical to the case with 36. Evening horses are in the same condition, as shown in Figure 7, using the turtle line beauty board 丨 push — 7 — Xi Yue wiring board , Only in the first floor of the 潫 soil plate 1 a into the configuration shown in the figure, ^ ^ ^ ^ ^ ^ ^ ^ No configuration. In the second layer of the wiring substrate 1 b, a yoke of the first layer of wiring is f a ^ ^ η ^ ^.

Set 1 q in group a to group d to lose y H so +, Λ σ, daily film. The circuit structure in this case is shown in Figure 6. Only the right button φ ^ θ θ, ^ / is connected to the chipset of group 3 to group d with slashes, and the connection lines of group e to group h are formed. A τ t # μ μ #% a / policy is completely separated from the jumper wiring 20 on the clock signal side and the 1/0 signal side of Rong 4. In addition, when there are 9 crystals, 1 night holding, mouth η strong and strong Q iWm > on the day of the sun and moon 1 U, as shown in Figure 9, the use is the same as the case of 36 Evening s Ψ ± ^ 7 evening θ wiring substrate, the chip shown in the figure is only μ 2 in the wiring substrate 1 a, the wiring substrate is not arranged on the second layer, the circuit structure of April f is shown in Figure 8 It is shown that the jumper 2 0 is not passed. The 9 wafers (group 8 and group b) of the two sources (group 8 and group 5) of tiger source (shown by diagonal lines in Fig. 8) are arranged as shown in Fig. 9 (a), and the dotted lines become empty. In addition, as shown in FIG. 8, all the jumper wires 20 are cut off, and all the connection wires other than the chips in the & group and b group are cut off.

567565 V. Description of the invention (12) The above embodiments are described by taking a memory module as an example, but the invention is not limited to the memory module. For microcomputer chips or M ^ ci, it is also the same. Can be implemented. FIG. 10 is a schematic view showing a composite crystal of the multi-mode wiring substrate 1 including the morphological wafer 10, the ASIC wafer 30, and the microcomputer wafer 40. The manufacturing method is omitted because it is related to the above-mentioned memory module. [Effects of the invention] A plurality of connection profiles are installed in a manner that a plurality of wafers are split and overlapped, and the COB of the present invention is provided with a multi-layer wiring board. A plurality of wafers are individually or two individually. "Multi-layer wiring board each wafer mounting part; a plurality of connection pads, spots corresponding to each wafer bumping part is said to be avoided on the above-mentioned J: forming a connection with a single wafer or the uppermost wafer; Contact 2 base edge a. The above-mentioned respective connection pads are provided in the above-mentioned multilayer distribution = terminals: or assembled in the above-mentioned multilayer wiring substrate board $ 5 = each layer of the above-mentioned wiring substrate; and each of the models described Moulding of the wafer and each liner: Please use the pair of Shangxin's wafers that are qualified for electrical characteristics test; therefore, do not use lead wires to add a 'memory module' to the frame. In addition, Before making:: Volume '! · 生-式 测' so even if it fails, it is wasteful. In addition, for the wafers that failed the electrical characteristics test, only == ^ may: make the unqualified wafers remain directly in the multi-layer assembly ..., = overlapped with the electrical characteristics test for other wafers that pass: 16th Page C: \ 2D-CODE \ 92-01 \ 91124366.ptd 567565 V. Description of the invention (13) Sheets are resin-molded, so the number of manufacturing steps can be reduced for its effect. In order to reduce the COB of the present invention, the wafers mounted on the above-mentioned multi-layered wafer mounting portion are divided into a plurality of groups, and the designated group ^ means that signals are not received through the jumper wiring, and the crystals of other groups The chip line of j receives signals, which can reduce the reliability of the erroneous operation. 1 In order to improve the COB of the present invention, the multi-layer wiring substrate, the multi-wiring substrate, the main-surface-side wiring substrate and the structure that constitute the main surface Another: Gulu's other side of the wiring board, each with a plurality of crystals and a number of wafers, respectively mounted on the above main surface side and in addition-^ σ, each wafer mounting portion of the multi-substrate; a plurality of bonding pads The pads are placed on the wiring board on the main surface side and the other surface side of the two wires, respectively: the upper part is connected to the corresponding chip; multiple connection pads 塾 = the wiring that is recognized on the main side and the other side

Corresponding to each of the connecting linings, corresponding to == J hole, is set to cross the above main surface side and the other, then, to pass through the plate; jumping linings are respectively set on the above main surface side And another f-line basis

The f wire f board becomes a contact pad close to the above, and is used with: J edge terminal, which is provided on one or both of the above main surface side and the other through-through substrate, and is used to connect the above-mentioned through-hole wiring. Come to mold the above-mentioned main surface side and the other surface side with the beauty, tree, and each liner; therefore, the multilayer substrate can be converted, which can improve production efficiency and reduce price. * ,, ^ page 17 C: \ 2D-OODE \ 92-Ol \ 9ll24366.ptd 567565

V. Description of the invention (14) [Explanation of component number] 1 Multi-layer wiring board 4 Edge terminal 10 Wafer 10A Wafer pad 10X Failed wafer 10Y Passed wafer 11 Connection pad 12 Wire contact profile 14, 16 Wiring pattern 15 Jumper pad 17 Through-hole 18 Resin molded body 20 Jumper wiring 30 ASIC chip 40 Microcomputer chip 50 Connection IC •

C: \ 2D-CODE \ 92-Ol \ 91124366.ptd Page 18 567565 Brief Description of Drawings Figure 1 is a schematic diagram, and an example of a memory module is used to show the structure of Embodiment 1 of the present invention, (a) It is an oblique view showing the overall structure, and (b) is a schematic plan view showing the structure of (c) two adjacent wafers and the structure of various pads interposed therebetween. FIG. 2 is a flowchart showing manufacturing steps of the memory module shown in FIG. 1. FIG. Fig. 3 is a schematic line diagram showing the circuit structure of the second embodiment of the present invention. The figure shows an example when 36 wafers are mounted. »Figures 4 (a) and (b) are schematic diagrams showing the arrangement structure of the wafer on the multilayer substrate in the case of FIG. Fig. 5 is a schematic diagram showing a cross-sectional structure of a first-layer wiring substrate and a second-layer wiring substrate constituting a multilayer wiring substrate. Fig. 6 is a schematic diagram showing the circuit structure of the second embodiment, and shows an example when 18 wafers are mounted. 7 (a) and 7 (b) are schematic diagrams showing the arrangement structure of the wafers on the multilayer wiring substrate in the case of FIG. Fig. 8 is a schematic line diagram showing the circuit structure of the second embodiment, and the figure shows an example when 9 wafers are mounted. 9 (a) and 9 (b) are schematic diagrams showing the arrangement structure of the wafer on the multilayer substrate in the case of FIG. Fig. 10 is a schematic diagram showing a structure of a COB of a composite wafer in which a memory chip "ASIC chip" microcomputer chip is mounted on a multilayer wiring substrate. Fig. 11 is a schematic diagram showing the structure of a conventional COB with an example of a memory module. (A) is a perspective view showing the overall structure, and (b) is a side view.

C: \ 2D-CODE \ 92-01 \ 91124366.ptd Page 19 567565 Brief description of the drawing A cross-sectional view showing the mounting structure of two adjacent ICs mounted on a multilayer wiring board. Fig. 12 is a flow chart showing the manufacturing steps of a conventional memory module, a circuit diagram of a set of modules, and a table of memory and knowledge. The figure is roughly 3 11 Middle a) a Figure 1 (4 Dressing is when there are many layers. Case 13 The actual picture shows the situation and the situation is used. Figure 1C outlines the circuit module of the circuit to remember the knowledge of one person. The outline of the line diagram used in the study table is based on the base line of the 15-line diagram. If the case is shown in the figure C, the outline of the 1C diagram is roughly 18 (B) Show a κί \ in Figure C. Figure 16 and Figure Φ The model of the circuit building tool to remember the learning of the ancient mouth. The outline of the schematic diagram of the line drawing is based on the 17 line drawing and the drawing line. When there have been many layers. Example 17 The actual picture is shown in the table and the situation is used. The 1C picture is a little 36. The outline is shown in the figure. B) The C display is shown in a.

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Claims (1)

567565 ν. Ι ζ Replacement of this case _ Case No. 91124366 VI. Patent application scope 1. A board-connected chip, and the board has multiple chips mounted adjacent to it. Second: Convergence is equipped with: Multi-layer wiring base overlapping The way is installed :: The; solid: said piece of film " respectively in a single or two parts; a plurality of connection pads, the bathroom, the wire substrate each chip mounted on the above-mentioned multilayer wiring base = The corresponding part of the work is provided with a crystal moon connection " contact pad, on the wafer or the uppermost connection; skip pad ,; set to connect the corresponding connection pad to the above-mentioned multilayer wiring board: with; Description: The contact liner 'is used to connect = 件 pieces' or straddle the layers of the above-mentioned multilayer wiring substrate; and the two θ's are used to mold each of the above wafers and each pad; 2 ^ Φ The upper wafer is a wafer that passed the electrical characteristics test. Λΐ :: On-board connected wafer of the first item in the range, in which the above test fails: Among the T wafers, the wafer other than the uppermost part is the electrical characteristic test η On-board connected wafer of the first item in the patent scope Among them, the wafers in the wafer mounting portion of the ^^ layer wiring board are divided into ^, and the specified group of wafers do not receive signals through the jumper wiring. The other groups of wafers receive jumper wiring. Accept the signal. # 4 · If the board-connected wafer of item 2 of the patent application scope, wherein the wafers mounted on the wafer mounting portion of the above-mentioned wiring board are divided into f's and designated groups of wafers No signal is received via the jumper wiring. Chips in other groups receive signals via the jumper wiring. 5 · A board-connected chip, which is characterized by: multi-layer wiring base c: \ master file \ 91 \ 91124366 \ 91124366 (replacement)].! Page 21 567565 VI. Patent application board, multi-layer configuration multiple The wiring substrate includes a plurality of wafer mounting portions on the main surface side wiring substrate constituting the main surface and the other surface side wiring substrate constituting the other surface, and a plurality of wafers are respectively mounted on the main surface side and the other. Each wafer mounting portion of the wiring substrate on one surface side; a plurality of connection pads, 'are provided on the wiring substrate on the main surface side and the other surface side, respectively, so as to correspond to the respective wafers described above, and form a connection with the corresponding wafer; A plurality of contact pads are respectively provided on the main surface side and the other side of the wiring substrate to correspond to each of the above-mentioned connection pads, to form connections with the corresponding connection pads, and through holes are provided to span the above-mentioned main Wiring board on the front side and the other side; jump over the pads, and the wiring board on the other side of the main side side temple entrance is close to the contact Pads are used to connect the above-mentioned through-holes; edge terminals are provided on one or both of the above-mentioned main surface side and the other side of the wiring substrate, and are used to connect the above-mentioned through-hole resins to the above main Each wafer and each pad of the wiring soil board on the front side and the other side are molded. 6: =, The above-mentioned wafer in the on-board wafer 8 of any one of the patent scope! To 5 is a memory wafer. Step 7: Package: Manufacturing method of upper-connected wafer, which is characterized by: "Each wafer mounting portion of a multilayer wiring substrate having a plurality of wafer mounting portions, and Pads and connections corresponding to each connection pad 2 ^ 々μ τ Contact liner; Connect the test device to C: \ Overall \ 91 \ 91124366 \ 91124366 (replace) -1.ptc Page 22 567565 After receiving each of the above contact pads, it is used to test and cut off the wafers and the wafers that have become unqualified in the test described above; characteristics; connect and overlap the wafers that pass the test on the unqualified wafers; each of the wafers and each pad described Molded. 8. The manufacturing steps of a board-connected wafer include the following: a special test device for connecting each of each of the sintering pads and the layer wiring substrate to each of the connection test devices provided adjacent to the wafer. Electrical characteristics of the connecting lining qualified crystal 9. As claimed, in which the wafer is mounted on the wafer mounting section, and each connection board, connecting the connection profile and the wafer with the specified connection to obtain the above connection to the above; Cut off the connection of the above pads, and the pieces; and the above-mentioned patents, the above-mentioned wafers, a plurality of green substrates, and the above-mentioned multiple pads, and the jumper is connected with the above-mentioned finger contact pads; each wafer corresponds to it. Molded with test lines. The manufacturer has a plurality of layers of wafer mounting portions, and sets contact pads corresponding to the respective pads corresponding to the above-mentioned wafers on each wafer, and correspondingly connects with the corresponding contact pads; The pad and the near corresponding contact pad use the respective designated wafers and the respective contact pads adjacent to the wafers, and the test used for the test is to become a non-compliant wafer and each of the wafers overlapped on the non-compliant wafer. With each pad, the on-board chip of item 7 or 8 is a memory chip.