JP2003258195A - Chip-on-board and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-on-board and a method for manufacturing the same, which enables direct mounting of dies on a multilayer circuit board, and standardization of the multilayer circuit board, and is able to further manufacturing processes, without demounting the dies, even if unsuccessful in electrical characteristics tests. <P>SOLUTION: The chip on board is provided with the multilayer circuit board 1 having portions for mounting a plurality of dies, a plurality of dies 10 which are mounted on the individual die-mounting portions singly or with more than two of them being stacked, a plurality of bonding pads 11 which are disposed in correspondence with the die mounting portions, respectively, being connected to a single die 10 or an uppermost die 10Y, contact pads 13 which are disposed in correspondence with the bonding pads 11, respectively, each being connected to a corresponding bonding pad 11, jumper pads 15 which are disposed close to the contact pads 13, each being connected to an edge terminal 4, a circuit element or a through-hole 17, and a mold resin 18 for molding the whole. The uppermost die should be the one that has passed the electrical characteristics testings. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Board, especially memory chip, microcomputer chip, ASIC
The present invention relates to a chip-on-board in which a semiconductor chip (die) such as a chip is mounted on a multilayer wiring board and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 11 is a schematic view showing the structure of a conventional chip-on-board (hereinafter referred to as COB) by way of example of a memory module, and (a) is a perspective view showing the whole structure.
(B) shows a configuration in which two adjacent ICs in the configuration shown in (a) are mounted on a multilayer wiring board. In these figures, 1 is a multilayer wiring board, 2 is a large number provided on the multilayer wiring board, and IC lead pads for connecting and fixing the leads of the IC to mount the IC on the multilayer wiring board 1 and 3 are IC leads. A wiring pattern for electrically connecting the pads 2 to each other, connecting to ICs, connecting to circuit elements (not shown) such as resistors, capacitors and fuses mounted on the multilayer wiring board, and straddling the multilayer wiring board. Formed on the surface of the multilayer wiring board 1 in a predetermined pattern for connection with through-holes for connecting the wiring boards or for connection with the edge terminal 4 serving as a connection terminal outside the multilayer wiring board. It is what is done. Reference numeral 5 denotes an IC, which is mounted on the multilayer wiring board 1 by fixing a plurality of leads 5A to the IC lead pad 2.

FIG. 12 is a flow chart showing a manufacturing process of the memory module shown in FIG. That is, in step S1, a memory chip (die, not shown) is die-bonded to a known lead frame (not shown). Next, in step S2, the die and the lead frame are wire-bonded. Subsequently, in step S3, the die and the lead frame are resin-molded to form the IC5. After that, an electric characteristic test is performed for each IC in step S4, and if it fails, it is discarded in step S5, and if it passes, step S
6 is mounted on the multilayer wiring board 1 as shown in FIG. Then, in step S7, an electrical characteristic test as a memory module is performed, and the manufacturing process ends.

13 to 18 show the IC5 in step S6.
FIG. 13 and FIG. 14 are schematic diagrams showing a circuit configuration and a method of arranging ICs when mounting the ICs on the multilayer wiring board 1.
15 and 9 are mounted, the ICs shown in FIGS.
17 and FIG. 18 show the case of mounting 36 ICs, respectively. When 9 ICs are mounted, each IC is arranged and mounted on the multilayer wiring board as shown in FIG. This figure shows an example in which the multilayer wiring board 1 has two layers. (A) shows the wiring board 1a of the first layer on the front surface, and (b) shows the wiring board 1b of the second layer on the back surface.
Indicates. The nine ICs are divided into two groups of four and five, and the groups of four (5a1 to 5a4) are arranged on the first-layer wiring board 1a as shown in the figure and the group of five ( 5b1 to 5b5) are second-layer wiring boards 1
It is arranged as shown in FIG. 5b, and the connection between both substrates is made by a through hole (not shown). Reference numeral 50 in the first-layer wiring board 1a is a connecting IC for connecting to an external circuit via the edge terminal 4.

The circuit configuration is as shown in FIG. 13, in which clock signals (Add, CKEO, / SO-3, etc.) and I / O signals (DQ
0 ... etc. are each IC (5a1-5) of a group of 4
a4) and each IC of the group consisting of 5 (5b1-5)
b5) are separately supplied in parallel. For convenience of illustration, for example, the clock signal for the IC 5a2 is supplied via the IC 5a1, but is supplied to the IC 5a2 without passing through the IC 5a1 and similarly to the IC 5a3. , I
The connection is such that it is supplied without passing through C5a1 and IC5a2. The same applies to other ICs. The same applies to the I / O signal.

Further, when mounting 18 ICs, each IC is arranged and mounted on the multilayer wiring boards 1a and 1b as shown in FIG. That is, nine wiring boards are arranged on each of the first-layer wiring board 1a and the second-layer wiring board 1b. The connection IC 50 and the through hole (not shown) are the same as those in the case of FIG.
The circuit configuration is as shown in FIG. The method of supplying each signal to each IC is the same as that in FIG. 13, and only the difference is that the number of ICs in each group is 9, and therefore the description is omitted. Further, when 36 ICs are mounted, each IC is divided into 4 groups of 9 ICs, and as shown in FIG.
It is arranged and mounted on b. That is, the wiring substrate 1a of the first layer
And two groups of 18 wiring boards are arranged on the second-layer wiring board 1b. The connection IC 50 and the through hole (not shown) are the same as those in the case of FIG.

The circuit configuration is as shown in FIG. The clock signals (Add, CKEO, / SO-3, etc.) have the number of parallel circuits increased by the increase in the number of groups with respect to FIG. 13, but the method of supply to each group is the same as in FIG. The I / O signals (DQ0 ...) Are also supplied in parallel to the ICs of each group, and are electrically similar to those in FIG. For convenience of illustration, for example, the I / O signal to the IC 5d1 is supplied via the IC 5b1, but the IC 5b1 is supplied to the IC 5b 1.
The connection is such that it is supplied without going through 1. This is the same for ICs 5a1 and 5c1 as well.
The same applies to C.

[0008]

Since the conventional memory module is constructed as described above, there is a problem that a lead frame is required and the material cost becomes high. In addition, the manufacturing process also requires two processes, a process of die-bonding a die to a lead frame to form an IC, and a process of mounting the IC on a wiring board for a module, resulting in a high manufacturing cost. There was a point. Further, if the result of the electrical characteristic test of the IC is a failure, there is a problem that the mold resin and the lead frame of the IC to be discarded are wasted because they are discarded. Furthermore, when mounting an IC on a wiring board, the circuit configuration and the layout configuration of the multilayer wiring board differ depending on the number of ICs to be mounted, so that it is necessary to prepare several types of multilayer wiring boards. there were.

The present invention has been made in order to solve the above problems, without using a lead frame,
An object of the present invention is to provide a COB having a structure in which a semiconductor chip (die) such as a memory chip is directly mounted on a multilayer wiring board. Further, the present invention provides a COB capable of using the same multilayer wiring board even when the number of dies is changed, when mounting the die on the multilayer wiring board, and thus reducing the number of types of multilayer wiring boards. The purpose is to Furthermore, the present invention mounts the die on a multilayer wiring board, conducts an electrical characteristic test before molding with a resin, and if there is a die that fails, connect the connecting wire between the reject die and the multilayer wiring board. It is an object of the present invention to provide a COB manufacturing method in which the manufacturing process can be carried out only by removing the rejected die without removing the rejected die.

[0010]

COB according to the present invention
Is a multi-layer wiring board having a plurality of die mounting parts, a plurality of dies mounted on each die mounting part of the multi-layer wiring substrate singly or in a stack of two or more, and corresponding to each die mounting part. A plurality of bonding pads arranged on the multilayer wiring board and connected to a single die or an uppermost die, and corresponding bonding pads arranged on the multilayer wiring board corresponding to the respective bonding pads. Connected to the contact pad connected to the contact pad, and to an edge terminal of the multilayer wiring board, a circuit element mounted on the multilayer wiring board, or a through hole extending over each layer of the multilayer wiring board. Equipped with a jumper pad and a molding resin that molds the above-mentioned dies and pads. It is an die that have passed the test.

In the COB according to the present invention, among the dies formed by stacking two or more of the above, the dies other than the top die are the dies that have failed the electrical characteristic test.

The COB according to the present invention also divides the dies mounted on the die mounting portion of the above-mentioned multilayer wiring board into a plurality of groups, and the dies of a predetermined group receive signals without using jumper wiring. , The other groups of dies are designed to receive signals via jumper wires.

In the COB according to the present invention, a plurality of wiring boards are arranged in multiple layers, and a plurality of die mounting portions are respectively provided on the main surface side wiring board forming the main surface and the other surface side wiring board forming the other surface. A multi-layer wiring board having, a plurality of dies mounted on each die mounting portion of the main surface side and the other surface side wiring board, and on the main surface side and the other surface side wiring board corresponding to each die A plurality of bonding pads respectively arranged and connected to the corresponding die, and arranged on the main surface side and the other surface side wiring boards respectively corresponding to the respective bonding pads and connected to the corresponding bonding pads. A plurality of contact pads, a through hole provided over the main surface side and the other surface side wiring board, and a plurality of through holes provided in the main surface side and the other surface side wiring board in the vicinity of the contact pad, respectively. A jumper pad connected to the through hole, an edge terminal provided on one or both of the main surface side and the other surface side wiring board and connected to the through hole, and each of the main surface side and the other surface side wiring board. It is provided with a die and a molding resin for molding each pad. The COB according to the present invention also uses the die as a memory chip.

In the method for manufacturing a COB according to the present invention, a die is attached to each die attaching portion of a multilayer wiring board having a plurality of die attaching portions, and a plurality of bonding pads corresponding to the above-mentioned die and each bonding are provided. A step of arranging contact pads corresponding to the pads on the above-mentioned multilayer wiring board and connecting between each die and the corresponding bonding pad and between each bonding pad and the corresponding contact pad, testing each contact pad Connecting the equipment and testing the electrical properties of each die,
While disconnecting the die and the corresponding bonding pad that failed the above test, the step of stacking and mounting the tested die on the failed die, and each die and each pad And a step of molding and.

In the method of manufacturing a COB according to the present invention, a die is attached to each die attaching portion of a multilayer wiring board having a plurality of die attaching portions, and a plurality of bonding pads corresponding to the die are provided. A step of arranging contact pads corresponding to each bonding pad on the multilayer wiring board and connecting between each die and the corresponding bonding pad and between each bonding pad and the corresponding contact pad, to a predetermined die A jumper which is provided near a corresponding contact pad and a contact pad corresponding to a die adjacent to the predetermined die so that the predetermined die and the adjacent die can be connected by connecting with each contact pad. The process of arranging the pads, connecting the test equipment to each of the above contact pads, and A step of testing the property, a step of disconnecting the die and the bonding pad corresponding to the die that failed in the above test, and a step of mounting the tested die on the die that has failed, and It has a step of molding each die and each pad.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing the configuration of the first embodiment as an example of a memory module. (A) is a perspective view showing the overall configuration of the memory module, and (b) is an adjacent two of the configurations shown in (a). FIG. 3 is a schematic plan view showing the configuration of one die and bonding pads, contact pads, jumper pads and the like provided between them, and FIG. 6C is a side sectional view showing the configuration on the multilayer wiring board shown in FIG. In these figures, reference numeral 1 denotes a multilayer wiring board, on the surface of which a plurality of die mounting portions are arranged. 10
Are nine memory chips (dies) fixed to the die mounting portions, and are directly fixed to the multilayer wiring board without die bonding to the lead frame as in the conventional case.
The die 10 is mounted on the multilayer wiring board 1 by itself as shown in the left side of FIG. 1C, and two dies 10X are provided as shown in the right side of FIG. 1C. It may be mounted in the form of overlapping with 10Y. Two dies can be mounted in a stack
It may be more than one. Details will be described later.

10A is a pad provided on each die,
Reference numeral 11 is a bonding pad provided on the multilayer wiring board 1 corresponding to each die mounting portion, and 12 is a die 10 (if two or more are mounted in a stacked form, the uppermost die 10 is used).
Y) a wire connecting the pad 10A and the bonding pad 11, 13 is a contact pad provided on the multilayer wiring substrate 1 corresponding to the bonding pad 11, and 14 is a wiring pattern connecting the bonding pad 11 and the contact pad 13. , 15 are jumper pads provided in the vicinity of the contact pads 13, 16 is a wiring pattern for connecting the jumper pads 15 to each other, which is connected to the edge terminal 4 which is a connection terminal to the outside of the multilayer wiring board, or the multilayer wiring board. 1. Connection with circuit elements (not shown) such as capacitors, resistors, fuses, etc. mounted on 1 or formed across a plurality of wiring boards constituting a multilayer wiring board,
The wiring patterns are arranged in a predetermined pattern for connection with the through holes 17 for connecting the wiring boards.

FIG. 2 is a flow chart showing a manufacturing process of the memory module shown in FIG. In step S11, the nine dies 10 are die-bonded to the multilayer wiring board 1. Next, in step S12, the die pad 10A and the bonding pad 11 are wire-bonded. Then, in step S13, a tester (not shown) is connected to the contact pad 13 and an electrical characteristic test of the die 10 is performed. In this test, for example, if the die 10X in FIG. 1C fails, the wire (not shown) connecting the failed die 10X and the bonding pad 11 is removed in step S14 to remove the die. Disconnect 10X from the circuit. However, the die 10X is not removed, but is left as it is on the multilayer wiring board 1 as illustrated.

Next, in step S15, a die 10Y that has passed the electrical characteristic test targeting only the die 10 separately prepared is prepared, and in step S16, the passed die 10Y is prepared.
Is overlaid on the rejected die 10X and die-bonded. After that, the pad of the pass die 10Y, which is the uppermost die of the stacked dies in step S17, is wire-bonded to the bonding pad 11, and the pass die 10Y is connected instead of the fail die 10X to form a circuit. Next, in step S18, the contact pad 13 and the jumper pad 1
5 and 5 are wire-bonded to each other. continue,
In step S19, each die 10, 10 on the multilayer wiring board 1
The X and 10Y, the bonding pad 11, the contact pad 13, the jumper pad 15, the wire 12 and the wiring patterns 14 and 16 are molded with the molding resin 18. Then, in step S20, an electrical characteristic test as a memory module is performed, and the manufacturing process ends.

Embodiment 2. Next, a second embodiment of the present invention will be described with reference to the drawings. 3 to 9 show the configuration of the second embodiment as an example of a memory module, and show a circuit configuration and a method of disposing the die 10 when the die 10 is mounted on the multilayer wiring board 1 in step S11 described above. FIGS. 3 and 4 are schematic diagrams showing that 36 dies are mounted, FIGS. 6 and 7 are 18 dies, and FIGS. 8 and 9 are 9 dies are mounted. Are shown respectively. First, when 36 dies 10 are mounted, each die is arranged and mounted on the multilayer wiring board 1 as shown in FIG. This figure shows an example in which the multilayer wiring board 1 has two layers. (A) shows the wiring board 1a of the first layer which is the surface,
(B) shows the second-layer wiring board 1b which is the back surface. 36
Each of the dies 10 forms a group of four or five dies and is divided into a total of eight groups (a group to h group). The wiring board 1a of the first layer includes a group (10a1 to 10a5) and b group (10b1 to 10a1).
b4), c groups (10c1 to 10c4), and d groups (10d1 to 10d5), four groups of dies are arranged, and the second layer wiring board 1b has an e group (10e).
1 to 10e5), f group (10f1 to 10f4),
g group (10g1-10g4) and h group (1
Four groups of dies (0h1 to 10h5) are arranged.

FIG. 5 is a schematic view showing a cross-sectional structure of the wiring substrate 1a of the first layer and the wiring substrate 1b of the second layer in a portion surrounded by a circle in FIG. 4 (a). 3 schematically shows the connection relationship with the through hole 17 to be connected. Since the reference numerals in the figure are the same as those in FIG. 1C, the description thereof will be omitted. The position of the through hole 17 in this figure is an example, and the position is not limited to this position.
The circuit configuration is as shown in Fig. 3. Clock signals (Add, CKEO, / SO-3 etc.) and I / O signals (DQ0 ... etc.) are supplied in parallel to each die of each group. It is configured to be. For convenience of illustration, for example, the clock signal for die 10a3 is configured to be provided through dies 10a1 and 10a2, but dies 10a1 and 1
The connection is such that the dies are supplied in parallel without passing through 0a2. The same applies to the other dies. The same applies to the I / O signal.

The clock signals are connected so as to be directly supplied to the dies (10a1 to 10a5) of the a group and the dies (10b1 to 10b4) of the b group without passing through the jumper wiring 20. But c
The dies of the groups h to h are supplied through the jumper wiring 20. Also, I /
The O signal is connected so as to be directly supplied to the dies in the a group to the d group without passing through the jumper wiring 20, but is connected to the dies in the e group to the h group by the jumper. It is configured to be supplied via the wiring 20. As will be described later, this means that when the number of dies mounted on the multilayer wiring board decreases and only some groups of dies are connected, the circuit where the dies are not mounted is connected. Since it causes a malfunction when played with, the circuit of the part where the die is not mounted can be separated by the jumper wiring part.

Next, in the case of mounting 18 dies 10, the same multilayer wiring board as in the case of mounting 36 dies is used as shown in FIG. 7, and only the first layer wiring board 1a is shown. And is not arranged on the second-layer wiring board 1b. The layout of the dies of the wiring board 1a of the first layer is the same as that of FIG. 4, and 18 dies of groups a to d are arranged. In the circuit configuration in this case, as shown in FIG. 6, only the dies of groups a to d, which are hatched in the figure, are connected, and the connecting lines of groups e to h are connected to the clock signal side and the I line. The jumper wiring 20 on the / O signal side is entirely disconnected. Also, die 10
In the case of individually mounting, as shown in FIG. 9, the same multilayer wiring board as in the case of mounting 36 pieces is used, and the wiring board of the second layer is arranged only on the wiring board 1a of the first layer as shown in the drawing. Board 1
Not placed in b. The circuit configuration in this case is as shown in FIG. 8, and there are nine die of group a and group b (shown by hatching in FIG. 8) that can be connected to the signal source without passing through the jumper wiring 20. It is arranged as shown in FIG. 9A, and the broken line portion becomes empty. Further, as shown in FIG. 8, all the jumper wirings 20 are in a disconnected state, and all the connection lines other than the die of the a group and the b group are disconnected.

Although each of the above embodiments has been described by taking the example of the memory module, the present invention is not limited to the memory module and can be similarly applied to a microcomputer chip or an ASIC chip. FIG. 10 shows a memory chip 10, an ASIC chip 30,
The schematic of COB of the composite die which mounted the microcomputer chip 40 is shown. Since the manufacturing method is the same as that of the memory module described above, description thereof will be omitted.

[0025]

The COB according to the present invention comprises a multi-layer wiring board having a plurality of die mounting portions, and a plurality of dies mounted on each die mounting portion of the multi-layer wiring board singly or in a stack of two or more. A plurality of bonding pads arranged on the multilayer wiring board corresponding to the die mounting parts and connected to a single die or an uppermost die, and the multilayer wiring board corresponding to the bonding pads. A contact pad disposed above and connected to a corresponding bonding pad, and an edge terminal of the multi-layer wiring board or a circuit element mounted on the multi-layer wiring board or the multi-layer, which is disposed in the vicinity of the contact pad. Two jumper pads connected to through holes extending over each layer of the wiring board, and a mold resin for molding each die and each pad are provided. Because the top of the die superimposed on, is to die which pass an electrical characteristic test, COB such as a memory module without using a lead frame
In addition, since the electrical characteristic test is performed before molding, the waste of the mold does not occur even if it fails. For dies that failed the electrical characteristics test, simply remove the connecting wires, leave the failed dies as they are on the multilayer wiring board, and pass the electrical characteristics test only for the dies that were performed separately. Since the dies are stacked and mounted and resin-molded, the number of manufacturing steps can be reduced, which is effective in cost reduction.

The COB according to the present invention also divides the dies mounted on the die mounting portion of the multilayer wiring board into a plurality of groups, and the dies of a predetermined group receive signals without using jumper wiring. , The dies of the other groups receive the signal through the jumper wiring, the possibility of malfunction is reduced, and the reliability can be improved.

In the COB according to the present invention, a plurality of wiring boards are arranged in multiple layers, and a plurality of die mounting parts are respectively provided on the main surface side wiring board forming the main surface and the other surface side wiring board forming the other surface. A multi-layer wiring board having, a plurality of dies mounted on each die mounting portion of the main surface side and the other surface side wiring board, and on the main surface side and the other surface side wiring board corresponding to each die A plurality of bonding pads respectively arranged and connected to the corresponding die, and arranged on the main surface side and the other surface side wiring boards respectively corresponding to the respective bonding pads and connected to the corresponding bonding pads. A plurality of contact pads, a through hole provided over the main surface side and the other surface side wiring board, and a plurality of through holes provided in the main surface side and the other surface side wiring board in the vicinity of the contact pad, respectively. A jumper pad connected to the through hole, an edge terminal provided on one or both of the main surface side and the other surface side wiring board and connected to the through hole, and each of the main surface side and the other surface side wiring board. Since the die and the molding resin for molding the pads are provided, the multilayer wiring board can be standardized, and the productivity can be improved and the cost can be reduced.

[Brief description of drawings]

1A and 1B are schematic diagrams showing a configuration of a first embodiment of the present invention as an example of a memory module, in which FIG. 1A is a perspective view showing an overall configuration, and FIG. 1B is an adjacent configuration of FIG. 1A. FIG. 2 is a schematic plan view showing the configuration of two dies and various pads provided between them, and FIG. 6C is a side sectional view showing the configuration of the multilayer wiring board shown in FIG.

FIG. 2 is a flowchart showing manufacturing steps of the memory module shown in FIG.

FIG. 3 is a schematic diagram showing a circuit configuration according to the second embodiment of the present invention, showing an example of a case where 36 dies are mounted.

FIG. 4 is a schematic diagram showing an arrangement configuration of dies on a multilayer wiring board in the case of FIG.

FIG. 5 is a schematic diagram showing a cross-sectional structure of a first-layer wiring board and a second-layer wiring board that form a multilayer wiring board.

FIG. 6 is a schematic diagram showing a circuit configuration according to the second embodiment, showing an example of mounting 18 dies.

FIG. 7 is a schematic diagram showing a layout configuration of dies on a multilayer wiring board in the case of FIG. 6;

FIG. 8 is a schematic diagram showing a circuit configuration according to the second embodiment and shows an example in which nine dies are mounted.

FIG. 9 is a schematic diagram showing a layout configuration of dies on a multilayer wiring board in the case of FIG. 8;

FIG. 10 is a schematic diagram showing a COB configuration of a composite die in which a memory chip, an ASIC chip, and a microcomputer chip are mounted on a multilayer wiring board.

FIG. 11 is a schematic diagram showing a configuration of a conventional COB as an example of a memory module, (a) is a perspective view showing the entire configuration,
(B) is a side sectional view showing a mounting configuration of two adjacent ICs on a multilayer wiring board.

FIG. 12 is a flowchart showing manufacturing steps of a conventional memory module.

FIG. 13 is a schematic diagram showing a circuit configuration of a conventional memory module, showing an example in which nine ICs are mounted.

FIG. 14 is a schematic diagram showing the configuration of the multilayer wiring board in the case of FIG.

FIG. 15 is a schematic diagram showing a circuit configuration of a conventional memory module, showing an example of mounting 18 ICs.

16 is a schematic diagram showing a configuration of a multilayer wiring board in the case of FIG.

FIG. 17 is a schematic diagram showing a circuit configuration of a conventional memory module, showing an example of mounting 36 ICs.

FIG. 18 is a schematic diagram showing the structure of the multilayer wiring board in the case of FIG.

[Explanation of symbols]

1 multilayer wiring board, 4 edge terminals, 10
Die, 10A die pad, 10X reject die, 10Y pass die, 11 bonding pad, 12 wire, 13 contact pad,
14, 16 wiring pattern, 15 jumper pad, 17 through hole, 18 resin mold,
20 jumper wiring, 30 ASIC chip,
40 microcomputer chip, 50 connection IC.

Claims (8)

[Claims] 1. A multi-layer wiring board having a plurality of die mounting parts, a plurality of dies mounted on each die mounting part of the multi-layer wiring substrate singly or in a stack of two or more, and each of the die mounting parts. Correspondingly arranged on the multilayer wiring board,
A plurality of bonding pads connected to a single die or an uppermost die, contact pads arranged on the multilayer wiring board corresponding to the bonding pads and connected to corresponding bonding pads, and the contacts Jumper pads arranged in proximity to the pads and connected to edge terminals of the multilayer wiring board or circuit elements mounted on the multilayer wiring board or through holes extending over each layer of the multilayer wiring board; A chip-on-board characterized in that the uppermost die, which is equipped with a molding resin that molds each pad, is a die that has passed the electrical characteristic test. 2. The chip-on-board according to claim 1, wherein among the dies formed by stacking two or more dies, the dies other than the top die are dies that have failed the electrical characteristic test. 3. The dies mounted on the die mounting portion of the multilayer wiring board are divided into a plurality of groups, the dies of a predetermined group receive signals without jumper wiring, and the dies of other groups are The signal is received via a jumper wiring.
Alternatively, the chip-on-board according to claim 2. 4. A multi-layer wiring board having a plurality of wiring boards arranged in multiple layers, each having a plurality of die mounting parts on the main surface side wiring board forming the main surface and the other surface side wiring board forming the other surface,
A plurality of dies mounted on the die mounting portions of the main surface side and the other surface side wiring board respectively, and arranged on the main surface side and the other surface side wiring board respectively corresponding to the respective dies, and corresponding. A plurality of bonding pads connected to the die, respectively arranged on the main surface side and the other surface side wiring substrate corresponding to each of the bonding pads, a plurality of contact pads connected to the corresponding bonding pad, Through holes provided over the main surface side and the other surface side wiring board, and jumpers respectively provided on the main surface side and the other surface side wiring board near the contact pads and connected to the through holes A pad, an edge terminal provided on one or both of the main surface side and the other surface side wiring board and connected to the through hole, and each die of the main surface side and the other surface side wiring board. Beauty chip-on-board and a resin molding the respective pads. 5. The chip on board according to claim 1, wherein the die is a memory chip. 6. A multi-layer wiring board having a plurality of die mounting portions is mounted with a die on each die mounting portion, and a plurality of bonding pads corresponding to the respective die and contact pads corresponding to the respective bonding pads are formed. A step of arranging on a multilayer wiring board and connecting between each die and corresponding bonding pad and between each bonding pad and corresponding contact pad, connecting a test device to each contact pad, The process of testing the electrical characteristics, disconnecting the connection between the die that failed the test and the corresponding bonding pad,
A method for manufacturing a chip-on-board, comprising: mounting a tested pass die on a rejected die; and molding the die and pads. 7. A multi-layer wiring board having a plurality of die mounting parts is mounted on each die mounting part, and a plurality of bonding pads corresponding to the respective dies and contact pads corresponding to the respective bonding pads are mounted on the plurality of die mounting parts. Arranging on the multilayer wiring board, connecting between each die and the bonding pad corresponding to each, and between each bonding pad and the contact pad corresponding to them, the contact pad corresponding to a predetermined die and the above-mentioned predetermined die A step of arranging a jumper pad which is provided close to a contact pad corresponding to an adjacent die and which can connect the predetermined die and the adjacent die by connecting with each contact pad; The process of connecting the test equipment to the pad and testing the electrical characteristics of each die. Disconnecting the connection between the die and the corresponding bonding pad, and mounting the tested pass die on the rejected die, and the step of molding each die and each pad. A method for manufacturing a chip-on-board having the same. 8. The chip-on-chip according to claim 6, wherein the die is a memory chip.
Board manufacturing method.