JP2974315B1 - Stacked semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a structure in which two or more identical chips can be easily stacked. SOLUTION: A first semiconductor chip 1 including a lead frame 105, ICs are formed above and below the lead frame 105, and bonding pads are formed at substantially the same positions in a chip surface.
01 and the second semiconductor chip 103 are arranged, and the position where the first semiconductor chip 101 and the lead frame 105 are wire-bonded is set to the bonding pad 1 of the first semiconductor chip 101.
The lead frame 105 and the lead line 125 are wire-bonded at the position from the position 01a to a position separated in the chip plane by the lead line 125, and the second semiconductor chip 103 and the lead frame 105 are The semiconductor chip 103 is wire-bonded to the lead frame 105 at the position of the bonding pad 103a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor device having a plurality of semiconductor chips mounted in a package, and more particularly, to the lead frame and the integrated circuit at substantially the same position in a chip surface. The present invention relates to a stacked semiconductor device in which at least two semiconductor chips each including a memory circuit as a main part and having a bonding pad for wire bonding for forming an electrical connection with the semiconductor chip are stacked.

[0002]

2. Description of the Related Art Recently, with the rapid development of semiconductor package manufacturing technology, research and development of a stacked semiconductor device in which a larger number of semiconductor chips are accommodated and arranged in a limited area has been actively conducted. In particular, in a semiconductor chip having a memory circuit as its main part, for example, by stacking two identical chips, the storage capacity of the stacked semiconductor device as a whole is doubled, and the limited space is effectively used. Thus, an increase in storage capacity can be realized.

Conventionally, a semiconductor device having a configuration in which a plurality of semiconductor chips are housed in the same package is disclosed in
A structure having a configuration as disclosed in JP-A-35444 has been proposed. FIG. 3 shows a laminated structure disclosed in this publication. In this laminated structure A, the first and second two semiconductor chips 3 and 5 above and below the chip support 1 are supported, and wire bonding is formed by wires 11 to the lead wires 7 from above and below. .

Japanese Patent Application Laid-Open No. 63-136642 discloses a structure as shown in FIG. In this structure, two upper and lower semiconductor chips 3 and 5 are stacked. The lead wires 7 are connected to heat-resistant insulating films 17 and 17 provided on both sides of the laminated structure of the chip via adhesive layers 15 and 15, and the lead wires 7 and 7 on both sides are connected.
Are bonding pads 5a and 5b of chips 3.5
They are electrically connected via the bumps 21 to form a laminated structure B.

On the other hand, a manufacturing method as shown in steps a) to d) of FIG. 5 has been devised. According to this manufacturing method, after the semiconductor chips 23 and 25 are wire-bonded to the respective lead wires 27a and 27b in separate steps, these separately formed structures are turned upside down and laminated. Form structure C. By using such a process, a stacked structure can be formed using the same chip. For example, a semiconductor device having twice the storage capacity can be manufactured.

[0006]

However, FIG.
In the laminated structure A as shown in FIG. 7, when the upper and lower semiconductor chips 3 and 5 have the same integrated circuit pattern, the positions of the bonding pads for performing wire bonding are the same. When the two semiconductor chips are simply turned upside down to form a laminated structure, there is a problem that the position of the pads is shifted and the subsequent wire bonding process is complicated. further,
Since the wire bonding must be performed in the vertical direction, there is a problem that the manufacturing process is complicated.

On the other hand, also in the laminated structure B as shown in FIG. 4, since the semiconductor chips 3 and 5 need to be turned over,
The same problems as those in the conventional example described above cannot be solved, and the process of connecting leads and pads using bumps is required, so that the process is inevitably complicated. Further, in connection with the use of two semiconductor chips one inside out, it is necessary to prepare two types of chip circuits. However, it becomes necessary to prepare two types of chips. There has been a problem that the cost is increased. Therefore, even with any structure, it is difficult to easily obtain, for example, twice the capacity of the same chip of the memory.

Further, according to the manufacturing method shown in FIG.
It is no longer necessary to prepare two types of chips, but two separate assembling steps are required, and as a result, the problem of increased manufacturing costs cannot be avoided. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a simple structure, for example, capable of obtaining a double capacity with the same chip of a memory.

[0009]

Means for Solving the Problems In order to achieve the above object, the following means were taken. In other words, the stacked semiconductor device according to claim 1 includes a lead frame, and the lead frame and the integrated circuit are located above and below the lead frame at approximately the same position in a chip surface on which an integrated circuit is formed in advance. A stacked semiconductor device in which a first semiconductor chip on which bonding pads for wire bonding for forming an electrical connection are formed and a second semiconductor chip are arranged with the chip surfaces oriented in the same direction. hand,
A position where the first semiconductor chip and the lead frame are wire-bonded is drawn out from a position of a bonding pad provided in advance in the surface of the first semiconductor chip to a position separated in the chip surface by a lead wiring. The lead frame and the lead-out wiring are wire-bonded at the pulled-out position, and the second semiconductor chip and the lead frame are provided in advance in the plane of the second semiconductor chip. The bonding pad and the lead frame are wire-bonded.

In the stacked semiconductor device according to the present invention, the space efficiency is improved by the stacked structure,
The semiconductor chip and the second semiconductor chip are arranged with the chip surfaces facing in the same direction, and the positions for bonding with the lead frame are separated from each other, so that the wire bonding process is easy. Becomes

In the stacked semiconductor device according to the second aspect, in the stacked semiconductor device according to the first aspect, the first semiconductor chip and the second semiconductor chip are configured with a memory circuit as a main part. It is characterized by being the same semiconductor chip.

In the stacked semiconductor device according to the present invention, since the first semiconductor chip and the second semiconductor chip are the same semiconductor chip having a memory circuit as a main part, a space is not required. It is possible to double the storage capacity of the memory device while maintaining good efficiency. In the stacked semiconductor device according to claim 3, in the stacked semiconductor device according to claim 1 or 2, the lead-out wiring is wired on the first semiconductor chip via a polyimide insulating film. It is characterized by being.

In the stacked semiconductor device according to the third aspect, since the lead wiring is wired via the polyimide insulating film, the influence on the integrated circuit formed in advance on the semiconductor chip is small and the reliability is reduced. Can be formed.

According to a fourth aspect of the present invention, in the stacked semiconductor device according to any one of the first to third aspects, the lead frame, the first semiconductor chip, and the second semiconductor are provided. The chip is characterized by being fixed via an adhesive tape.

In the stacked semiconductor device according to the present invention, since the lead frame is fixed to the first semiconductor chip and the second semiconductor chip via an adhesive tape, the semiconductor chip may not be connected. It can be easily and reliably fixed to the semiconductor package.

As described above, the feature of the present invention is that, first, in a chip in which a circuit formed up to a pad is the same, one of the chips is coated with polyimide, and a metal wiring is formed thereon, thereby forming an original chip. Change the position of the pad from the pad of
This is a stacked semiconductor device assembled with an adhesive tape so as to sandwich a lead frame.

Second, the chip mainly has a memory circuit, and the circuit uses either a pad arranged in a center portion or a pad arranged in a peripheral portion,
In the case where the pad is placed in the center part, one is wired with metal wiring on polyimide so that the bonding point moves to the periphery, assembled by wire bonding on the lead, and the other is under the lead Assembled by wire bonding from center pad to lead.

Third, similarly, a chip having pads on the periphery of the chip is formed with metal wiring on one side of the polyimide so that the pad moves from the peripheral pad to the vicinity of the center,
Assembled similarly.

Fourth, the whole is encapsulated with resin, and the leads are bent to form a so-called TSOP type package. The mounting method on a printed board is the same as that of TSOP.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of the present invention will be described with reference to the drawings. FIG. 1 shows a stacked semiconductor device shown as a first embodiment of the present invention. In this stacked semiconductor device D, the same two chips in which pads 101a and 103a are arranged only in the central portion of semiconductor memory chips 101 and 103 having a thickness of about 200 to 300 microns are assembled by a stack method. Configuration. The chip 101 is a lead wire 125 having a thickness of 125 microns.
An adhesive tape 107 having a thickness of 60 microns is arranged below the lead wire 05 and the lead wire 105 and the chip 101 are joined. Wire bonding is performed from the center pad 101a to the lead wire 105 using a wire 111 having a diameter of 20 to 30 microns. Next, the chip 103 is coated with a polyimide film 121 having a thickness of 10 μm on the chip surface, and a lead wire (metal wiring) 125 having a thickness of 1 to 2 μm is formed from the pad 103a to a predetermined peripheral position by a vapor deposition method or the like. Formed.

Next, the chip 103 is connected to the lead wire 105 and the chip 1 by using an adhesive tape 135 on the lead wire 105.
03 is bonded to the back surface. Then, wire bonding is performed by a wire 141 from the end of the lead wire 125 to the lead wire 105. Next, using a mold, the resin 15
5 to form a predetermined outer shape. Next, the lead wire 105 is bent downward to form a 1000 micron thick TS.
This is an OP package D.

Next, a stacked semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows two semiconductor chips 201 and 20 having the same memory circuit.
3, pads 201a and 201b,
This shows a configuration in which two chips on which 03a and 203b are arranged are vertically stacked.

In order to manufacture this laminated structure, first,
In the same manner as in the case of the chip 103 in the first embodiment, the lead wire (metal wiring) 2 is provided on the surface of the chip 201.
25 are formed. The chip 201 and the lead wire 205
The bonding is performed via the adhesive tape 207. Leader 225
Indicates the bonding position to the surrounding pads 201a and 20a.
1b so as to be movable to the center of the chip. Wire bonding is performed by wires 231 from the ends 225a and 225b of the lead wire 225 rearranged near the center to the lead wire 205. Next, the chip 203 is bonded to the lead wire 205 via the adhesive tape 251 in the same manner, and the peripheral pads 203 a
The wire 26 from 203b to the lead wire 205
The wire bonding is performed according to 1. Finally, similarly to the first embodiment, resin encapsulation and lead molding are performed to obtain a product.

According to the above-described method, wire bonding can be performed with both surfaces of the two memory chips facing upward (or downward), and the bonding positions are also different. And a stacked structure of chips can be realized.

[0025]

According to the stacked semiconductor device of the present invention, one of two chips on which the same integrated circuit is formed is provided with metal wiring and the position of a pad used for wire bonding up to a lead is moved. In addition, two semiconductor chips stacked one above the other can be stacked with good space efficiency.

That is, in the stacked semiconductor device according to the first aspect, space efficiency is improved by the stacked structure, and the first semiconductor chip and the second semiconductor chip have their chip surfaces oriented in the same direction. Since they are arranged in a state and the positions for bonding with the lead frame are separated from each other, the wire bonding step is facilitated.

In the stacked semiconductor device according to the second aspect, since the first semiconductor chip and the second semiconductor chip are the same semiconductor chip having a memory circuit as a main part thereof, a space is not required. It is possible to double the storage capacity of the memory device while maintaining good efficiency.

Therefore, conventionally, it was necessary to newly design a chip circuit in order to obtain a semiconductor device having twice the capacity. However, in the system of the present invention, a chip which is suitable for existing mass production is used. Therefore, it can be manufactured at low cost.

In the stacked semiconductor device according to the third aspect, since the lead wiring is wired via the polyimide insulating film, the influence on the integrated circuit formed in advance on the semiconductor chip is small and the reliability is improved. Can be formed.

In the stacked semiconductor device according to the fourth aspect, since the lead frame is fixed to the first semiconductor chip and the second semiconductor chip via an adhesive tape, the semiconductor chip is mounted on the semiconductor chip. It can be easily and reliably fixed to the semiconductor package.

[Brief description of the drawings]

FIG. 1 is a side view of a stacked structure of a semiconductor chip shown as a first embodiment of the present invention.

FIG. 2 is a side view of a stacked structure of a semiconductor chip shown as a second embodiment of the present invention.

FIG. 3 is a diagram showing a first conventional example relating to a laminated structure of a semiconductor chip.

FIG. 4 is a diagram showing a second conventional example relating to a laminated structure of a semiconductor chip.

FIG. 5 shows a manufacturing process shown as a third conventional example relating to a laminated structure of a semiconductor chip.

[Explanation of symbols]

 D Stacked structure 101 First semiconductor chip 101a Bonding pad of first semiconductor chip 103 Second semiconductor chip 103a Bonding pad of second semiconductor chip 105 Lead wire (lead frame) 107 Adhesive tape 111 Wire 121 Polyimide 125 Lead wire (Metal wiring) 135 Adhesive tape 141 Wire

Claims (4)

(57) [Claims] 1. A semiconductor device comprising a lead frame, wherein electrical connections between the lead frame and the integrated circuit are formed above and below the lead frame at approximately the same position in a chip surface on which an integrated circuit is formed in advance. A stacked semiconductor device in which a first semiconductor chip on which a bonding pad for wire bonding is formed and a second semiconductor chip are arranged with the chip surfaces facing in the same direction, wherein the first semiconductor chip The position where the wire bonding is performed between the lead frame and the lead frame is drawn out from the position of a bonding pad provided in advance in the plane of the first semiconductor chip to a position separated in the plane of the chip by a lead wiring. In the above, the lead frame and the lead-out wiring are wire-bonded, and the second The conductor chip and the lead frame, a stacked semiconductor device in which the bonding pads are provided in advance in the plane of the second semiconductor chip and the lead frame is characterized in that it is wire bonding. 2. The stacked semiconductor according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are the same semiconductor chip having a memory circuit as a main part. apparatus. 3. The stacked semiconductor device according to claim 1, wherein the lead wiring is wired on the first semiconductor chip via a polyimide insulating film. 4. The semiconductor device according to claim 1, wherein the lead frame, the first semiconductor chip, and the second semiconductor chip are fixed via an adhesive tape.
13. The stacked semiconductor device according to claim 1.