TW565876B - Method for fabricating recessed source/drain junction of a semiconductor device - Google Patents

Abstract

A method for fabricating a recessed source/drain junction of a semiconductor device is described. A substrate is provided. A gate structure is formed on the substrate, wherein a cap layer is formed on a top of the gate structure. A spacer is formed on the sidewall of the gate structure. Using the cap layer and the spacer as an etching mask, an opening is formed in the substrate beside the side of the spacer. A selective thin film is then formed in the opening as the source/drain region.

Description

565876 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a semiconductor device with a recessed source / drain junction (R e c s s e d Source / Drain Junction). In addition to the metal oxide semiconductor device (MOS) having a gate oxide layer and a gate structure, the substrate on both sides of the gate structure further includes a semiconductor region having electrical properties opposite to the silicon substrate. In the field of very large scale integrated circuits (VLSI), metal-oxide-semiconductor devices are widely used. For example, logic circuits, memory devices, and the like, metal-oxide semiconductor devices are indispensable semiconductor devices. Figures 1A to 1C are schematic cross-sectional views showing the manufacturing process of a conventional semiconductor device. Referring to FIG. 1A, a substrate is first provided, and then a thin oxide layer 102 and a polycrystalline silicon layer are formed on the substrate 100. Next, referring to FIG. 1B, the polycrystalline silicon layer 04 and the thin oxide layer 102 are patterned to form a gate conductive layer 104a and a gate oxide layer 102a. After that, an ion implantation step is performed using the gate conductive layer 104a as an implant mask to form a lightly doped drain region (LDD) in the substrate 丨 00 on both sides of the gate conductive layer 104a. 1 08. After that, please refer to FIG. 1C, a gap wall 110 is formed on both sides of the gate conductive layer 10 ". Then, an ion implantation step is performed using the gap wall u0 as an ion implantation mask to A source / drain region 112 is formed in the substrate 100 on both sides of the wall 110. Then, a metal is formed on the surface of the gate conductive layer 10 "and the source, and the surface of the substrate above the drain 12 12 The silicide layer 4 reduces the resistance values of the gate conductive layer 104a and the source / drain regions 2 and 3.

9166twf.ptd Page 5 565876 V. Description of the Invention (2) However, when the size of the device gradually decreases with the increase of the integration degree of the integrated circuit, the size of the source / drain of the semiconductor device must also be reduced accordingly. . However, the reduction of the source / drain size will cause its resistance to rise, which will reduce the component current and cause excessive load (Qver Loading). If the junction depth of the source / drain is increased (Junction Depth) to solve the problem of increasing the source / drain resistance, not only the short channel effect (Short Channel Effect) will be derived, but also the junction will be easily generated. Leakage (Junction Leakage) and other issues. If the source / drain of the shallow junction is made by using a high concentration of doping to avoid problems such as short channel effects and junction leakage caused by the junction being too deep, then it will be produced due to the solubility of the solid state. It cannot overcome the problem of excessive source / drain load. In addition, in the conventional method, the method of reducing the gap wall and forming a shallow junction source / f pole is more used to solve the short channel effect, but this method is easy to make the j-plane source / drain on the Metal silicide layer produces unacceptable junction leakage. Therefore, the object of the present invention is to provide a method for semiconductor devices with a junction and junction to reduce the source == junction = = = ΐ to provide a recessed formation Source " and extremely shallow, 'so that the junction of the source " and the pole can avoid problems such as short-channel effects and junction leakage. Element-type source / drain junction semiconductor gate structure, 苴 / middle gate, substrate, and then a silicon oxide cap is formed on the top of the gate structure. 9) 66twi.plc] 565876 V. Description of the invention (3) Afterwards, a gap wall is formed on the side wall of the gate structure, and the f cap layer is oxidized and the gap wall is an etching mask to form a ▲ opening on the base of both sides of the gap wall. Next, a germanium silicide layer (h-xGex) is formed in the shallow opening to serve as a shallow junction source / drain. Among them, the method for forming germanium silicide is to use a rapid thermal rhenium chemical vapor deposition method (RTCVD), a reaction gas system used in ^ 1 rapid thermal process chemical vapor deposition method: i2H6 / GeH4 mixed gas or SiH2Cl2 / GeH4 mixed gas. This = also includes adding W in the process of forming a staggered layer of lithium, so that the purpose of activating the germanium layer can be achieved at the same time when germanium is formed, and the impurities of the germanium silicide layer can be subsequently tempered. Steps of activation. After that, the present invention forms a metal silicide layer on the germanium silicide source / drain, so as to reduce the resistance value of / J and the electrode. In addition, the present invention can also first remove the gate and, after the cap layer is removed, a metal silicide layer is formed on the gate structure and the source // and the electrode at the same time. First, the present invention proposes a method for forming a recessed source / drain junction. The 2 :: method is firstly provided-a substrate, and then formed on the substrate-using p / rJ 冓. After that, a gap wall is formed on the side wall of the gate structure, and Libi is wide-screened to form a single screen in the base on both sides of the gap wall = two shifts two I "step, formed in shallow opening °-Shi Xihua Staggered layer) In order to form this silicon oxide germanium electrode, at the same time, on the top of the gate structure, the manufacturing process and:... The method of forming the germanium silicide layer is to use a rapid ... Phase deposition method (RTCVD), and used in the rapid thermal, trapped phase deposition method-the reaction gas system is Si2H6 / GeH4 1 565876 V. Description of the invention (4) Bulk or 3 丨 1 ^ (: 12/66114 of Mixed gas. Add b2 h6 in the process of germanium layer. In this way, 'Ming also includes the purpose of forming silicidation to activate germanium silicide layer, and the subsequent step of tempering activation can be achieved at the same time when germanium silicide is formed. Then, this second: In order to eliminate the surface of the impurity electrode of the germanium silicide layer and the gate junction formed if is included in the germanium silicide source / drain-metal fossil compound I, thereby reducing the resistance value of the surface of the germanium silicide layer by several millimeters. A method for forming a recessed source / square φAa ^ and a semiconductor device with a pole junction, because of its Replace the conventional source formed by the ion implantation method with a material with better conductivity ^ ^ ^ ^ X ^ ^ ^ ^ ^ ^ X ^ ^ from 7 / and the polar region, so it can effectively reduce the source / Drain resistance value. According to the method for forming a semiconductor device with a recessed source / drain junction in the present invention, the source / drain junction formed with germanium silicide can be shallow, so short channels can be avoided. Effect, and leakage at the interface. The method for forming a semiconductor device with a recessed source / drain interface can effectively improve the reliability of the source / drain interface, thereby improving the reliability of the entire component. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Symbols of the drawings: 100, 200: Substrate 1 0 2, 2 0 2: thin oxide layer 104, 2 0 4 • polycrystalline stone layer 102a, 202a: gate oxide layer

565876 V. Description of the invention (5)-~-^ 1 04a, 204a · · Gate conductive layer 1 0 · Light · Dopant> and pole region 1 1 0, 2 0 8: Gap wall I 1 2: Source Electrode / Drain Region II 4, 2 1 4: Metal silicide layer 206: Dielectric layer 206a: Top cap layer 210 ... Openings 212, 212a: Selective thin film FIGS. 2A to 2G of the first embodiment, which A schematic diagram of a semiconductor device for forming a recessed source / drain junction according to the present invention is shown. w ® Buchuan 9 Please refer to FIG. 2A. First, a thin hafnium oxide 202, a conductive layer 204, and a dielectric layer 206 are formed on a substrate 200. Among them, the material of the conductive layer 2 is, for example, polycrystalline silicon or other materials suitable for use as a gate conductive layer ', and the material of the dielectric layer 206 is, for example, TEOS. Then, referring to FIG. 2B, a lithographic etching process is performed on the pattern layer 206, the conductive layer 204, and the thin oxide layer 202 to form a cap layer 1, 206a, a gate conductive layer 204a, and A gate oxide layer 202 &, a gate structure. Fu Chengyi Then, please refer to FIG. 2c, a gate wall 208 is formed on the side wall of the gate structure. In the middle, the partition wall 208 is formed by a low pressure chemical vapor deposition method (LPCVD) and an anisotropic etching process, which means the partition wall is formed.

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565876 V. Description of the invention (6) 208 The method is to first form a conformal dielectric layer on the substrate 200 by a low pressure chemical vapor deposition method to cover the capping layer 2 6 a, and then use non-isotropic etching to make the private layer. This conformal dielectric layer is etched back to form a spacer 208. Here, the material of the partition wall 208 is, for example, silicon nitride or silicon oxide. Next, please refer to FIG. 2D, the top cover layer 2 06a and the partition wall 2 0 8 are used as the mask, and the bases 2 on both sides of the partition wall 2 0 8 are patterned to form the opening 2 1 0 . Among them, the method of patterning the substrates on both sides of the spacer wall 08 to form the opening 2 10 is, for example, an anisotropic etching process, and one of the reaction gases used in this anisotropic etching process is, for example, six Sulfur fluoride (SF 6). After that, referring to FIG. 2E, a selective thin film 212 is formed in the opening 21o as a source / drain of the semiconductor device. In other words, the source / drain 2 12 is formed by digging out the opening 2 丨 0 in the substrate 2000, and then forming the selective film 212 in the opening 2 j 0. Therefore, this type of source / drain: only two Λ trapped source / non-polar. It is worth mentioning that this selective thin T is only :: formed on the material of Shi Xi ', and will not be formed on dielectric materials such as Shi Xixi. You, the niche from @ T 破 页 盍 层 2〇6a and The partition wall 208 is covered, so the selective film 212 will only grow in the opening 21o. (Si selective film 212 is-Shi Xihua staggered layer (ο 12 u Θχ) to form fragmented staggered layer 212, and 17 丨 "« chemical vapor deposition method, and this rapid thermal process The reaction gas is, for example, a mixed gas of Si2H6 / GeH4 or a two-reaction gas. In addition, the temperature of the mixed layer 2 1 2 is chemical vapor deposition by a rapid thermal process, and the temperature of the mixed layer 2 12 is, for example, about 500 degrees Celsius, and germanium Torr. Moreover, the pressure is, for example, 1 to 2565565. V. Description of the invention (7) Since the germanium silicide layer 2 of the present invention 2 is formed by a rapid hafnium: product method at low temperature (about 500 degrees Celsius), Because of this: the profile of the source electrode of the household = and the electrode junction will show a nearly perfect steep feed./ In addition, if B2He is added during the formation of the germanium silicide layer 212, the germanium layer 21 2 will At the same time, the germanium silicide layer 2 丨 2 can achieve the effect of enhancing activation / (Enhanced ACtivati0n), so that the subsequent step of impurity tempering activation of the germanite layer 212 is not required. Then, the present invention uses Controlling the concentration of germanium in the Shixihua, so as to reduce its band gap and thus reduce the source / drain resistance Here, it is particularly worth mentioning that because the resistance value of germanium silicide is generally lower on the semiconductor silicon substrate, and as mentioned above, by adjusting the concentration of germanium silicide, the band gap can be reduced to achieve a reduction. The purpose of its resistance value. Therefore, the depth of the source / drain junction of the present invention can be made shallow to avoid short-channel effects and leakage problems at the junction. This means that when the opening 210 is formed, the opening 21 can be removed. The depth is shallow, and after the subsequent formation of the Shixihua staggered layer in the opening 21 as the source / drain, the problems of short channel effect and junction leakage can be avoided. Then, please refer to FIG. 2F. A metal silicide layer 214 is formed on the electrode / drain 212, so as to reduce the resistance value of the source / drain. In the present invention, if the spacer 208 is made of nitride material, the top cover can be firstly covered. After the layer 2 0 a is removed, a metal silicide layer 21 4 (as shown in FIG. 2G) is formed on the gate conductive layer 2 04 a and the source / drain 212 at the same time, and a metal silicide is formed. The method of layer 2 1 4 is, for example, formed before the substrate 200 A metal layer, and then a thermal process is performed to make the metal layer react with silicon to form self-w 9166twf.ptd page 11 565876

V. Description of the invention (8) A quasi-metallic oxide material layer is formed. In this example, 『a a ^ Conventional Example』 metal silicide layer 2 1 4

Material: For example: CoSix or Nickel (N Second Embodiment x Figures 3A to 3D), the number of examples of which is ππ * ′,, It is not a schematic diagram of another preferred implementation according to the present invention. The flow section 202 of the semiconductor device with the source / non-electrode junction is shown in the figure and referenced. First, a thin oxide layer is formed on the substrate 200. 2 ° 4. Among them, the material of the conductive layer is, for example, 26H, which is suitable for use as an interfacial conductive layer, and the material of the dielectric layer ZUb is, for example, TE0S—Stone Oxide. After 204 / „According to 3BSI A conductive etching layer 202 ′ is patterned by a lithographic etching process to form a gate conductive layer and a: 丄: —02a to form a gate structure. Then, the second structure of the gate structure is formed. The partition wall 208. The material of the partition wall 208 is, for example, nitrogen or stone oxide. The method for forming the partition wall 208 is the same as the method of the first embodiment, and is not repeated here. Next, please refer to 3C. In the figure, the partition wall 208 is used as an etching mask, and the substrates 20 on both sides of the partition wall 208 are patterned to form an opening. 21〇. Since there is no etching mask over the gate conductive layer 204a, during this etching step, part of the thickness of the gate conductive layer 204a may be removed at the same time. Among them, the opening 2 1 0 is formed. The method is, for example, an anisotropic etching process, and one of the reaction gases used in the anisotropic etching process is, for example, sulfur hexafluoride (S F6). Afterwards, please refer to FIG. 3D, in the opening 2 1 0 Selectivity

imam Μ a

9166twf.ptd 565876 V. Description of the invention (9) 'The film 2 ^ 2 is used as a source / drain of a semiconductor element. At the same time, a selective thin film 212a is formed on the surface of the exposed gate conductive layer 204a. In other words, the source / drain 2 12 is formed by digging the opening 2 丨 in the substrate 2000 and then growing a selective film 212 in the opening 210. In addition, although the gate conductive layer 2 0 4 a may be partially removed in the previous step, the selective film 2 12 a may also be formed on the gate conductive layer 20 ″ so it can be replaced The thickness of the gate conductive layer 2 0a that was lost previously. In this embodiment, the selective films 212 and 212a are a germanium silicide layer (ShxGex). The method for forming the germanium silicide layers 212 and 212a is, for example, a rapid thermal process. A chemical vapor deposition method, and one of the reaction gases of the rapid thermal process chemical vapor deposition method is, for example, a Shl / GeH4 mixed gas or a SiHgClg / GeH4 mixed gas. In addition, a rapid thermal process chemical vapor deposition method is used to form Shi Xi The temperature of the germanium silicide layers 212 and 212a is, for example, about 500 ° C and the pressure is, for example, 20 Torr. Since the germanium silicide layer 2 1 2 of the present invention uses a rapid thermal process chemical vapor deposition method at a low temperature, (Approximately 500 degrees Celsius), so the profile of the formed source / drain junction will show almost perfect steepness. In addition, if b2h6 is added during the formation of the germanium silicide layers 212, 212a, When forming germanium silicide 212, 212a, At this time, the germanium silicide layers 212 and 212a can achieve the effect of enhanced activation. In this way, the subsequent step of impurity tempering activation of the germanium silicide layers 212 and 212a is not necessary. Furthermore, the present invention can be used to control silicide The germanium concentration of germanium reduces the band gap and thereby reduces the source / drain resistance. It is particularly worth mentioning here that the resistance value of germanium ε is relatively low.

^ 166twf.pt d

565876 V. Description of the invention (10) Generally, the resistance value of semiconductor silicon substrate is lower, and as mentioned above, by adjusting the concentration of germanium in fossilized germanium, the band gap can be reduced and the resistance value can be reduced. Therefore, the depth of the source / drain junction of the present invention can be made shallow to avoid the problems of short channel effects and junction leakage. This means that the depth of the opening 2 10 can be made shallow when the opening 2 10 is formed, and after a germanium silicide layer is formed in the opening 2 10 as a source / drain, the short channel effect and the connection can be avoided. Surface leakage problem. Next, referring to FIG. 3E, a metal silicide layer 2 1 4 is formed on the surfaces of the selective films 212 and 212a, thereby reducing the resistance value of the device. The method for forming the metal silicide layer 214 is, for example, forming a metal layer on the substrate 200, and then performing a thermal process to react the metal layer with silicon to form a self-quasi-metal silicide layer. In this embodiment, the material of the metal silicide layer 214 is, for example, cobalt silicide (coSix) or nickel silicide (Nδδ). Due to the semiconductor element of the present invention, the source / drain 2 1 2 is replaced with a silicide material instead of the source / drain region formed by the ion implantation method, and because germanium silicide has better conductivity, Therefore, the resistance value of the formed source / drain electrode 21 2 can be effectively reduced, thereby solving the problem that the resistance value of the source / drain electrode will increase after the component size is reduced. In addition, since the germanium silicide has better conductivity, the interface between the source / drain electrodes 2 and 2 of the present invention can be made shallow, so as to avoid the problems of short channel effect and leakage at the interface. In this way, the source / drain 2 1 2 interface can be increased to blame, and the guilty degree of the ancient needle 7 soil drinking is returned, and then the sin of the entire component is raised. Furthermore, the source / drain is formed due to the present invention. The method of non-polarity is to use the rapid production of low temperature conditions. 彳 ^ 朽 /% 99 · ^ & Γ Learn the rolling facies deposition method, so the formation of the source electrode 7 and electrode 212 will be popular. Presents almost perfect encounters, and if

565876 V. Description of the invention (11) Adding B2 H6 in the process of forming germanium silicide can further eliminate the impurity tempering activation step of germanium silicide, thereby simplifying the manufacturing process. To sum up, the present invention has the following advantages: 1. The method for forming a semiconductor device with a recessed source / drain junction according to the present invention can effectively reduce the resistance value of the source / drain. 2. The method for forming a semiconductor device with a recessed source / drain junction according to the present invention can avoid problems such as short channel effects and junction leakage. 3. The method for forming a semiconductor device with a recessed source / drain interface according to the present invention can effectively improve the reliability of the source / drain interface and the reliability of the entire device. Zhinan Although the present invention has been disclosed as above with a preferred embodiment, 1 restricts the person who is familiar with this art without departing from :; within the scope and scope of the Ming, there can be some changes and retouching, so this The spiritual scope of ^ shall be determined by the scope of the attached patent application. * Protection of Ming

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Claims (1)

565876 VI. Method of applying for patent scope Two methods for forming a semiconductor element with a recessed source / and electrode junction provide a substrate; forming a gate structure on the substrate is formed with a cap layer; wherein the closed-pole structure A top wall forms a gap on the side wall of the delta gate structure; an opening is formed in the base on both sides of the cover with the capping layer and the gap wall; and an opening is formed in the opening early in the gap wall Selective thin 2. As in the scope of patent application]: operation / one source / non-polar. Method of junction semiconductor device, 1 ;;: recessed source / drain includes-fast; process chemical vapor phase = (=) selective thin film junction semiconductor device: item J2: described in formation of depression Source / Drain 4. The square-shaped junction of the semiconductor device as described in the first item of the patent application & tapping recessed source / drain offset). Wherein, the thin film includes a lithography. 5. As described in the application for the scope of the patent application No. 4 of the semiconductor elements of the Fang Weiyu concave ^ source electrode and the method of Si H / r ΓΓ method, wherein One reaction body of the germanium silicide layer includes a mixed gas of Sl2H6 / GeH4 or a mixed gas of ~ / 〜. 6. The formation of a recessed source / drain as described in item 5 of the patent application 9166twf.ptd page 17 565876 A method for joining semiconductor devices in the scope of a six-patent application, wherein the reaction gas further includes adding B2H6. 7. The method for forming a semiconductor device with a recessed source / drain junction as described in item 1 of the scope of patent application, wherein the source / drain is a shallow junction source / drain. 8. The method for forming a semiconductor device with a recessed source / drain junction as described in item 1 of the scope of patent application, further comprising forming a metal oxide layer on the source / drain. 9. The method for forming a semiconductor device with a recessed source / drain junction as described in item 8 of the scope of the patent application, wherein the metal silicide layer includes a CoSix layer or a NiSix layer ). The pole is connected to one side. The material of the recessed source / dip wall as described in Fengshen // Λ Fanmu item 1 is the same or different. Method, =. Includes a semiconductor element forming a recessed source / drain junction to provide a substrate; forming a gate toast on the substrate, forming a capping layer; "" * eight The top of the gate structure is on the side of the gate structure, and an opening is formed in the base with the cap layer and the gap wall on both sides of the wall, so that the gap is in the opening in the gap. Forming a selective film to remove the capping layer, exposing that the gate electrode j is a source / drain; and a structure; and 9166twf.ptd page 18 565876 6. Scope of patent application --- at the gate A metal silicide layer is formed on the source structure and the source / drain. 1 2 · The method for forming a recessed source / inverted semiconductor device as described in item 11 of the scope of patent application, wherein the method for forming the selective thin film includes a rapid thermal process chemical weather deposition method (RTCVD). 1 3 · The method for forming a recessed source / drain junction semiconductor device as described in item 12 of the scope of patent application, wherein the temperature for performing the rapid thermal process chemical vapor deposition method is 500 degrees Celsius And the pressure is 1 ~ 20 to Torr ° 1 4 · The method for forming a semiconductor device with a recessed source / drain junction as described in item 11 of the scope of patent application, wherein the selective film includes a stone eve Germanium layer (SiwGex). 1 5 · The method for forming a semiconductor device with a recessed source / non-electrode junction as described in item 14 of the scope of the patent application, wherein one of the reaction gases for forming the petrochemical germanium layer includes 8 丨 2} 16 / 〇 6114 mixed gas or 3 丨 112 (: 12 / (^ mixed gas. 1 6) The method for forming a semiconductor device with a recessed source / drain junction as described in item 15 of the patent application scope, wherein The reaction gas includes adding B2H6. 1 7 · The method of forming a recessed source / deposited semiconductor device as described in item 11 of the patent application scope, wherein the source / drain is a Shallow junction source / drain. 1 8 · The method for forming a recessed source / drain junction semiconductor device as described in item 丨 丨 of the patent application scope, wherein the metal silicide layer includes a 1 ill ill I IS _ ill 9166twf.ptd Page 19 565876 VI. Scope of patent application Shi Xihua starting layer (CoSix) or a nickel silicide layer (Nis [1 9 · as in the scope of patent application] item] 'pole connection The surface of the semiconductor element is too soil, ^ The material of the heart-shaped recessed source / dip wall is not the same The material of the capping layer and the space 20. A method of forming a recessed source / drain method, including a semiconductor device providing a substrate; forming a gate structure on the substrate; and forming a gate structure on the substrate A gap wall is formed on the side wall of the structure; an opening is formed in the gap wall as a slanting plate; and a mask is engraved ... The bases on both sides of the gap wall form a selectivity in the opening The thin film is used as a semiconductor device, and at the same time, the gate electrode company is exposed at the same time. The semiconductor device is formed as a recessed source / drain: as described in the patent application, please refer to item 20 of the patent scope. A method for forming the selective thin film / including a rapid thermal process chemical vapor deposition (RTcvd). 2 2 · Forming a recessed source / dip junction as described in item 21 of the scope of patent application The method of semiconductor device, wherein the temperature of performing the rapid thermal process chemical vapor deposition method is 500 degrees Celsius, and the pressure thereof is 1 to 20 T0rr 02. Said semiconductor element forming a recessed source / non-electrode interface Method, wherein the selective film includes a germanium silicide layer (SiHGex) C) 166twf • Ptd m page 20 565876 Scope of patent application 24. The method for forming a semiconductor device with a recessed source / drain junction as described in item 23 of the scope of patent application, wherein one of the reactant gases forming the germanium layer includes a Si2H6 / GeH4 mixed gas or SiH2C1 "Mixed gas of GeH4. 2 5 · The method for forming a semiconductor device with a recessed source / electrode junction as described in item 24 of the scope of patent application, wherein the $ Hai reaction gas further includes the addition of B2H6. 2 6. The method for forming a recessed source / and-junction semiconductor device as described in item 20 of the scope of patent application, wherein the source / drain is-shallow junction source / non-electrode. 27. The method for forming a recessed source / inverted semiconductor device as described in item 20 of the scope of patent application, further comprising forming a metal oxide layer on the surface of the selective film. 28. The method for forming a recessed source / deposited semiconductor device as described in item 27 of the scope of the patent application, wherein the metal silicide layer includes a cobalt silicide layer (CoSix) or a nickel silicide layer ( NiSix). 9166twf.ptd Page 21