CN102110612A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102110612A CN102110612A CN2009102441332A CN200910244133A CN102110612A CN 102110612 A CN102110612 A CN 102110612A CN 2009102441332 A CN2009102441332 A CN 2009102441332A CN 200910244133 A CN200910244133 A CN 200910244133A CN 102110612 A CN102110612 A CN 102110612A
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device and the manufacturing method have the following beneficial effects: an N-FET (field effect transistor) with source and drain regions with side walls sunk relative to the upper surface of a substrate is formed and materials with tensile stress property are directly formed in contact holes above the source and drain regions, thus ensuring the tensile stress to be applied to a channel region while the property of the channel of the N-FET is improved; later, a pseudo gate layer in a gate stack of the N-FET is removed to further reduce the reaction force of the gate stack on the channel region, thus improving the tensile stress of the channel region, improving the mobility of the carrier and improving the properties of the device; and the properties of the semiconductor device with smaller channel region size can be obviously improved.
Description
Technical field
The present invention relates to improve the manufacture method of N-FET transistor device performance, more specifically, the present invention relates to improve the mobility of charge carrier rate by causing the stress changes of channel region by strain engineering.
Background technology
Along with development of semiconductor, have more high-performance and the bigger component density of more powerful integrated circuit requirement, and between each parts, element or size, size and the space of each element self needs also further to dwindle.
Yet, when the size of integrated circuit component is dwindled, damaged the constant material behavior and the physical effect of transistor and the running of other elements inevitably.Therefore, a lot of new innovations have been carried out in transistorized design, so that suitable level is arrived in the property retention of these elements.
Keeping the key factor of performance in the field-effect transistor is carrier mobility, under the voltage condition that applies on the grid of and channel isolation next by extremely thin gate medium, carrier mobility can influence the electric current or the quantity of electric charge that flows in the doped semiconductor raceway groove.
Total known type and stress direction according to charge carrier, the mechanical stress in the channel region of field-effect transistor (FET) can improve or reduce the mobility of charge carrier rate significantly.In FET, tension stress can improve electron mobility, reduces hole mobility, can advantageously improve the performance of N type FET transistor (N-FET); And compression can improve hole mobility, reduces electron mobility, can advantageously improve the performance of P type FET device (P-FET).Having proposed a large amount of structure and materials in the prior art is used for comprising pulling force or pressure at semi-conducting material, for example have in the mosfet transistor of stress silicon raceway groove existing, the mode that produces stress usually is to be coated with the stress induction layer in transistorized channel region, source electrode and drain region.
Though this mode has increased the stress of semiconductor device to a certain extent, along with reducing of present dimensions of semiconductor devices, corresponding channel region also reduces thereupon.Therefore, when stress material expands, for source electrode that is applied to the channel region both sides and/or drain region stress material, the stress of its corresponding increase is very limited, thereby can not improve mosfet transistor well, especially the transistorized performance of N-FET, like this, the performance of its corresponding COMS circuit that constitutes is also correspondingly relatively poor.
Summary of the invention
In view of the above problems, the invention provides a kind of semiconductor device and manufacture method thereof of improving the transistorized carrier mobility of N-FET that have, and then increase the stress of N-FET transistor channel region.
According to an aspect of the present invention, the manufacture method of the semiconductor device of the embodiment of the invention may further comprise the steps: form n type field effect transistor on substrate, described N-FET transistor comprise have gate dielectric layer, the grid of metal gate layer and dummy gate layer pile up and source area and drain region, wherein said source area and described drain region comprise the sidewall recessed with respect to described substrate top surface in the zone that contiguous described grid pile up; Cover the transistorized described source area of described N-FET, described drain region and described grid and pile up the formation contact etching stop layer; Form first pair of contact hole being positioned at above described source area and the described drain region in described contact etching stop layer respectively, the contiguous described grid of described first pair of contact hole pile up setting; In described first pair of contact hole, form material, apply tension stress described grid are piled up corresponding channel region with tension stress character; And remove described dummy gate layer, to improve the tension stress of channel region.
The further embodiment according to the present invention, described material with tension stress character is preferably tungsten.
The further embodiment according to the present invention, described recessed sidewall have one or more side that tilts with respect to described substrate top surface.The further embodiment according to the present invention forms described source area and described drain region with described recessed sidewall and comprises: the upper surface metallization medium layer of piling up at described substrate and described grid; Described dielectric layer and described substrate are carried out etching, to obtain side wall that described grid pile up and at the both sides of the described side wall sidewall recessed with respect to the upper surface of described substrate; And described recessed sidewall is carried out source electrode and drain ion respectively inject and anneal.
Further, can after the step that is removing described dummy gate layer, on described metal gate layer, form stressor layers or non-stressor layers.Forming under the situation of non-stressor layers, can be on described metal gate layer plated metal articulamentum, for example Al.Forming under the situation of stressor layers, can on described metal gate layers, deposit stressor layers with compression character, for example silicon nitride layer or TiAl layer are with the tension stress of further raising channel region.
Can cover further protective layer and the interlayer dielectric layer of forming in surface that described contact etching stop layer, described first pair of contact hole surface and described grid pile up; and second pair of contact hole that formation is communicated with described first pair of contact hole in described protective layer and interlayer dielectric layer; the contact material that deposition has tension stress character in described second pair of contact hole, for example tungsten.
According to an aspect of the present invention, the semiconductor device of the embodiment of the invention comprises: be formed on the n type field effect transistor on the substrate, described N-FET transistor comprises that the grid with gate dielectric layer and metal gate layer pile up and source area and drain region, and wherein said source area and described drain region comprise the sidewall recessed with respect to described substrate top surface in the zone that contiguous described grid pile up; Cover the transistorized described source area of described N-FET, described drain region and described grid and pile up the contact etching stop layer of formation; What form respectively in described contact etching stop layer is positioned at first pair of contact hole above described source area and the described drain region, and the contiguous described grid of described first pair of contact hole pile up setting; Be formed on the material in described first pair of contact hole, apply tension stress described grid are piled up corresponding channel region with tension stress character.
When forming described N-FET transistor, described grid pile up and also comprise the dummy gate layer that is formed on described metal gate layer top, and described dummy gate layer is removed behind the material that forms described tension stress character, to improve the tension stress of channel region.
The present invention at first forms source, the drain region with recessed sidewall, and directly form material in the contact hole above the transistorized source area of N-FET, drain region respectively with tension stress character, thereby guaranteeing that the N-FET transistor has under the situation that the junction current of the short-channel effect of minimizing, minimizing leaks, and applies bigger tension stress to the transistorized channel region of N-FET.And the step of the dummy gate layer in piling up in conjunction with follow-up removal N-FET transistor device grid, the reaction force that grid are piled up channel region further reduces, thereby can under the situation of less dimensions of semiconductor devices and channel dimensions, further increase the tension stress of channel region, improve the mobility of charge carrier rate, significantly improve the performance of device.
Especially, can in grid pile up, remove in the zone of dummy gate layer and further deposit stressor layers, with the tension stress of further raising channel region with compression character.
In addition, by the second pair of contact hole that is communicated with and wherein deposits tension stress character contact material with first pair of contact hole is set, the stress of N-FET transistor channel region be can increase further, thereby carrier mobility and its performance of corresponding raising of this device significantly improved.
Description of drawings
Fig. 1-10 shows the schematic sectional view of the different phase that the semiconductor device with n type field effect transistor device of the embodiment of the invention makes.
Embodiment
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.Should be noted that the not necessarily drafting in proportion of illustrated in the accompanying drawings parts.The present invention has omitted description to known assemblies and treatment technology and technology to avoid unnecessarily limiting the present invention.
To Figure 10, will provide detailed description below with reference to Fig. 1 to the manufacture method of the semiconductor device of the embodiment of the invention.
At first with reference to figure 1, Fig. 1 shows according to the transistorized schematic diagram of fabrication technology of the n type field effect transistor of the semiconductor device of the embodiment of the invention (N-FET).
In this technology, utilize known treatment technology to form the N-FET transistor, at first on substrate 200, form the N-FET transistor.
As shown in Figure 1, at first the grid that form gate dielectric layer 208, metal gate layer 210 and dummy gate layer 212 on substrate 200 pile up, the upper surface metallization medium layer 215 of piling up then at the grid that comprise above-mentioned layer, and piling up metallization medium layer 217 on the substrate 200 of both sides at grid, dielectric layer 215,217 for example is a nitride layer here.
Especially as shown in Figure 1, can form isolated area in Semiconductor substrate 200, for example shallow trench isolation is from (STI) structure 214, so that electricity is isolated continuous FET device.
Above channel region 204, form grid and pile up 206, for example, at first on substrate 200, form gate dielectric layer 208, can form by depositing high k material, for example HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, the thickness of gate dielectric layer 208 is approximately 2-10nm.Then on gate dielectric layer 208, form metal gate layer 210, for example by depositing for example TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
xForm, thickness is approximately 2-10nm.On metal gate layer 210, form dummy gate layer 212, for example form dummy gate layer 212 by deposition Poly-Si, Poly-SiGe.
Then, the grid that form in gate dielectric layer 208, metal gate layer 210 and dummy gate layer 212 pile up 206 total surface deposition dielectric layer 215, for example nitride.With reference to figure 2, Fig. 2 shows that the dielectric layer 215 to Fig. 1 deposition carries out patterning, for example by reactive ion etching (RIE), piles up 206 side wall 216 thereby form grid.Side wall 216 can for but be not limited to nitride material, can form by the method for formation side wall well known in the art.
In addition, by grid pile up the dielectric layer 217 of both sides and the substrate 200 of below carries out crystallographic etch technology to being positioned at, for example RIE etching, thereby form source area and the drain region recessed sidewall 202 ' and 203 ' recessed with respect to substrate 200 upper surfaces, wherein recessed sidewall 202 ' and 203 ' has one or more sides that tilt about substrate 200 upper surfaces, as shown in Figure 2, it also comprises and the parallel bottom surface of substrate 200 upper surfaces.
Then, recessed sidewall 202 ' and 203 ' corresponding region are carried out the source electrode of N-FET transistor corresponding types and drain ion respectively inject and anneal, thereby obtain having the source area 202 and the drain region 203 of recessed sidewall.
Wherein source area 202 and drain region 203 are contiguous and be positioned at grid and pile up 206 both sides, and channel region 204 is positioned at grid and piles up 206 corresponding below.
In the illustrated embodiment, carry out depositing operation simultaneously by pile up 206 upper surface at source area 202, drain region 203 and grid, thereby the dielectric layer 215 that forms stacking gate 206 side walls 216 forms in same processing step with the dielectric layer 217 that forms recessed sidewall 202 ' and 203 ', with simplified manufacturing technique.And, in same etch process to be deposited on grid pile up 206 and the both sides substrate on dielectric layer carry out etching, thereby obtain the recessed sidewall 202 ' and 203 ' of the side wall 216 of stacking gate 206 and source, drain region correspondence simultaneously.
Have about the recessed sidewall 202 ' of substrate 200 upper surfaces inclination and 203 ' source, drain region 202,203 by formation, can avoid the stretching area of undercutting source area 202 and drain region 204, reduce short-channel effect, reduce the junction current leakage, thereby improve the performance of device.
Particularly, crystallographic etch technology can be the dry ecthing and/or the wet etch process of any appropriate known in this field, in one embodiment, the recessed sidewall 202 ' of etching source, drain region correspondence and 203 ' technology can be carried out by one or more wet etching process, and this technology for example uses etching solution based on ammoniacal liquor, based on the etching solution of Tetramethylammonium hydroxide (TMAH), based on the etching solution of hydroxide, based on etching solution of vinylidene diphosphonic acid (EDP) or the like.
In one embodiment, at the surface deposition of substrate shown in Figure 1 200 and dummy gate layer 212 simultaneously or before successively forming the dielectric layer 215 and 217 of nitration case for example, can be at first at the thin metal level (not shown) of their surface deposition one deck, for example Ni or Co.Then, at cvd nitride layer again, and this device annealed, corresponding substrate 200 zones like this, chemical reaction takes place with the silicon substrate 200 that is positioned at its below in the metal level of deposition, thereby forms metal silicide, for example NiSi or CoSi2 at the device surface that metal level contacts with this; Corresponding dummy gate layer 212 zones, chemical reaction takes place with the polysilicon dummy gate layer 212 that is positioned at its below in the metal level of deposition, thereby forms metal silicide at the device surface that metal level contacts with this.
Like this, substrate 200 corresponding nitration cases 217 shown in Figure 1 are being carried out etching, to form recessed sidewall 202 ' and 203 ' shown in Figure 2, and the nitration case 215 that grid shown in Figure 1 pile up 206 top correspondences carried out etching, when removing responseless metal level, the metal silicide layer 218 that can corresponding be arranged in source area and drain region as shown in Figure 3 and be positioned at the dummy gate layer top then.
Corresponding recessed sidewall 202 ' and 203 ' metal silicide layer 218 can reduce to be formed in Semiconductor substrate 200 and the subsequent technique contact resistance between the metal material of contact hole.
Correspondence is positioned at the metal silicide layer 218 at dummy gate layer 212 tops, and for example the NiSi layer can play the effect that reduces resistance.
Then, as shown in Figure 4, the whole surface that the source area that comprises metal silicide layer 218, drain region and the grid that the covering above-mentioned steps forms pile up forms contact etching stop layer 220.Contact etching stop layer 220 can utilize depositing operation well known in the art to form, and for example can be but is not limited to nitride layer, and for example silicon nitride layer, and its deposit thickness can be about 10-100nm.
Then; as shown in Figure 5; can further deposit protective layer in the whole surface of contact etching stop layer 220, for example SiO2 layer 221 prevents the infringement that this PROCESS FOR TREATMENT is piled up grid to be used for follow-up chemico-mechanical polishing (CMP) technology, hereinafter will provide explanation in detail.In one embodiment, the thickness of the SiO2 layer 221 of deposition can be in the scope of 100-300nm.
Then as shown in Figure 6, form respectively in contact etching stop layer 220 and SiO2 layer 221 and be positioned at source area with recessed sidewall and first pair of contact hole 222 above the drain region, contact hole 222 contiguous grid pile up setting.Contact hole 222 can utilize the method for formation contact hole for example well known in the art, and for example reactive ion etching forms.In one embodiment, contact hole 222 can be arranged on apart from grid and pile up in the scope of about 10nm-50nm.
After this, as shown in Figure 7, in first pair of contact hole 222, form material respectively, thereby the channel region 204 of described N-FET device is applied tension stress with tension stress character.Be filled into material in first pair of contact hole 222 and can be but be not limited to tungsten with tension stress character.
Can use the method that contact hole is deposited well known in the art to form the stress contact and connect for example tungsten contact.For example, alternatively, can be in contact hole 222 depositing TiN layer (not shown) at first, then by chemical vapor deposition (CVD) deposits tungsten material on the TiN layer.At last the whole contact etching stop layer 220 and the SiO2 layer 221 that comprise first pair of contact hole 222 are carried out chemico-mechanical polishing (CMP), wherein CMP technology stops on the contact etching stop layer 220 of both sides in corresponding source, drain region, SiO2 layer 221 is removed fully by CMP like this, thereby form the stress contact 222 ' of a pair of tungsten, and expose dummy gate layer 212.By for example protective layer of SiO2 layer 221 is set, can prevent in carrying out the CMP technical process, especially when the polishing grid pile up contact etching stop layer 220 above in the of 216, excessive polishing and cause the damage that grid are piled up.
The effect of depositing TiN layer is as diffusion impervious layer, goes thereby stop the tungsten of subsequent deposition in contact hole 222 to be diffused in the silicon.
As shown in Figure 8, the dummy gate layer 212 that exposes is removed, to improve the tension stress of N-FET transistor channel region 204.Because the material of dummy gate layer 212 is polysilicon or polycrystalline silicon germanium material, therefore, it can for example pass through, and dehydrogenation etching gaseous mixture carries out.Because dummy gate layer 212 is removed, causes the reaction force of grid in piling up further to reduce, thereby further heightened the tension stress of channel region 204.
In addition as shown in Figure 9, selectively, deposit stressor layers in the zone that can corresponding dummy gate layer 212 removes on metal gate layers 210 or be non-stressor layers 224.Under the situation of deposition stressor layers, stressor layers can be to have the material that has counter stress with the material of affiliated filling contact hole, with the tension stress of further raising channel region.For example can deposit stress material, include, but are not limited to the silicon nitride of TiAl or compression etc. with compression character.Under the situation of the non-stressor layers of deposition, can be on metal gate layers 210 the plated metal articulamentum, the material of this metal connecting layer includes but not limited to Al.
Especially, selectively, as shown in figure 10, the surface and the grid that can cover contact etching stop layer 220, stress contact 220 ' pile up 206 surface formation protective layer 226 and interlayer dielectric layer 228.And form the second pair of contact hole that is communicated with first pair of contact hole 222 in protective layer 226 and interlayer dielectric layer 228, deposition has the contact material of tension stress character in second pair of contact hole then, thereby forms poroid stress contact 230.The contact material that deposits in second pair of contact hole can include but not limited to tungsten.
And, by forming first pair of contact hole 222 earlier, form second pair of contact hole again, and fill corresponding stress material respectively, so just can pass through two independently technology formation contact hole and Metal Contact, thereby advantageously avoid metal filled difficulty.
The present invention at first has source, the drain region of the recessed sidewall that tilts about substrate top surface by formation, reduce short-channel effect, reduces junction current and leaks, and improves the performance of device.And by directly respectively N-FET transistorized have in the source area of recessed sidewall, the contact hole above the drain region form material with tension stress character, when channel region is placed in tension stress following time, can improve the transistorized performance of N-FET.Thereby the transistorized channel region of N-FET is applied bigger tension stress.Then remove the dummy gate layer of the transistorized grid of N-FET in piling up,, thereby improve the tension stress of channel region, improve the mobility of charge carrier rate, improve the performance of device so that the reaction force that grid pile up channel region further reduces.Correspondingly, utilize the performance of the corresponding COMS circuit that constitutes of this method manufacturing N-FET transistor also can significantly improve.
Like this, the present invention avoids adopting independent stressor layers to improve the tension stress of N-FET transistor channel region, can significantly improve size of devices and performance under the situation of less dimensions of semiconductor devices and channel dimensions.
In addition, the present invention forms protective layer and interlayer dielectric layer by further on device, and forms the second pair of contact hole that is communicated with first pair of contact hole in protective layer and interlayer dielectric layer, the contact material that deposition has tension stress in described second pair of contact hole.So just can increase the stress in N-FET transistor respective channels zone further.
Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, claims of the present invention are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (35)
1. the manufacture method of a semiconductor device may further comprise the steps:
On substrate, form n type field effect transistor, described N-FET transistor comprise have gate dielectric layer, the grid of metal gate layer and dummy gate layer pile up and source area and drain region, wherein said source area and described drain region comprise the sidewall recessed with respect to described substrate top surface in the zone that contiguous described grid pile up;
Cover the transistorized described source area of described N-FET, described drain region and described grid and pile up the formation contact etching stop layer;
Form first pair of contact hole being positioned at above described source area and the described drain region in described contact etching stop layer respectively, the contiguous described grid of described first pair of contact hole pile up setting;
In described first pair of contact hole, form material, apply tension stress described grid are piled up corresponding channel region with tension stress character; And
Remove described dummy gate layer, to improve the tension stress of channel region.
2. manufacture method according to claim 1, wherein said material with tension stress character is a tungsten.
3. manufacture method according to claim 2, the step that wherein forms the material with tension stress character in described first pair of contact hole also comprises:
In described first pair of contact hole, form the TiN layer respectively;
The described tungsten material of deposition on described TiN layer; And
Described contact etching stop layer is carried out chemico-mechanical polishing to form the tungsten contact and to expose described dummy gate layer.
4. manufacture method according to claim 1, wherein said recessed sidewall have one or more side that tilts with respect to described substrate top surface.
5. according to claim 1 or 4 described manufacture methods, wherein form described source area and described drain region and comprise with described recessed sidewall:
The upper surface metallization medium layer of piling up at described substrate and described grid;
Described dielectric layer and described substrate are carried out etching, to obtain side wall that described grid pile up and at the both sides of the described side wall sidewall recessed with respect to the upper surface of described substrate; And
Described recessed sidewall is carried out source electrode and drain ion respectively to be injected and anneals.
6. manufacture method according to claim 1 also comprises:
After removing the step of described dummy gate layer, on described metal gate layer, form metal connecting layer.
7. manufacture method according to claim 6, the material of wherein said metal connecting layer comprises Al.
8. manufacture method according to claim 1 also comprises:
After removing the step of described dummy gate layer, on described metal gate layer, form stressor layers with compression character.
9. manufacture method according to claim 8, wherein said stressor layers are TiAl layer or silicon nitride layer.
10. manufacture method according to claim 1 also comprises:
Before the step that forms contact etching stop layer, form the step of metal silicide layer on the surface of described source area, surface, described drain region and described dummy gate layer.
11. manufacture method according to claim 10, wherein said metal silicide layer comprises: NiSi or CoSi
2
12. manufacture method according to claim 1, described first pair of contact hole forms at the described grid of distance piles up about 10-50nm place, both sides.
13. manufacture method according to claim 1 also comprises:
After formation has the step of material of tension stress character, described contact etching stop layer is carried out chemico-mechanical polishing, to expose described dummy gate layer.
14. according to claim 1,3 or 13 described manufacture methods, wherein said contact etching stop layer comprises nitride layer.
15. manufacture method according to claim 1 also comprises:
After removing the step of described dummy grid, cover surface formation protective layer and interlayer dielectric layer that described contact etching stop layer, described first pair of contact hole surface and described grid pile up;
In described protective layer and interlayer dielectric layer, form the second pair of contact hole that is communicated with described first pair of contact hole; And
The contact material that deposition has tension stress character in described second pair of contact hole.
16. manufacture method according to claim 15, wherein said protective layer comprises nitride layer.
17. manufacture method according to claim 15, wherein said interlayer dielectric layer comprises oxide skin(coating) or low-k materials.
18. manufacture method according to claim 15, wherein said contact material with tension stress character is a tungsten.
19. a semiconductor device comprises:
Be formed on the n type field effect transistor on the substrate, described N-FET transistor comprises that the grid with gate dielectric layer and metal gate layer pile up and source area and drain region, and wherein said source area and described drain region comprise the sidewall recessed with respect to described substrate top surface in the zone that contiguous described grid pile up;
Cover the transistorized described source area of described N-FET, described drain region and described grid and pile up the contact etching stop layer of formation;
What form respectively in described contact etching stop layer is positioned at first pair of contact hole above described source area and the described drain region, and the contiguous described grid of described first pair of contact hole pile up setting; And
Be formed on the material in described first pair of contact hole, apply tension stress described grid are piled up corresponding channel region with tension stress character.
20. semiconductor device according to claim 19, wherein described grid pile up and also comprise the dummy gate layer that is formed on above the described metal gate layer when forming described N-FET transistor, and described dummy gate layer is removed behind the material that forms described tension stress character, to improve the tension stress of channel region.
21. according to claim 19 or 20 described semiconductor device, wherein said material with tension stress character is a tungsten.
22. semiconductor device according to claim 20 also comprises:
Be respectively formed at the TiN layer between the material of described first pair of contact hole and described tension stress character; Wherein,
Form the tungsten contact and expose described dummy gate layer by described contact etching stop layer being carried out chemico-mechanical polishing.
23. according to claim 19 or 20 described semiconductor device, wherein said recessed sidewall has one or more side that tilts with respect to described substrate top surface.
24. semiconductor device according to claim 20 also comprises:
After removing described dummy gate layer, be formed on the metal connecting layer on the described metal gate layer.
25. semiconductor device according to claim 24, the material of wherein said metal connecting layer comprises Al.
26. semiconductor device according to claim 20 also comprises:
After removing described dummy gate layer, be formed on the stressor layers on the described metal gate layer with compression character.
27. manufacture method according to claim 26, wherein said stressor layers are TiAl layer or silicon nitride layer.
28. semiconductor device according to claim 20 also comprises:
Before forming contact etching stop layer, be formed on the metal silicide layer on described source area, surface, described drain region and described dummy gate layer surface.
29. semiconductor device according to claim 28, wherein said metal silicide layer comprises: NiSi or CoSi
2
30. according to claim 19 or 20 described semiconductor device, described first pair of contact hole forms at the described grid of distance piles up about 10-50nm place, both sides.
31. according to claim 19,20,22 or 28 described semiconductor device, wherein said contact etching stop layer comprises nitride layer.
32., also comprise according to claim 19 or 20 described semiconductor device:
Cover protective layer and interlayer dielectric layer that surface that described contact etching stop layer, described first pair of contact hole surface and described grid pile up forms;
Be formed on the second pair of contact hole that is communicated with described first pair of contact hole in described protective layer and the interlayer dielectric layer; And
Be deposited on the contact material in described second pair of contact hole with tension stress character.
33. semiconductor device according to claim 32, wherein said protective layer comprises nitride layer.
34. semiconductor device according to claim 32, wherein said interlayer dielectric layer comprises oxide skin(coating) or low-k materials.
35. semiconductor device according to claim 32, wherein said contact material with tension stress character is a tungsten.
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| CN103779321A (en) * | 2012-10-25 | 2014-05-07 | 联华电子股份有限公司 | Semiconductor structure with contact plug and formation method of semiconductor structure |
| JP2015103814A (en) * | 2013-11-26 | 2015-06-04 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Finfet semiconductor element and manufacturing method of the same |
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| CN103779321A (en) * | 2012-10-25 | 2014-05-07 | 联华电子股份有限公司 | Semiconductor structure with contact plug and formation method of semiconductor structure |
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| CN106206690A (en) * | 2014-12-19 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Semiconductor device with interconnection structure and forming method thereof |
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