CN102956452A - Method for manufacturing metal plugs during manufacturing of metal grids - Google Patents
Method for manufacturing metal plugs during manufacturing of metal grids Download PDFInfo
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- CN102956452A CN102956452A CN2011102380035A CN201110238003A CN102956452A CN 102956452 A CN102956452 A CN 102956452A CN 2011102380035 A CN2011102380035 A CN 2011102380035A CN 201110238003 A CN201110238003 A CN 201110238003A CN 102956452 A CN102956452 A CN 102956452A
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Abstract
The invention discloses a method for manufacturing metal plugs during manufacturing of metal grids. The method includes firstly, manufacturing a first metal plug which is flush with a substitute grid or lower than a metal grid, connecting the first metal plug to an active area of a CMOS(complementary metal-oxide-semiconductor transistor) device, taking the first metal plug as a CMP(chemical mechanical planarization) stop layer, subjecting a dielectric layer above the substitute grid to CMP to expose the substitute grid, removing the substitute grid, filling metal into the substitute grid to obtain the metal grid; secondly, manufacturing a second metal plug above the first metal plug and forming a metal plug unit by the first metal plug and the second metal plug; thirdly, manufacturing a metal plug unit above the metal grid according to the same process during manufacturing of the second metal plug so as to connect the metal grid to the external. The communication between the metal plug and the active area is guaranteed during manufacturing of the grid by the method in actual application.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of method of in making the metal gates process, making metal closures.
Background technology
At present, semi-conductor industry is growth of device on wafer (wafer) device side of silicon substrate mainly, for example, and CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device.Generally adopt now two trap CMOS techniques on silicon substrate, to make simultaneously the N-shaped channel mosfet that p-type NMOS N-channel MOS N field effect transistor (MOSFET) that conducting channel is the hole and conducting channel are electronics, concrete steps are: at first, zones of different in the silicon substrate is become respectively by mixing after (N-shaped) silicon substrate and (p-type) silicon substrate take the hole as majority carrier take electronics as majority carrier, between N-shaped silicon substrate and p-type silicon substrate, make shallow trench isolation from (STI) 101, then form respectively cavity type doped diffusion region (P trap) 102 and electron doping diffusion region (N trap) 103 in the STI both sides with the method for Implantation, then make successively the stacked grid that is formed by gate dielectric layer 104 and metal gate 105 in the wafer device side of P trap 102 and N trap 103 positions respectively, in P trap 102 and N trap 103, make respectively source electrode and drain electrode at last, source electrode and drain electrode are positioned at the both sides (not shown in FIG.) of stacked grid, in the P trap, form the N-shaped channel mosfet, in the N trap, form the p-type channel mosfet, obtain cmos device structure as shown in Figure 1.
The stacked grid of traditional oxynitrides/polysilicon, be with nitrogen oxide as gate dielectric layer, polysilicon is as grid.Along with the development of semiconductor technology, the cmos device of the stacked grid of oxynitrides/polysilicon can not satisfy the needs of small size semiconductor technology because the problem such as leakage current and power consumption be excessive.Therefore, proposed with high-dielectric coefficient (HK) material as gate dielectric layer, with the metal gates of metal material as metal gate.
Fig. 2 a～Fig. 2 d is prior art is made the embodiment of the method one of metal closures in making the metal gates process generalized section, wherein,
Shown in Fig. 2 a, form the cmos device structure according to the described process of Fig. 1 in Semiconductor substrate 11, this cmos device structure comprises replacement gate 22, source electrode and drain electrode (source electrode and drain not shown), on replacement gate 22, also have side wall 55, also have barrier layer 66 in this cmos device; The 66 surfaces deposition first medium layer 77 on the barrier layer;
Here, barrier layer 66 is titanium layer or titanium nitride layer, generally as etching stop layer;
Here, replacement gate also has the gate dielectric layer (not shown) of metal gates and employing HK material for 22 times;
Shown in Fig. 2 b, adopt chemical-mechanical planarization (CMP) mode that first medium layer 77 is polished, until barrier layer 66 stops, then removing replacement gate;
Shown in Fig. 2 c, at this cmos device surface deposition metal level 88, such as tungsten or aluminium lamination, fill the replacement gate zone, then adopt CMP to be etched to silicon nitride layer 66 and stop;
Shown in Fig. 2 d, make metal closures 99 on this cmos device surface;
When making, deposit exactly one deck dielectric layer after, adopt photoetching and etching technics after the metal closures zone makes through hole, adopts metal filled after, formation metal closures 99.When making through hole, with the barrier layer as etching stop layer;
In said process, in the described process of Fig. 2 b, sunk area can appear at dielectric layer, when subsequent figure 2c depositing metal layers 88, also can deposit to sunk area, make in metal closures 99 processes at 2d, if metal closures 99 just in time is positioned on the sunk area, just cause when making through hole, to be deposited on the metal level 88 of sunk area as etching stop layer, namely etch into sunk area and stop, causing the metal closures 99 of made can't connect the active region of this cmos device, cause final this cmos device of making to open circuit.
In order to overcome this problem, adopted another kind of method of in making the metal gates process, making metal closures, shown in Fig. 3 a～Fig. 3 c, particularly:
Shown in Fig. 3 a, form the cmos device structure according to the described process of Fig. 1 in Semiconductor substrate 11, this cmos device structure comprises replacement gate 22, source electrode and drain electrode (source electrode and drain not shown), also has side wall 55 on replacement gate 22, and this cmos device has barrier layer 66 is arranged; The 66 surfaces deposition first medium layer 77 on the barrier layer;
Here, barrier layer 66 is titanium layer or titanium nitride layer, generally as etching stop layer;
Here, replacement gate also has the gate dielectric layer (not shown) of metal gates and employing HK material for 22 times;
Shown in Fig. 3 b, make metal closures 99 at first medium layer 77;
In this step, adopt photoetching and etching technics after the metal closures zone makes through hole, adopts metal filled after, formation metal closures 99; When making through hole, with the barrier layer as etching stop layer;
Shown in Fig. 3 c, adopt the CMP mode that first medium layer 77 is polished, until silicon nitride layer 66 stops, then remove replacement gate, at this cmos device surface deposition metal level 88, such as tungsten or aluminium lamination, then filling replacement gate zone is adopted CMP to be etched to silicon nitride layer 66 and is stopped.
Because before employing CMP mode is polished first medium layer 77, made metal closures 99, and this metal closures 99 is connected the active region of this cmos device, do not make so the depression that causes when adopting CMP on first medium layer 77 etching can not affect metal closures, solved and adopted Fig. 2 a～described process of Fig. 2 d in making the metal gates process, to make the problem that metal closures produces.
But, also there is defective in Fig. 3 a～described process of Fig. 3 c, this be because, polish in the first medium layer in employing CMP mode, the metal closures that need to polish simultaneously the first medium layer and make, and the metal closures plane that guarantees first medium layer plane and made in polishing process is equal to, because the material of first medium layer and metal closures is different, employed polishing fluid is also different, so in polishing process, be difficult to guarantee that the metal closures plane of first medium layer plane and made is equal to, so Fig. 3 a～Fig. 3 c is just feasible in theory, but can't realize in practical application.
Summary of the invention
In view of this, the invention provides a kind of method of making metal closures in making the metal gates process, the method can guarantee in actual applications that the metal closures of made in making gate process is communicated with active area.
Technical scheme of the present invention is achieved in that
A kind of method of in making the metal gates process, making metal closures, the method comprises:
At the cmos device face deposition first medium layer of Semiconductor substrate, described cmos device comprises replacement gate;
Adopt photoetching and etching technics after the first medium layer forms the first contact hole, fill metal in the first contact hole, form the first sub-metal closures, the first sub-metal closures height is not higher than described replacement gate;
With the first sub-metal closures as polishing stop layer, polishing first medium layer, remove described replacement gate after, adopt the second metal level to fill described replacement gate zone;
Cmos device face in Semiconductor substrate deposits the second barrier layer and second medium layer successively, adopt photoetching and etching technics, take the second barrier layer as etching stop layer, after the second medium layer forms the second contact hole, in the second contact hole, fill the second metal level, after forming the second sub-metal closures, the described first sub-metal closures and the second sub-metal closures consist of metal closures.
Described the second barrier layer is silicon nitride.
Have the gate dielectric layer that adopts high dielectric constant material under the described replacement gate, described high dielectric constant material is hafnium oxide HfO2, hafnium silicon oxide HfSiO or hafnium silicon oxynitride HfSiNO.
The metal of filling in the first contact hole is tungsten or aluminium, fills metal in the first contact hole, forms the first sub-metal closures, and process is:
Behind first medium layer deposition the first metal layer, employing chemical-mechanical planarization CMP mode or dry etching mode are removed the first metal layer on the first medium layer, this the first metal layer is packed into the first contact hole, then the metal level in the first contact hole is carried out dry etching, etch into the height that is not higher than replacement gate, form the first sub-metal closures.
Described the second contact hole directly over described the first contact hole, described second metal level of in the second contact hole, filling, the process that forms the second sub-metal closures is:
Behind second medium layer deposition the second metal level, adopt CMP mode or dry etching mode, remove the second metal level on the second medium layer, this second metal level is packed into the second contact hole, forms the second sub-metal closures.
Adopt sulphur hexafluoride SF6 during described dry etching.
Described employing photoetching and etching technics take the second barrier layer as etching stop layer, after the second medium layer forms the second contact hole, are filled the second metal level in the second contact hole, when forming the second sub-metal closures, also comprise:
Adopt photoetching and etching technics, take the second barrier layer as etching stop layer, form the metal closures through hole that is communicated with metal gates at the second medium layer, at metal closures filling through hole second metal level of described connection metal gates, form the metal closures of metal gates.
Can find out from such scheme, method provided by the invention is in making the metal gates process, at first make contour with replacement gate or be lower than the first sub-metal closures of metal gates, this the first sub-metal closures is communicated with the active region of cmos device, then with this first sub-metal closures as the CMP stop-layer, the dielectric layer of CMP replacement gate top, after the exposed replacement gate, remove replacement gate, adopt metal filled replacement gate, obtain metal gates, belonging to beyond the Great Wall at the first interest again, the side makes the second sub-metal closures, the first sub-metal closures and the second sub-metal closures consist of metal closures, because before the employing CMP mode in making the metal gates process is polished the first medium layer take the first sub-metal closures as polishing stop layer, just made contour with metal gates or be lower than the first sub-metal closures of metal gates, so when adopting the CMP mode to polish the first medium layer, just polish the first medium layer, and can not be polished to the first sub-metal closures, so surface polishing can keep level, on the other hand, before employing CMP mode is polished the first medium layer, made the first sub-metal closures, and this first sub-metal closures is connected active region and the polishing of this cmos device and is carried out as stop-layer with this first sub-metal closures, does not make so the depression that causes when adopting CMP that the first medium layer is polished can not affect follow-up metal closures.And follow-uply when the first interest belongs to that the side makes the second sub-metal closures beyond the Great Wall, can not leave the space yet, in addition, when making the second sub-metal closures, above metal gates, make metal closures according to same technological process yet, be used for metal gates is communicated to the outside.Therefore, method provided by the invention guarantees that in actual applications the metal closures of made in making gate process is communicated with active area.
Description of drawings
Fig. 1 is the cmos device cross-sectional view of prior art;
Fig. 2 a～Fig. 2 d is prior art is made the embodiment of the method one of metal closures in making the metal gates process generalized section;
Fig. 3 a～Fig. 3 c is prior art is made the embodiment of the method two of metal closures in making the metal gates process generalized section;
Fig. 4 is a kind of method flow diagram of making metal closures in making the metal gates process provided by the invention;
Fig. 5 a～Fig. 5 f is a kind of process generalized section of making metal closures in making the metal gates process provided by the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The present invention also makes metal closures simultaneously when making the metal gates process, process is: make contour with replacement gate or be lower than the first sub-metal closures of metal gates, this the first sub-metal closures is communicated with the active region of cmos device, then with this first sub-metal closures as the CMP stop-layer, the dielectric layer of CMP replacement gate top, after the exposed replacement gate, remove replacement gate, adopt metal filled replacement gate, obtain metal gates, belong to the second sub-metal closures of side's making beyond the Great Wall at the first interest again, the first sub-metal closures and the second sub-metal closures consist of metal closures.
Like this, because before the employing CMP mode in making the metal gates process is polished the first medium layer take the first sub-metal closures as polishing stop layer, just made contour with metal gates or be lower than the first sub-metal closures of metal gates, so when adopting the CMP mode to polish the first medium layer, just polish the first medium layer, and can not be polished to the first sub-metal closures, so surface polishing can keep level, on the other hand, before employing CMP mode is polished the first medium layer, made the first sub-metal closures, and this first sub-metal closures is connected active region and the polishing of this cmos device and is carried out as stop-layer with this first sub-metal closures, does not make so the depression that causes when adopting CMP that the first medium layer is polished can not affect follow-up metal closures.And follow-up when the first interest belongs to the second sub-metal closures of side's making beyond the Great Wall, can not leave the space yet.
Therefore, method provided by the invention guarantees that in actual applications the metal closures of made in making gate process is communicated with active area.
Fig. 4 is a kind of method flow diagram of making metal closures in making the metal gates process provided by the invention, provided by the invention a kind of process generalized section of making metal closures in making the metal gates process in conjunction with shown in Fig. 5 a～Fig. 5 f is elaborated:
Step 401, form the cmos device structures in Semiconductor substrate 11, this cmos device structure comprises replacement gate 22, source electrode and drain electrode (source electrode and drain not shown), on replacement gate 22, also has side wall 55, in this cmos device, namely the cmos device surface has the first barrier layer 66; At the first barrier layer 66 deposition first medium layers 77, shown in Fig. 5 a;
In this step, the first barrier layer 66 is titanium nitride or titanium, adopts scheme same as the prior art, repeats no more here;
Here, replacement gate also has the gate dielectric layer (not shown) of metal gates and employing HK material for 22 times;
Here, replacement gate can only have the gate dielectric layer that adopts the HK material for 22 times, as the protection of the gate dielectric layer that adopts the HK material;
Here, the HK material is hafnium oxide (HfO2), hafnium silicon oxide (HfSiO) or hafnium silicon oxynitride (HfSiNO);
Here, replacement gate 22 is polysilicon;
In this step, contact hole 101 is used for follow-up making the first sub-metal closures, adopts photoetching and etching technics to form contact hole 101 in the zone that will form metal closures;
In this step, the metal material of the first metal layer 102 of deposition is tungsten or aluminium;
Adopt sulphur hexafluoride (SF6) when in this step, carrying out dry etching;
In this step, as polishing stop layer, carry out CMP with the first sub-metal closures, can guarantee that there is not the space in the metal closures of final made;
In this step, formed the second contact hole 105 when forming the second contact hole 105, adopts photoetching and etching technics above contact hole 101, and the second barrier layer 103 is as etching stop layer;
The process of filling the second metal level 106 at the second contact hole 105 is: at second medium layer 104 deposition the second metal level 106, then adopt CMP to be polished to the second barrier layer 103 and end;
In this step, the second barrier layer 103 is silicon nitride layer etc., exists as etching stop layer;
In this step, adopt SF6 during described dry etching.
In the described process of Fig. 4, in step 406, also comprise the metal closures process of making the metal gates top, this metal closures can be so that metal gates be communicated to the semiconductor device outside, and process is:
Adopt photoetching and etching technics, take the second barrier layer as etching stop layer, form the metal closures through hole that is communicated with metal gates at the second medium layer, at metal closures filling through hole second metal level of described connection metal gates, form the metal closures of metal gates.This process is shown in Fig. 5 f.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (7)
1. method of in making the metal gates process, making metal closures, the method comprises:
At the cmos device face deposition first medium layer of Semiconductor substrate, described cmos device comprises replacement gate;
Adopt photoetching and etching technics after the first medium layer forms the first contact hole, fill metal in the first contact hole, form the first sub-metal closures, the first sub-metal closures height is not higher than described replacement gate;
With the first sub-metal closures as polishing stop layer, polishing first medium layer, remove described replacement gate after, adopt the second metal level to fill described replacement gate zone;
Cmos device face in Semiconductor substrate deposits the second barrier layer and second medium layer successively, adopt photoetching and etching technics, take the second barrier layer as etching stop layer, after the second medium layer forms the second contact hole, in the second contact hole, fill the second metal level, after forming the second sub-metal closures, the described first sub-metal closures and the second sub-metal closures consist of metal closures.
2. the method for claim 1 is characterized in that, described the second barrier layer is silicon nitride.
3. the method for claim 1 is characterized in that, has the gate dielectric layer that adopts high dielectric constant material under the described replacement gate, and described high dielectric constant material is hafnium oxide HfO2, hafnium silicon oxide HfSiO or hafnium silicon oxynitride HfSiNO.
4. the method for claim 1 is characterized in that, the metal of filling in the first contact hole is tungsten or aluminium, fills metal in the first contact hole, forms the first sub-metal closures, and process is:
Behind first medium layer deposition the first metal layer, employing chemical-mechanical planarization CMP mode or dry etching mode are removed the first metal layer on the first medium layer, this the first metal layer is packed into the first contact hole, then the metal level in the first contact hole is carried out dry etching, etch into the height that is not higher than replacement gate, form the first sub-metal closures.
5. the method for claim 1 is characterized in that, described the second contact hole directly over described the first contact hole, described second metal level of in the second contact hole, filling, the process that forms the second sub-metal closures is:
Behind second medium layer deposition the second metal level, adopt CMP mode or dry etching mode, remove the second metal level on the second medium layer, this second metal level is packed into the second contact hole, forms the second sub-metal closures.
6. such as claim 4 or 5 described methods, it is characterized in that, adopt sulphur hexafluoride SF6 during described dry etching.
7. the method for claim 1 is characterized in that, described employing photoetching and etching technics, take the second barrier layer as etching stop layer, after the second medium layer forms the second contact hole, in the second contact hole, fill the second metal level, when forming the second sub-metal closures, also comprise:
Adopt photoetching and etching technics, take the second barrier layer as etching stop layer, form the metal closures through hole that is communicated with metal gates at the second medium layer, at metal closures filling through hole second metal level of described connection metal gates, form the metal closures of metal gates.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001891A1 (en) * | 2000-06-21 | 2002-01-03 | Kim Tae Kyun | Method for fabricating MOSFET device |
| US20030151098A1 (en) * | 2002-02-13 | 2003-08-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having dual-gate structure and method of manufacturing the same |
| US20080087966A1 (en) * | 2006-10-16 | 2008-04-17 | Sony Corporation | Semiconductor device and method for manufacturing same |
| CN102110612A (en) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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- 2011-08-18 CN CN201110238003.5A patent/CN102956452B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001891A1 (en) * | 2000-06-21 | 2002-01-03 | Kim Tae Kyun | Method for fabricating MOSFET device |
| US20030151098A1 (en) * | 2002-02-13 | 2003-08-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having dual-gate structure and method of manufacturing the same |
| US20080087966A1 (en) * | 2006-10-16 | 2008-04-17 | Sony Corporation | Semiconductor device and method for manufacturing same |
| CN102110612A (en) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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