CN202003995U

CN202003995U - Field effect transistor device with stress structure

Info

Publication number: CN202003995U
Application number: CN2011200341845U
Authority: CN
Inventors: 朱慧珑; 骆志炯; 尹海洲
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2011-01-31
Filing date: 2011-01-31
Publication date: 2011-10-05
Anticipated expiration: 2021-01-31

Abstract

The utility model discloses a field effect transistor device with stress structure includes: a semiconductor substrate having an NMOS region and a PMOS region; a source region and a drain region formed in the semiconductor substrate and belonging to the NMOS region and the PMOS region; a first channel region in the semiconductor substrate between the source and drain regions of the NMOS region and a second channel region between the source and drain regions of the PMOS region; a first gate stack over the first channel region of the NMOS region and a second gate stack over the second channel region of the PMOS region. The first gate stack includes a first gate dielectric layer and a first conductive gate layer thereon. The second gate stack includes a second gate dielectric layer and a second conductive gate layer thereon. The device further includes a third stress structure having a tensile stress property at a sidewall of the first gate stack and a fourth stress structure having a compressive stress property at a sidewall of the second gate stack. The field effect transistor device can improve the tensile stress of the NMOS device and the compressive stress of the PMOS device, thereby improving the performance of the device.

Description

FET device with stress structure

Technical field

The utility model relates to the FET device with stress structure, and more specifically, the utility model relates to by utilizing stress structure to improve the FET device of mobility of charge carrier rate to the channel region stress application.

Background technology

Along with development of semiconductor, have more high-performance and the bigger component density of more powerful integrated circuit requirement, and the size of each parts needs also further to dwindle.

Yet, when the size of integrated circuit component is dwindled, damaged the constant material behavior and the physical effect of transistor and other element work inevitably.Therefore, a lot of new innovations have been carried out in transistorized design, so that suitable level is arrived in the property retention of these elements.

Keeping the key factor of performance in the field-effect transistor is carrier mobility.Apply under the voltage condition on the grid of and channel isolation next by extremely thin gate medium, carrier mobility can influence the electric current or the quantity of electric charge that flows in the doped semiconductor raceway groove.

Know that according to the type and the stress direction of charge carrier, the mechanical stress in the channel region of FET can improve or reduce the mobility of charge carrier rate significantly.In the FET that raceway groove forms along 110 crystal orientation usually, the tension stress on source/drain region direction can improve electron mobility, reduces hole mobility, thereby advantageously improves the performance of NMOS; And the compression on source/drain region direction can improve hole mobility, reduces electron mobility, thereby can advantageously improve the performance of PMOS.Having proposed a large amount of structure and materials in the prior art is used for comprising pulling force or pressure at semi-conducting material.For example in US 2006/0160317, just proposed a kind of on the MOSFET device by the deposition stressor layers, and all or part of grid layer of etching optionally improves the scheme of the carrier mobility in the raceway groove.

Yet prior art changes the mobility of charge carrier rate by stressor layers or stress interface usually, this will be unfavorable for device size continue dwindle, and cause complicated manufacturing process.And along with the reducing of present dimensions of semiconductor devices, corresponding channel region also reduces thereupon.Therefore, when stress material expands, for source electrode that is applied to the channel region both sides and/or drain region stress material, the stress of its corresponding increase is very limited, thereby can not improve the performance of mosfet transistor (for example switch current ratio) well, the performance of the COMS circuit of corresponding formation is also correspondingly relatively poor.Therefore, need provide a kind of new semiconductor device, can improve the carrier mobility of the channel region of NMOS and/or PMOS device simultaneously, reduce size of devices, and simplified manufacturing technique.

The utility model content

In view of the above problems, the utility model provides a kind of FET device, and described device comprises: the Semiconductor substrate with nmos area territory and PMOS zone; Source area that belongs to the nmos area territory that in described Semiconductor substrate, forms and drain region and the source area and the drain region that belong to the PMOS zone; In described Semiconductor substrate, form at the source area in described nmos area territory and first channel region between the drain region, and at the source area in described PMOS zone and second channel region between the drain region; Second grid that described second channel region top in described PMOS zone is piled up and be positioned to the first grid that is positioned at described first channel region top in described nmos area territory pile up, and wherein, the described first grid is piled up and comprised: first grid dielectric layer; And first conductive gate layer on described first grid dielectric layer; Described second grid pile up and comprise: second gate dielectric layer; With second conductive gate layer on described second gate dielectric layer; Pile up the tertiary stress structure with tension stress character of sidewall in the described first grid; And the 4th stress structure with compression character of the sidewall that piles up at described second grid.

In addition, the utility model also provides a kind of n type field effect transistor device, and described device comprises: Semiconductor substrate; Source area that in described Semiconductor substrate, forms and drain region; The channel region between source area and drain region that in described Semiconductor substrate, forms; The grid that are positioned at described channel region top pile up, and wherein, described grid pile up and comprise: gate dielectric layer; With the conductive gate layer on described gate dielectric layer; And the stress structure that piles up sidewall at described grid with tension stress character.And a kind of p type field effect transistor device, described device comprises: Semiconductor substrate; Source area that in described Semiconductor substrate, forms and drain region; The channel region between source area and drain region that in described Semiconductor substrate, forms; The grid that are positioned at described channel region top pile up, and wherein, described grid pile up and comprise: gate dielectric layer; With the conductive gate layer on described gate dielectric layer; Pile up the stress structure with compression character of sidewall at described grid.

Device of the present utility model can be under the situation that device size continues to dwindle, and stress is applied to greatest extent in the raceway groove of nmos device and/or PMOS device to improve device performance.

Description of drawings

Fig. 1-15 shows the schematic sectional view according to the different phase of the FET device of an embodiment of the present utility model;

Figure 16 shows the flow chart according to the manufacture method of the field-effect transistor of an embodiment of the present utility model;

Figure 17-24 shows the schematic sectional view according to the different phase of the FET device of another embodiment of the present utility model; And

Figure 25 shows the flow chart according to the manufacture method of the field-effect transistor of another embodiment of the present utility model.

Embodiment

Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present utility model.Of the present utility model open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the utility model.In addition, the utility model can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and examples of material that the utility model provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.Should be noted that the not necessarily drafting in proportion of illustrated in the accompanying drawings parts.The utility model has omitted description to known assemblies and treatment technology and technology to avoid unnecessarily limiting the utility model.

As mentioned above, channel region is placed in tension stress following time, can improve the performance of n type field effect transistor (NMOS) device; And channel region is placed in compression following time, can improve the performance of p type field effect transistor (PMOS) device.In embodiment of the present utility model, preferably utilize the grid alternative techniques by forming formation second stressor layers in first stressor layers and the gap in the middle of the grid of PMOS pile up in the gap in the middle of the grid of NMOS pile up respectively; And after forming stressor layers, remove side wall that the grid of PMOS and nmos device pile up, and then the tension stress of lifting nmos device channel region and the compression of PMOS device channel region so that discharge described stress to channel region.Preferably, this first stressor layers has compression, and this second stressor layers has tension stress.More preferably, can pile up at the described grid of nmos device and PMOS device sidewall and part source area and drain region above form stress structure with counter stress character so that further improve the tension stress of nmos device and the compression of PMOS device.That is,, can deposit tertiary stress structure with tension stress character for nmos device; For the PMOS device, can deposit the 4th stress structure with compression character.By device of the present utility model, can under the situation that device size continues to dwindle, stress be applied to greatest extent in the raceway groove of nmos device and PMOS device, thereby improve device performance.

With reference to Figure 15, Figure 15 shows the structure chart according to the semiconductor device of embodiment of the present utility model.Described device for example can substitute with the side wall alternative techniques by grid and make.So-called grid alternative techniques is meant and forms dummy grid earlier, and described device carried out source/leakage is injected and source/leakage is annealed, leak doping with activation of source, after forming source area and drain region, remove described dummy grid and form the new grid that belong to nmos area territory and PMOS zone and pile up.So-called side wall alternative techniques is meant, the grid in described nmos area territory and PMOS zone pile up sidewall and form pseudo-side wall earlier, and remove described pseudo-side wall in due course, forms new structure according to the design needs of device.

To describe structure below in detail according to the semiconductor device of embodiment of the present utility model.Described device has the Semiconductor substrate 200 that comprises nmos area territory 202 and PMOS zone 204, and wherein said nmos area territory 202 is isolated by isolated area 206 mutually with described PMOS zone 204.

In the present embodiment, substrate 200 comprises the silicon substrate (for example wafer) that is crystal structure.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 200 can have various doping configurations.The substrate 200 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Perhaps, substrate 200 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 200 can comprise epitaxial loayer alternatively, can be by stress changes strengthening the property, and can comprise silicon-on-insulator (SOI) structure.

Schematically provide an isolated area 206 in the present embodiment, the device architecture with a plurality of isolated areas 206 can repeat according to the structural cycle that the utility model provides to form.In the present embodiment, isolated area 206 forms according to the conventional method in this area, can be for example to utilize photoetching technique to form mask on the surface of the device to be formed of Semiconductor substrate 200, and the opening etched substrate by mask is utilized SiO then to form groove ₂Dielectric material is filled this groove, as shown in Figure 1.

Described device also comprises source/drain region 214 that belongs to the nmos area territory and the source/drain region 217 that belongs to the PMOS zone, and the channel region 215 in the middle of described source area and drain region.Described source/drain region 214,217 can be injected n type or p type alloy or impurity and form to substrate 200 by the transistor arrangement according to expectation.Source/drain region 214 can be the Si:C that the N type mixes, and wherein C% is 0.2-2%.Source/drain region 217 can be the SiGe that the P type mixes, and wherein Ge is 20-70%.Source/drain region 214,217 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.Because the utility model can use the grid alternative techniques, so source electrode and drain electrode 214,217 are piled up prior to the grid in described NMOS and PMOS zone and are formed.Can utilize common semiconducter process and step, described device is carried out thermal annealing, to activate the doping in source electrode and the drain electrode 214,217.Thermal annealing can adopt the technologies that those skilled in the art knew such as comprising rapid thermal annealing, spike annealing to carry out.

Described device comprises that also the first grid that is formed on the described nmos area territory 202 is piled up and second grid that are formed on the described PMOS zone 204 pile up.The described first grid is piled up and is comprised first grid dielectric layer 232 and first conductive gate layer 234 on described first grid dielectric layer 232, preferably also comprises first stressor layers 236 in the gap of filling described first conductive gate layer 234 centres.Described second grid pile up and comprise second gate dielectric layer 226 and second conductive gate layer 228 on described second gate dielectric layer, preferably also comprise second stressor layers 230 in the gap of filling described second conductive gate layer 228 centres.Preferably, first stressor layers 236 has compression, and second stressor layers 230 has tension stress.

Described first grid dielectric layer 232 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, La ₂O ₃, thickness is preferably about 1-5nm.Described first conductive gate layer 234 can include but not limited to TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa for polysilicon or N type metal _x, NiTa _xPreferably, the work function of described first conductive gate layer 234 is near the conduction band edge of Si, for example apart from the distance on Si conduction band limit less than 0.2eV, thickness is preferably about 1-5nm.Described first stressor layers 236 is filled the gap in the middle of described first conductive gate layer 234, the material that described first stressor layers 236 preferably has compression character, and for example TiAl can form by sputtered with Ti Al.

Described second gate dielectric layer 226 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO2, ZrO ₂, Al ₂O ₃, thickness is preferably about 1-5nm.Described second conductive gate layer 228 can include but not limited to MoN for polysilicon or P type metal _x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi _x, Ni ₃Si, Pt, Ru, Ir, Mo, HfRu, RuO _xPreferably, the work function of described conductive gate layer 228 is near the valence-band edge edge of Si, for example apart from the distance of Si valence-band edge less than 0.2eV, thickness is preferably about 1-5nm.Described second stressor layers 230 is filled the gap in the middle of described second conductive gate layer 228.Described second stressor layers 230 preferably includes the material with tension stress character, for example can be by depositing Ti and Al in the gap in the middle of piling up at described grid, and approximately carrying out the TiAl that about 1-20s thermal annealing second forms tension stress character under 300-500 ℃.

Shown in Fig. 2-4, at first on substrate, form first dummy gate layer 208 (for example polysilicon) and first side wall 216 belong to the nmos area territory, nitride for example is as silicon nitride.Then remove described dummy gate layer 208 with the formation opening, and the formation first grid is piled up in described opening, this first grid is piled up and can be comprised the first grid dielectric layer 232 and first conductive gate layer 234, preferably also comprises first stressor layers 236.In the same manner, at first on substrate, form the second dummy grid dielectric layer 208 and second side wall 216 that belongs to the PMOS zone.Then remove described dummy gate layer 208 with the formation opening, and formation second grid pile up in described opening, these second grid pile up and can comprise second gate dielectric layer 226 and second conductive gate layer 228, preferably also comprise second stressor layers 230, shown in Fig. 7-8.

Described first, second dummy gate layer 208 can for example form in the following way: at first the substrate surface in nmos area territory 202 and PMOS zone 204 deposits for example boundary layer 212 of 1-3nm, and described boundary layer can be an oxide skin(coating) for example, as SiO ₂Deposition dummy gate layer 208 on described boundary layer afterwards, polysilicon for example, thickness is approximately 50-120nm; The deposition-etch protective layer carries out the grid photoetching to form first dummy gate layer and second dummy gate layer 208 again.Described first side wall and second side wall 216 can then carry out reactive ion etching and form by nitride layer on described boundary layer 212.Source-drain electrode and expansion area thereof that described boundary layer 212 can be all device in the follow-up course of processing provide the etching protection.

Especially, described device also is included on the described substrate in the described first grid and piles up and the interlayer dielectric layer of second grid between piling up, shown in Fig. 5-6.Described inter-level dielectric comprises nitride layer 220, for example 10-30nm and oxide skin(coating) 222, for example 10-30nm.Can be by deposition (CVD, PECVD) nitride layer 220 and oxide skin(coating) 222 respectively, carry out the upper surface that the chemical-mechanical planarization operation exposes described first dummy gate layer and second dummy gate layer again and form described interlayer dielectric layer.

Especially, described second grid pile up and can pile up formation prior to the described first grid, cause material and the layer of the first grid in piling up to cause deterioration with the thermal annealing process of avoiding described second stressor layers 230.Promptly at first utilize the etching protective layer that the nmos area territory is protected and expose the PMOS zone; the dummy gate layer 208 in PMOS zone is carried out etching to form opening; and in described opening, form second gate dielectric layer 226, conductive gate layer 228 and optional stressor layers 230, carry out thermal annealing and form the TiAl that preferably has tension stress character with reaction.Then; utilize the etching protective layer that the PMOS locality protection is got up and expose the nmos area territory; the dummy gate layer 208 in nmos area territory is carried out etching forming opening, and in described opening, form first grid dielectric layer 232, conductive gate layer 234 and optionally have first stressor layers 236 of compression character.

Described device also is included in the tertiary stress structure 240 with tension stress character that the described first grid is piled up sidewall; And the 4th stress structure 244 that forms of the sidewall that piles up at described second grid with compression character.Described tertiary stress structure 240 forms for the material that has counter stress character with 236 layers of described first stress, the material that promptly has tension stress character, and tension stress nitride layer for example is as Si ₃N ₄Described the 4th stress structure 244 forms for the material that has counter stress character with described second stressor layers 230, the material that promptly has compression character, and compression nitride layer for example is as Si ₃N ₄

Pile up in the described first grid by removing described first side wall 216 and second side wall 216 back that the sidewall that piles up with second grid deposits the material of tension stress character respectively and the material of compression character forms described tertiary stress structure 240 and the 4th stress structure 244, shown in Fig. 9-15.Can remove described first side wall and second side wall 216 by for example reactive ion etching (RIE), as shown in Figure 9.Especially, the surface deposition etching protective layer that before described reactive ion etching, can pile up at first and second grid, for example oxide skin(coating) 238, pile up to protect described first and second grid.

Owing in the first grid in nmos area territory is piled up, preferably comprise first stressor layers 236 with compression character, for example TiAl layer.Therefore, behind first side wall 216 of removing the nmos area territory, the reaction force that side wall 216 applies is removed, the TiAl layer of compression character is released, cause the tension stress of the channel region 215 in nmos area territory to be promoted, thereby improve the mobility of electronics, improve device performance.In the same manner, behind second side wall 216 of removing the PMOS zone, the reaction force that side wall 216 applies is removed, the TiAl layer of the tension stress character that preferably comprises is released, cause the compression of the channel region 215 in PMOS zone to be promoted, thereby improve the mobility in hole, improve device performance.

The sidewall that piles up in the described first grid forms the tertiary stress structure 240 with tension stress character, the nitride that for example has tension stress character.Especially, described tertiary stress structure comprises that also the top of the source area that is positioned at described nmos area territory and drain region covers the part that described interlayer dielectric layer and the described first grid are piled up.The sidewall that piles up at described second grid forms the 4th stress structure 244 with compression character, the nitride that for example has compression character.Especially, described the 4th stress structure 244 comprises that also the top of the source area that is positioned at described PMOS zone and drain region covers the part that described interlayer dielectric layer and described second grid pile up.

For example, can form third and fourth stress structure 240,244 in the following way.At first as shown in figure 10, deposition has the tertiary stress structure 240 of tension stress character on NMOS and PMOS zone, thickness is approximately 10-30nm, described tertiary stress structure covers entire device, promptly be included on the source area and drain region in described NMOS and PMOS zone, cover the part of the upper surface that described interlayer dielectric layer and first, second grid pile up.Back deposition-etch protective layer 242 on described tertiary stress structure 240 for example can be oxide skin(coating), and as silica, thickness is approximately 5-15nm.Then as shown in figure 11, carry out photoetching so that on the nmos area territory, form the photoetching protective layer.Then carry out etching, for example RIE keeps the etching protective layer 242 on the nmos area territory to remove the etching protective layer 242 on the PMOS zone.Remove photoetching protective layer residual on the nmos area territory afterwards.As shown in figure 12, carry out RIE with selective removal be not etched the tertiary stress structure 240 that protective layer 242 covers, for example nitride layer of tension stress character.

Can adopt the mode identical to form the 4th stress structure 244 with said method.Promptly at first on NMOS and PMOS zone, deposit the 4th stress structure 244 with compression character, thickness is approximately 10-30nm, described the 4th stress structure covers entire device, promptly be included on the source area in described NMOS and PMOS zone and the drain region and cover described interlayer dielectric layer and the part of the upper surface that first, second grid pile up, as shown in figure 13.Back deposition-etch protective layer 246 on described the 4th stress structure 244 for example can be oxide skin(coating), and as silica, thickness is approximately 5-15nm.Then carry out photoetching so that on the PMOS zone, form the photoetching protective layer.Then carry out etching, for example RIE keeps the etching protective layer 246 on the PMOS zone, as shown in figure 14 to remove the etching protective layer 246 on the nmos area territory.Remove photoetching protective layer residual on the nmos area territory afterwards.Carry out RIE with selective removal be not etched the 4th stress structure 244 that protective layer 246 covers, for example nitride layer of compression character.

Described tertiary stress structure 240 is the same identical with common tension stress cap effect, can further improve the tension stress of described nmos device channel region, thereby improves the mobility of electronics, improves device performance.In like manner, described four stress structures 244 are identical the same with common compression cap effect, can further improve the compression of described PMOS device channel region, thereby improve the mobility in hole, improve device performance.

Carry out the surface of chemical-mechanical planarization technology (CMP) with the described Semiconductor substrate of planarization.

Described device can also be included in the contact hole 248 that forms in the interlayer dielectric layer of the source area in described nmos area territory and PMOS zone and top, drain region.Can cover described device upper surface, above the source area in described NMOS and PMOS zone and drain region, carry out photoetching, to form the photoetching protective layer.Carry out RIE and form contact hole 248.Described contact hole 248 can be arranged on that grid apart from NMOS and PMOS zone pile up or the scope of described the 3rd/the 4th about 10-50nm of side wall in.TiN layer that in described contact hole, forms and tungsten contact material.

Especially, can after the doping and annealing of source area that carries out NMOS and PMOS zone and drain region, in described source area and drain region, form metal silicide, for example NiPtSi or CoSi ₂For instance can be by the NiPt of the about 3-12nm of deposition on substrate, approximately carry out thermal annealing under 300-500 ℃, and after annealing, unreacted NiPt etched away and form, so that regulate the contact resistance of the contact hole that forms subsequently.

Structure according to the grid alternative techniques FET device of the carrier mobility with improvement of the present utility model has below been described.

Below will be according to the manufacture method of flow chart description FET device of the present utility model shown in Figure 16.

At step a, provide Semiconductor substrate with nmos area territory and PMOS zone.

As shown in Figure 1, be formed with nmos area territory 202 and PMOS zone 204 on Semiconductor substrate 200, wherein said nmos area territory 202 is isolated by isolated area 206 mutually with described PMOS zone 204.

In the present embodiment, substrate 200 comprises the silicon substrate (for example wafer) that is crystal structure.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 200 can comprise various doping configurations.The substrate 200 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Perhaps, substrate 200 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 200 can comprise epitaxial loayer alternatively, can be by stress changes strengthening the property, and can comprise silicon-on-insulator (SOI) structure.

Schematically provide an isolated area 206 in the present embodiment, the device architecture with a plurality of isolated areas 206 can repeat according to the structural cycle that the utility model provides to form.In the present embodiment, isolated area 206 forms according to the conventional method in this area, can be for example to utilize photoetching technique to form mask on the surface of the device to be formed of Semiconductor substrate 200, and the opening etched substrate by mask is utilized SiO then to form groove ₂Dielectric material is filled this groove.

Then at step b, on described Semiconductor substrate 200, form second contact surface layer 212, second dummy gate layer 208 and second grid that first boundary layer 212, first dummy gate layer 208 and the first grid belong to nmos area territory 202 pile up side wall 216 and belong to the PMOS zone and pile up side wall 216, and in described Semiconductor substrate, form the interlayer dielectric layer that belongs to the source area 214 and the drain region 214 in nmos area territory, the source area 217 that belongs to the PMOS zone and drain region 217 and the channel region 215 in the middle of described source area and drain region and cover described device respectively.

Described first and second boundary layers 212, first and second dummy gate layer 208 and side wall 216 can deposit for example boundary layer 212 of 1-3nm by the at first substrate surface in nmos area territory 202 and PMOS zone 204 for example shown in Figure 2, described boundary layer can be an oxide skin(coating) for example, as SiO ₂Source-drain electrode and expansion area thereof that described boundary layer 212 can be all device in the follow-up course of processing provide the etching protection.Deposition dummy gate layer 208 on described boundary layer afterwards, polysilicon for example, thickness is approximately 50-120nm, and the deposition-etch protective layer carries out the grid photoetching to form first dummy gate layer and second dummy gate layer 208, as shown in Figure 3 again.Described first side wall and second side wall 216 can then carry out reactive ion etching and form, as shown in Figure 4 by nitride layer on described boundary layer 212.

Described source/drain region 214,217 can be injected p type or n type alloy or impurity and form to substrate 200 by the transistor arrangement according to expectation.Source/drain region 214 for example can be the Si:C that the N type mixes, and wherein C% is 0.2-2%, and source/drain region 217 for example can be the SiGe that the P type mixes, and wherein Ge is 20-70%.Source/drain region 214,217 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.Can utilize common semiconducter process and step, described device is carried out thermal annealing, to activate the doping in source electrode and the drain electrode 214,217, thermal annealing can adopt the technologies that those skilled in the art knew such as comprising rapid thermal annealing, spike annealing to carry out, preferably, can use spike annealing, for example approximately 1000-1100 ℃ or laser annealing, activate the doping in source electrode and the drain electrode 214,217, as shown in Figure 4.

Especially, can after the doping and annealing of source area that carries out NMOS and PMOS zone and drain region, in described source area and drain region, form metal silicide, for example NiPtSi.For instance can be by the NiPt of the about 3-12nm of deposition on substrate, approximately carry out thermal annealing under 300-500 ℃, and after annealing, unreacted NiPt etched away and form, so that regulate the contact resistance of the contact hole that forms subsequently.

Can be on the described substrate and the described first grid is piled up and the interlayer dielectric layer of second grid between piling up, shown in Fig. 5-6.Described inter-level dielectric comprises nitride layer 220, for example 10-30nm and oxide skin(coating) 222, for example 10-30nm.Can be by respectively nitride layer 220 and oxide skin(coating) 222, carry out the upper surface that the chemical-mechanical planarization operation exposes described first dummy gate layer and second dummy gate layer again and form described interlayer dielectric layer.

Then enter step c, second dummy gate layer 208 that removes described PMOS zone is to form second opening, forming second grid in described second opening piles up, described second grid pile up and comprise second gate dielectric layer 226 and second conductive gate layer 228, preferably also comprise second stressor layers 230 in the gap in the middle of filling described second grid piles up.Described second gate dielectric layer 226 and second conductive gate layer 228 cover the sidewall and the described second contact surface layer 212 of described second opening, and described second stressor layers 230 is preferably the stress material with tension stress character.

As shown in Figure 7, deposition one deck etching protective layer 224 on device at first, oxide skin(coating) for example, as silica, thickness is approximately 5-20nm, carries out photoetching and form mask protection layer (not shown) on the nmos area territory.Then carry out etching with the etching protective layer 224 on the removal PMOS zone, thereby expose the PMOS zone, remove the mask protective layer on the described nmos area territory again.For example carry out that reactive ion etching RIE removes second dummy gate layer 208, to form opening.In described opening, form second gate dielectric layer 226, conductive gate layer 228 and preferred stressor layers 230.

Described second gate dielectric layer 226 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, Al ₂O ₃, thickness is preferably about 1-5nm.Described second conductive gate layer 228 can include but not limited to MoN for P type metal _x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi _x, Ni ₃Si, Pt, Ru, Ir, Mo, HfRu, RuO _xPreferably, the work function of described conductive gate layer 228 is near the valence-band edge edge of Si, for example apart from the distance of Si valence-band edge less than 0.2eV, thickness is preferably about 1-5nm.Described second stressor layers 230 that preferably includes is filled described second grid and is piled up middle gap, described second stressor layers 230 comprises the material with tension stress character, for example can be by depositing Ti and Al in the gap in the middle of piling up at described grid, and approximately carrying out the TiAl that about 1-20 thermal annealing second forms tension stress character under 300-500 ℃.

Then in steps d, first dummy gate layer that removes described nmos area territory is to form first opening, forming the first grid in described first opening piles up, the described first grid is piled up and is comprised the first grid dielectric layer and first conductive gate layer, first stressor layers that preferably also comprises the gap in the middle of filling the described first grid piles up, the described first grid dielectric layer and first conductive gate layer cover the sidewall and described first boundary layer of described first opening, and described first stressor layers is preferably the stress material with compression character.

As shown in Figure 8, deposition one deck etching protective layer 224 on device, oxide skin(coating) for example, as silica, thickness is approximately 5-20nm, carries out photoetching and form mask protection layer (not shown) on the PMOS zone.Then carry out etching with the etching protective layer 224 on the removal nmos area territory, thereby expose the nmos area territory, remove the mask protective layer on the described PMOS zone again.For example carry out that reactive ion etching RIE removes first dummy gate layer 208, to form opening.In described opening, form first grid dielectric layer 232, conductive gate layer 234 and preferred stressor layers 236.

Described first grid dielectric layer 232 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, La ₂O ₃, thickness is preferably about 1-5nm.Described first conductive gate layer 234 can include but not limited to TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa for N type metal _x, NiTa _xPreferably, the work function of described first conductive gate layer 234 is near the conduction band edge of Si, for example less than distance Si conduction band limit apart from 0.2eV, thickness is preferably about 1-5nm.Described first stressor layers 236 that preferably includes is filled the described first grid and is piled up middle gap, and described first stressor layers 236 comprises the material with compression character, and for example TiAl can form by sputtered with Ti Al.

Especially, described second grid pile up and can pile up formation prior to the described first grid, cause material and the layer of the first grid in piling up to cause deterioration with the thermal annealing process of avoiding described second stressor layers 230.

Then enter step e, remove the described first grid and pile up side wall 216, the tension stress with the channel region that improves described nmos area territory removes described second grid and piles up side wall 216, with the compression of the channel region that improves described PMOS zone.

Can selectively remove described first side wall and second side wall 216 by for example reactive ion etching (RIE), as shown in Figure 9.Especially, the surface deposition etching protective layer that before described reactive ion etching, can pile up at first and second grid, for example oxide skin(coating) 238, pile up to protect described first and second grid.Reactive ion etching can be set like this come the material of etching first side wall and second side wall, etching protective layer that as nitride layer and can the etching stack surface is as oxide skin(coating) 238.

After this, method enters step f, piles up sidewall in the first grid in described nmos area territory and forms the tertiary stress structure with tension stress character; Second grid in described PMOS zone pile up sidewall and form the 4th stress structure with compression character.

For example, can form third and fourth stress structure 240,244 in the following way.At first as shown in figure 10, deposition has the tertiary stress structure 240 of tension stress character on NMOS and PMOS zone, thickness is approximately 10-30nm, described tertiary stress structure 240 covers entire device, promptly is included on the source area in described NMOS and PMOS zone and the drain region and covers described interlayer dielectric layer and the part of the upper surface that first, second grid pile up.Deposition-etch protective layer 242 on described tertiary stress structure 240 for example can be oxide skin(coating) then, and as silica, thickness is approximately 5-15nm.Then as shown in figure 11, carry out photoetching so that on the nmos area territory, form the photoetching protective layer.Then carry out etching, for example RIE keeps the etching protective layer 242 on the nmos area territory to remove the etching protective layer 242 on the PMOS zone.Remove photoetching protective layer residual on the nmos area territory afterwards.As shown in figure 12; carry out RIE with the selective removal tertiary stress structure 240 that protective layer 242 covers that is not etched; the nitride layer of tension stress character for example, and the metal silicide of the oxide skin(coating) that piles up of etching grid and source area, top, drain region not optionally.

Can adopt the mode identical to form the 4th stress structure 244 with said method.Promptly at first on NMOS and PMOS zone, deposit the 4th stress structure 244 with compression character, thickness is approximately 10-30nm, described the 4th stress structure covers entire device, promptly be included on the source area in described NMOS and PMOS zone and the drain region and cover described interlayer dielectric layer and the part of the upper surface that first, second grid pile up, as shown in figure 13.Back deposition-etch protective layer 246 on described the 4th stress structure 244 for example can be oxide skin(coating), and as silica, thickness is approximately 5-15nm.Then carry out photoetching so that on the PMOS zone, form the photoetching protective layer.Then carry out etching, for example RIE keeps the etching protective layer 246 on the PMOS zone, as shown in figure 14 to remove the etching protective layer 246 on the nmos area territory.Remove photoetching protective layer residual on the nmos area territory afterwards.Carry out RIE with selective removal the 4th stress structure 244 that protective layer 246 covers that is not etched, the nitride layer of compression character for example, and the metal silicide of the oxide skin(coating) that piles up of etching grid and source area, top, drain region not optionally.

Selectively, can stop layer by deposition-etch before deposition tertiary stress structure 240, for example thickness is approximately the oxide skin(coating) (not shown) of 3-5nm, so as when etching tertiary stress structure as etching stop layer.Selectively, also can before forming, follow-up contact hole 248 carry out chemical-mechanical planarization technology, as shown in figure 14 so that equitant part is removed in tertiary stress structure 240 and the 4th stress structure 244.

Described tertiary stress structure 240 is identical with common tension stress cap layer effect, can further improve the tension stress of described nmos device channel region, thereby improve the mobility of electronics, improves device performance.Described four stress structures 244 are identical with common compression cap layer effect, can further improve the compression of described PMOS device channel region, thereby improve the mobility in hole, improve device performance.

Then, selectively, described method can also be included in the step that forms contact hole 248 in the interlayer dielectric layer of the source area in described nmos area territory and PMOS zone and top, drain region.Can cover described device upper surface, above the source area in described NMOS and PMOS zone and drain region, carry out photoetching, to form the photoetching protective layer.Carry out RIE and form contact hole 248.Described contact hole 248 can be arranged on that grid apart from NMOS and PMOS zone pile up or the scope of described the 3rd/the 4th about 10-50nm of side wall in.TiN layer that in described contact hole, forms and tungsten contact material.

Below the structure of using cmos device of the present utility model has been described according to embodiment of the present utility model.Yet in some applications, need to use the MOSFET device of particular type, for example n type field effect transistor device or p type field effect transistor device.For example, in NAND fence gate circuit, can use n type field effect transistor.

Embodiment of the present utility model also can provide the MOSFET of particular type, so that MOSFET device of the carrier mobility with improvement and forming method thereof is provided in these application-specific.These schemes those skilled in the art can easily obtain by the content of the embodiment above reading.

Is that example is introduced the explanation that it constructs its formation method in detail below in conjunction with accompanying drawing with the n type field effect transistor device.Wherein identical identical or similar device or the step of Reference numeral representative.The description of following device and forming method thereof also is applicable to p type field effect transistor device and forming method thereof, unless specifically stated otherwise.

As shown in figure 23, described field-effect transistor comprises substrate 300.In the present embodiment, substrate 300 comprises the silicon substrate (for example wafer) that is arranged in crystal structure.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 300 can comprise various doping configurations.The substrate 300 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Perhaps, substrate 300 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 300 can comprise epitaxial loayer alternatively, can be by stress changes strengthening the property, and can comprise silicon-on-insulator (SOI) structure.

Described device also comprises source area and the drain region 314 that is arranged in substrate, and the channel region 315 in the middle of described source area and drain region.For NMOS, the Si:C that for example mixes for the N type in described source/drain region 314, wherein C% is 0.2-2%.For PMOS, the SiGe that for example mixes for the P type in described source/drain region 314, wherein Ge is 20-70%.Source/drain region 314 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.Because the utility model can use the grid alternative techniques, so source electrode and drain electrode 314 are piled up prior to described grid and are formed.Can utilize common semiconducter process and step, described device is carried out thermal annealing, to activate the doping in source electrode and the drain electrode 314.Thermal annealing can adopt the technologies that those skilled in the art knew such as comprising rapid thermal annealing, spike annealing to carry out.

Described device comprises that also the grid that are formed on the substrate 300 pile up, wherein, described grid pile up and comprise gate dielectric layer 332 and the conductive gate layer 334 on described gate dielectric layer 332, preferably also comprise the stressor layers 336 with compression character, described stressor layers 336 is filled the gap in the middle of the described conductive gate layer 334.

For NMOS, described gate dielectric layer 332 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, La ₂O ₃, thickness is preferably about 1-5nm.Described conductive gate layer 334 can include but not limited to TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa for N type metal _x, NiTa _xPreferably, the work function of described conductive gate layer 334 is near the conduction band edge of Si, for example apart from the distance on Si conduction band limit less than 0.2eV, thickness is preferably about 1-5nm.Described stressor layers 336 is filled the gap in the middle of the described conductive gate layer 334, and described stressor layers 336 comprises the material with compression character, and for example TiAl can form by sputtered with Ti Al.

For PMOS, gate dielectric layer 332 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, Al ₂O ₃, thickness is preferably about 1-5nm.Described conductive gate layer 334 can include but not limited to MoN for P type metal _x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi _x, Ni ₃Si, Pt, Ru, Ir, Mo, HfRu, RuO _xPreferably, the work function of described conductive gate layer 334 is near the valence-band edge edge of Si, for example apart from the distance of Si valence-band edge less than 0.2eV, thickness is preferably about 1-5nm.Described stressor layers 336 is filled the gap in the middle of the described conductive gate layer, described stressor layers 336 comprises the material with tension stress character, for example can pass through depositing Ti and Al in the gap in the middle of described conductive gate layer, and under about 300-500 ℃, carry out the TiAl that about 1-20s thermal annealing second forms tension stress character.

As shown in figure 17, described grid pile up by at first form dummy gate layer 308 on substrate, for example polysilicon and side wall 316, and nitride for example is as silicon nitride.Then remove described dummy gate layer 308 with the formation opening, and formation gate dielectric layer 332, conductive gate layer 334 and preferred stressor layers 336 form in described opening.

Described dummy gate layer 308 and side wall 316 can be for example at first substrate surface deposit for example boundary layer 312 of 1-3nm, described boundary layer can be an oxide skin(coating) for example, as SiO ₂Deposition dummy gate layer 308 on described boundary layer afterwards, polysilicon for example, thickness is approximately 50-120nm, and the deposition-etch protective layer carries out the grid photoetching to form dummy gate layer 308 again.Described side wall 316 can then carry out reactive ion etching and form by nitride layer on described boundary layer 312.Described boundary layer 312 can be all device in the follow-up course of processing source-drain electrode and expansion area thereof provide the etching protection.

Especially, described device also comprises the interlayer dielectric layer that is positioned on the described substrate, shown in Figure 18-19.Described inter-level dielectric comprises nitride layer 320, for example 10-30nm and oxide skin(coating) 322, for example 10-30nm.Can (CVD, PECVD) nitride layer 320 and oxide skin(coating) 322 carry out the upper surface that the chemical-mechanical planarization operation exposes described dummy gate layer again and form described interlayer dielectric layer by deposition respectively.

For NMOS, described device also comprises and is positioned at the stress structure with tension stress character 340 that described grid pile up sidewall.Described stress structure 340 forms for the material that has counter stress character with described stressor layers 336, the material that promptly has tension stress character, and tension stress nitride layer for example is as Si ₃N ₄

For PMOS, described device also comprises and is positioned at the stress structure with compression character 340 that described grid pile up sidewall.Described stress structure 340 forms for the material that has counter stress character with described stressor layers 336, the material that promptly has compression character, and compression nitride layer for example is as Si ₃N ₄

Described stress structure 340 deposits the material of tension stress character respectively by the sidewalls of removing described side wall 316 backs and piling up at described grid and the material of compression character forms, shown in Figure 20-22.Can remove described side wall 316 by for example reactive ion etching (RIE), as shown in figure 21.Especially, the surface deposition etching protective layer that before described reactive ion etching, can pile up at grid, for example oxide skin(coating) 338, pile up to protect described grid.

For NMOS, during piling up, grid preferably comprise stressor layers 336, for example the TiAl layer with compression character.Therefore, after removing side wall 316, the reaction force that side wall 316 applies is removed, and the TiAl layer of compression character is released, and causes the tension stress of the channel region 315 of NMOS to be promoted, thereby improves the mobility of electronics, improves device performance.

For PMOS, during piling up, grid preferably comprise stressor layers 336, for example the TiAl layer with tension stress character.After removing side wall 316, the reaction force that side wall 316 applies is removed, and the TiAl layer of tension stress character is released, and causes the compression of the channel region 315 of PMOS to be promoted, thereby improves the mobility in hole, improves device performance.

Especially, described stress structure 340 also comprises the part that described interlayer dielectric layer of covering and grid pile up.

For NMOS, described stress structure 340 is identical with common tension stress cap effect, can further improve the tension stress of described nmos device channel region, thereby improves the mobility of electronics, improves device performance.In like manner, for PMOS, described stress structure 340 is identical with common compression cap effect, can further improve the compression of described PMOS device channel region, thereby improve the mobility in hole, improves device performance.

Described device can also be included in the contact hole 348 that forms in the interlayer dielectric layer of source area and top, drain region.Can cover the upper surface of described device, above described source area and drain region, carry out photoetching, to form the photoetching protective layer.Carry out RIE and form contact hole 348.Described contact hole 348 can be arranged on apart from grid pile up or the scope of the about 10-50nm of described side wall in.TiN layer that in described contact hole, forms and tungsten contact material.

Especially, can after the doping of carrying out source area and drain region and annealing, in described source area and drain region, form metal silicide, for example NiPtSi or CoSi ₂For instance can be by the NiPt of the about 3-12nm of deposition on substrate, approximately carry out thermal annealing under 300-500 ℃, and after annealing, unreacted NiPt etched away and form, so that regulate the contact resistance of the contact hole that forms subsequently.

Below will be according to the manufacture method of flow chart description FET device of the present utility model shown in Figure 25.

At step a, provide Semiconductor substrate.

As shown in figure 17, described field-effect transistor comprises substrate 300.In the present embodiment, substrate 300 comprises the silicon substrate (for example wafer) that is crystal structure.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 300 can comprise various doping configurations.The substrate 300 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Perhaps, substrate 300 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 300 can comprise epitaxial loayer alternatively, can be by stress changes strengthening the property, and can comprise silicon-on-insulator (SOI) structure.

Then, on described Semiconductor substrate, form boundary layer, dummy gate layer and grid and pile up side wall at step b, and the interlayer dielectric layer that in described Semiconductor substrate, forms source area and drain region and the described device of covering.

Formation boundary layer 312, dummy gate layer 308, grid pile up

side wall

316 and 300 formation source areas and drain region 314, the interlayer dielectric layer that covers described device and the channel region 215 in the middle of described source area and drain region in described Semiconductor substrate on described Semiconductor substrate 300.

Described boundary layer 312, dummy gate layer 308 and side wall 316 can be for example shown in Figure 17 at first at the substrate 300 surface depositions boundary layer 312 of 1-3nm for example, described boundary layer 312 can be an oxide skin(coating) for example, as SiO ₂Source-drain electrode and expansion area thereof that described boundary layer 312 can be all device in the follow-up course of processing provide the etching protection.Deposition dummy gate layer 308 on described boundary layer afterwards, polysilicon for example, thickness is approximately 50-120nm, and the deposition-etch protective layer carries out the grid photoetching to form dummy gate layer 308 again.

Described source/drain region 314 can be injected p type or n type alloy or impurity and form to substrate 300 by the transistor arrangement according to expectation.For NMOS, the Si:C that for example mixes for the N type in described source/drain region 314, wherein C% is 0.2-2%.For PMOS, the SiGe that for example mixes for the P type in described source/drain region 314, wherein Ge is 20-70%.Source/drain region 314 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.Because the utility model can be used the grid alternative techniques, therefore source electrode and drain electrode 314 are piled up prior to described grid and are formed, can utilize common semiconducter process and step, described device is carried out thermal annealing, to activate the doping in source electrode and the drain electrode 314, thermal annealing can adopt the technologies that those skilled in the art knew such as comprising rapid thermal annealing, spike annealing to carry out.Preferably, can use spike annealing, for example approximately 1000-1100 ℃ or laser annealing activates the doping in source electrode and the drain electrode 314.

Especially, can after the doping and annealing of source area and drain region, in described source area and drain region, form metal silicide, for example NiPtSi.For instance can be by the NiPt of the about 3-12nm of deposition on substrate, approximately carry out thermal annealing under 300-500 ℃, and after annealing, unreacted NiPt etched away and form, so that regulate the contact resistance of the contact hole that forms subsequently.

Can on described substrate, form interlayer dielectric layer, shown in Figure 18-19.Described inter-level dielectric comprises nitride layer 320, for example 10-30nm and oxide skin(coating) 322, for example 10-30nm.Can be by respectively nitride layer 320 and oxide skin(coating) 322, carry out the upper surface that the chemical-mechanical planarization operation exposes described dummy gate layer again and form described interlayer dielectric layer.

Then enter step c, remove described dummy gate layer 308 to form opening, form grid and pile up in described opening, described grid pile up and comprise gate dielectric layer 332 and conductive gate layer 334, preferably also comprise the stressor layers 336 in the gap in the middle of filling described grid piles up.The stress material of described stressor layers 336 for having stress characteristics.

Wherein said gate dielectric layer 332 and conductive gate layer 334 can cover the sidewall and the described boundary layer 312 of described opening.For NMOS, described gate dielectric layer 332 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, La ₂O ₃, thickness is preferably about 1-5nm.Described conductive gate layer 334 can include but not limited to TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa for N type metal _x, NiTa _xPreferably, the work function of described conductive gate layer 334 is near the conduction band edge of Si, for example apart from the distance at Si conduction band edge less than 0.2eV, thickness is preferably about 1-5nm.Described stressor layers 336 is filled the gap in the middle of the described conductive gate layer 334, and described stressor layers 336 preferably includes the material with compression character, and for example TiAl can form by sputtered with Ti Al.

For PMOS, gate dielectric layer 332 can be thermal oxide layer, comprises silica, silicon nitride, and for example silicon dioxide also can be high K medium, for example HfO ₂, TiO ₂, ZrO ₂, Al ₂O ₃, thickness is preferably about 1-5nm.Described conductive gate layer 334 can include but not limited to MoN for P type metal _x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi _x, Ni ₃Si, Pt, Ru, Ir, Mo, HfRu, RuO _xPreferably, the work function of described conductive gate layer 334 is near the valence-band edge edge of Si, for example apart from the distance on Si valence-band edge edge less than 0.2eV, thickness is preferably about 1-5nm.Described stressor layers 336 is filled described grid and is piled up middle gap, described stressor layers 336 preferably includes the material with tension stress character, for example can be by depositing Ti and Al in the gap in the middle of piling up at described grid, and approximately carrying out the TiAl that about 1-20s thermal annealing second forms tension stress character under 300-500 ℃.

Then enter steps d, remove described grid and pile up side wall 316, to improve the stress of described device channel region.

Can selectively remove side wall 316 by for example reactive ion etching (RIE), as shown in figure 21.Especially, the surface deposition etching protective layer that before described reactive ion etching, can pile up at grid, for example oxide skin(coating) 338, pile up to protect described grid.Like this material that reactive ion etching is come the etching side wall can be set, etching protective layer that as nitride layer and can the etching stack surface is as oxide skin(coating) 338.

For NMOS, because grid preferably comprise the stressor layers 336 with compression character in piling up, TiAl layer for example.Therefore, after removing side wall 316, the reaction force that side wall 316 applies is removed, the TiAl layer of compression character is released, and causes the tension stress of the channel region 315 of NMOS to be promoted, thereby improves the mobility of electronics, improve device performance, as shown in figure 21.

For PMOS, because grid preferably comprise the stressor layers 336 with tension stress character in piling up, TiAl layer for example.After removing side wall 316, the reaction force that side wall 316 applies is removed, and the TiAl layer of tension stress character is released, and causes the compression of the channel region 315 of PMOS to be promoted, thereby improves the mobility in hole, improves device performance, as shown in figure 24.

After this, method enters step e, piles up sidewall at described grid and forms the stress structure that has counter stress character with described stressor layers.

For NMOS, pile up sidewall at described grid and form stress structure 340 with tension stress character.Described stress structure 340 forms for the material that has counter stress character with described stressor layers 336, the material that promptly has tension stress character, and tension stress nitride layer for example is as Si ₃N ₄

For PMOS, pile up sidewall at described grid and form stress structure 340 with compression character.Described stress structure 340 forms for the material that has counter stress character with described stressor layers 336, the material that promptly has compression character, and compression nitride layer for example is as Si ₃N ₄

Especially, described stress structure also comprises the part that described interlayer dielectric layer of covering and grid pile up.

Then, selectively, described method can also be included in the step that forms contact hole 348 in the interlayer dielectric layer.Can cover the upper surface of described device, above described source area and drain region, carry out photoetching, to form the photoetching protective layer.Carry out RIE and form contact hole 348.Described contact hole 348 can be arranged on apart from grid pile up or the scope of the about 10-50nm of described side wall in.TiN layer that in described contact hole, forms and tungsten contact material.

Below described FET device of the present utility model in detail according to embodiment of the present utility model.The utility model can pile up at the described grid of nmos device and PMOS device sidewall and part source area and drain region above form and to have the stressor layers of counter stress character so that further improve the tension stress of nmos device and the compression of PMOS device.That is, can deposit tertiary stress structure with tension stress character and the 4th stress structure that has compression character for PMOS device deposition for nmos device.Preferably, can utilize the grid alternative techniques to form second stressor layers with tension stress character by forming in the gap in the middle of the grid of NMOS pile up respectively in first stressor layers with compression character and the gap in the middle of the grid of PMOS pile up; And after forming described stressor layers, remove side wall that the grid of PMOS and nmos device pile up so that discharge described stress, and then the tension stress of lifting nmos device channel region and the compression of PMOS device channel region to channel region by the side wall alternative techniques.Especially, by device of the present utility model, can be under the situation that device size continues to dwindle, stress is applied to greatest extent in the raceway groove of nmos device and/or PMOS device and improves device performance.

Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present utility model and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping the utility model protection range, the order of processing step can change.

In addition, range of application of the present utility model is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present utility model, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the utility model or obtain identical substantially result, can use them according to the utility model.Therefore, the utility model claims are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.

Claims

1. FET device, described FET device comprises:

Semiconductor substrate with nmos area territory and PMOS zone;

Source area that belongs to the nmos area territory that in described Semiconductor substrate, forms and drain region and the source area and the drain region that belong to the PMOS zone;

In described Semiconductor substrate, form at the source area in described nmos area territory and first channel region between the drain region, and at the source area in described PMOS zone and second channel region between the drain region; And

Second grid that described second channel region top in described PMOS zone is piled up and be positioned to the first grid that is positioned at described first channel region top in described nmos area territory pile up, and wherein, the described first grid is piled up and comprised: first grid dielectric layer; And first conductive gate layer on described first grid dielectric layer, described second grid pile up and comprise: second gate dielectric layer; And second conductive gate layer on described second gate dielectric layer;

It is characterized in that described FET device also comprises:

Pile up the tertiary stress structure with tension stress character of sidewall in the described first grid; And

The 4th stress structure with compression character of the sidewall that piles up at described second grid.

2. FET device according to claim 1, wherein, the described first grid is piled up and is also comprised first stressor layers with compression that is positioned on described first conductive gate layer.

3. FET device according to claim 1, wherein, described second grid pile up and also comprise second stressor layers with tension stress that is positioned on described second conductive gate layer.

4. according to any described FET device in the claim 1 to 3, wherein said tertiary stress structure comprises that also the top of the source area that is positioned at described nmos area territory and drain region covers the part that described interlayer dielectric layer and the described first grid are piled up; And described the 4th stress structure comprises that also the top of the source area that is positioned at described PMOS zone and drain region covers the part that described interlayer dielectric layer and described second grid pile up.

5. according to any described FET device in the claim 1 to 3, also be included in the contact hole that forms in the interlayer dielectric layer of the source area in described nmos area territory and PMOS zone and top, drain region.

6. n type field effect transistor device, described n type field effect transistor device comprises:

Semiconductor substrate;

Source area that in described Semiconductor substrate, forms and drain region;

The channel region between source area and drain region that in described Semiconductor substrate, forms; And

The grid that are positioned at described channel region top pile up, and wherein, described grid pile up and comprise: gate dielectric layer; With the conductive gate layer on described gate dielectric layer;

It is characterized in that described n type field effect transistor device also comprises:

Pile up the stress structure with tension stress character of sidewall at described grid.

7. n type field effect transistor device according to claim 6, wherein said grid pile up and also comprise the stressor layers with compression that is positioned on the described conductive gate layer.

8. according to any described n type field effect transistor device in the claim 6 to 7, wherein said stress structure also comprises the part that described interlayer dielectric layer of covering and described grid pile up.

9. according to any described n type field effect transistor device in the claim 6 to 7, also be included in the contact hole that forms in the interlayer dielectric layer of described source area and drain region top.

10. p type field effect transistor device, described p type field effect transistor device comprises:

Semiconductor substrate;

Source area that in described Semiconductor substrate, forms and drain region;

It is characterized in that described p type field effect transistor device also comprises:

Pile up the stress structure with compression character of sidewall at described grid.

11. piling up, p type field effect transistor device according to claim 10, wherein said grid also comprise the stressor layers that is positioned on the described conductive gate layer with tension stress.

12. according to any described p type field effect transistor device in the claim 10 to 11, wherein said stress structure also comprises the part that described interlayer dielectric layer of covering and described grid pile up.

13., also be included in the contact hole that forms in the interlayer dielectric layer of described source area and drain region top according to any described p type field effect transistor device in the claim 10 to 11.