CN102903751B - Semiconductor element and preparation method thereof - Google Patents
Semiconductor element and preparation method thereof Download PDFInfo
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- CN102903751B CN102903751B CN201110213145.6A CN201110213145A CN102903751B CN 102903751 B CN102903751 B CN 102903751B CN 201110213145 A CN201110213145 A CN 201110213145A CN 102903751 B CN102903751 B CN 102903751B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 15
- 229910052582 BN Inorganic materials 0.000 claims description 14
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910003978 SiClx Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 239000002023 wood Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- 229910052799 carbon Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 66
- 238000004519 manufacturing process Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 238000011049 filling Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention discloses a kind of semiconductor element and preparation method thereof, and the semiconductor element is located in the substrate comprising a substrate, a MOS transistor and a shallow isolating trough is in substrate and around MOS transistor.Wherein the shallow isolating trough is made up of a stress material.
Description
Technical field
The present invention relates to a kind of semiconductor element, there is stress shallow isolating trough or stress contact plunger more particularly, to one kind
Semiconductor element.
Background technology
Existing metal-oxide-semiconductor (MOS) (Metal Oxide Semiconductor, MOS) transistor has generally comprised a base
Bottom, source region, a drain region, a passage be located between source area and drain region and a grid be located at passage top.Its
In, grid is located on passage comprising a gate dielectric, a grid conducting layer is located on gate dielectric, and clearance wall position
In the side wall of grid conducting layer.In general, MOS transistor flows through the amount of drive current meeting of passage under an electric field fixed
It is directly proportional with the carrier mobility in passage.Therefore, how in existing manufacture craft equipment, carrier mobility is lifted
The big problem in current technical field of semiconductors is turned into the switching speed for increasing MOS transistor.
Epitaxial growth manufacture craft, such as SiGe source/drain manufacture craft are utilized after clearance wall formation, in adjoining
Extension is distinguished in the semiconductor base of each clearance wall and generates a SiGe epitaxial layer.Its utilize the lattice parameter of silicon germanide layer with
The different characteristic of silicon, makes silicon epitaxy that strain in structure is produced in silicon base and strained silicon is formed.Because the lattice of germanium-silicon layer is normal
Number (lattice constant) is bigger than silicon, and this causes that the band structure (band structure) of silicon changes, and causes to carry
Flowing sub- mobility increases, therefore can increase the switching speed of MOS transistor to improve integrated circuit effectiveness and speed.
Except the application of epitaxial layer, and as semiconductor fabrication process enters deep-sub-micrometer epoch, semiconductor fabrication process
The middle driving current (drive current) that MOS transistor is lifted using high stress film is increasingly becoming a heat subject.
The driving current of MOS transistor is lifted currently with high stress film can generally be divided into two aspects：One is applying
The metal silicides such as nickel SiClx formed before polysilicon stressor layers (poly stressor)；On the other hand it is then to apply in nickel
The metal silicides such as silicon formed after contact hole etching stopping layer (contact etch stop layer, CESL).
But the carrier of the passage area of MOS transistor is lifted with epitaxial layer or high stress film now
Flow has reached a bottleneck, therefore how to carry the whole semiconductor element of life extra on used manufacture craft extensive now
The efficiency of part is an important topic now.
The content of the invention
Therefore it is an object of the invention to provide a kind of semiconductor element, its mainly by the shallow isolating trough with stress or
Contact plunger lifts the carrier mobility of MOS transistor passage area.
It is that, up to above-mentioned purpose, present pre-ferred embodiments are to disclose a kind of semiconductor element, comprising a substrate, a gold medal oxygen half
Conductor transistor is in the substrate and a shallow isolating trough is in substrate and around MOS transistor.Wherein
The shallow isolating trough is made up of a stress material.
Another embodiment of the present invention is to disclose a kind of semiconductor element, and it includes a substrate；One MOS transistor
In the substrate；One dielectric layer is located in substrate and covers MOS transistor；And at least a stress connector is located at
In the dielectric layer and around the MOS transistor.Wherein the contact plunger is made up of a stress material.
Further embodiment of this invention is to disclose a kind of method for making semiconductor element.A substrate is provided first, then shape
Into a MOS transistor in the substrate, formed a dielectric layer in substrate and cover MOS transistor and
At least one is formed to contact hole in the dielectric layer and be located at around the MOS transistor.Finally utilize a stress material
Fill up the contact hole.
Brief description of the drawings
Fig. 1 is the schematic diagram that present pre-ferred embodiments make semiconductor element；
Fig. 2 is the upper diagram of the semiconductor element of another embodiment of the present invention；
Fig. 3 is generalized sections of the Fig. 2 along tangent line AA '；
Fig. 4 be another embodiment of the present invention stress connector and contact plunger simultaneously and the top view deposited.
Main element symbol description
The groove of 10 substrate 12
The shallow isolating trough of 14 stress material 16
The gate dielectric of 18 grid structure 20
The off normal clearance wall of 22 gate electrode 24
The lightly doped drain of 26 main gap wall 28
The metal silicide layer of 30 source/drain 32
The interlayer dielectric layer of 34 stressor layers 36
The substrate of 38 contact plunger 60
The gate dielectric of 68 grid structure 70
The off normal clearance wall of 72 gate electrode 74
The lightly doped drain of 76 main gap wall 78
The metal silicide layer of 80 source/drain 82
The interlayer dielectric layer of 84 stressor layers 86
The 88 contact stress connectors of hole 90
The shallow isolating trough of 92 active region 94
96 contact plungers
Specific embodiment
Fig. 1 is refer to, Fig. 1 is the schematic diagram that present pre-ferred embodiments make semiconductor element.As shown in figure 1, first
One substrate 10, a such as silicon base or a silicon-on-insulator (silicon-on-insulator, SOI) substrate etc. are first provided.
Then a shallow isolating trough (shallow trench isolation, STI) manufacture craft is carried out, such as first with together or together
Photoetching and etching process above forms a groove 12 in substrate and separates or around each active region, and being subsequently formed one should
Dead-wood material 14 is in the surface of substrate 10 and fills up groove 12, then carries out a planarization manufacture craft, such as with cmp
The part stress material 14 on manufacture craft removal substrate 10 surface, makes the stress material 14 in groove 12 neat with the surface of substrate 10
It is flat, and form a structure of shallow isolating trough 16 filled up by stress material 14.
According to presently preferred embodiments of the present invention, the stress material 14 for filling up groove 12 may be selected from by silicon nitride, boron nitride, oxygen
The group that SiClx, carborundum and silicon oxide carbide are constituted, and it can be single material to fill up the stress material 14 of shallow isolating trough 16
The bed of material, or multi-layer phase with or the material layer structures that differ, should all belong to covering scope of the invention.Wherein silicon nitride should
Power is between -3.5GPa to 2.0GPa；And the stress of boron nitride is then between -1GPa to -2GPa.Because no matter boron nitride is in air
In, in vacuum or in inert gas in stable state and be a kind of insulator of excellent heat conductivity, therefore the present invention is preferably adopted
It is used as filling up the stress material of groove 12 with boron nitride.
Then a MOS transistor manufacture craft is carried out, such as prior to the base of the both sides of shallow isolating trough 16 in Fig. 1
A grid structure 18 is formed on bottom 10.Wherein grid structure 18 can include a gate dielectric 20 and a gate electrode 22.Then
An off normal clearance wall 24 is formed respectively with main gap wall 26 in the side wall of each grid structure 18, and between off normal clearance wall 24 and master
The lightly doped drain 28 and source/drain 30 of corresponding conductivity type are formed in the substrate 10 of the both sides of gap wall 26 respectively.
Followed by a selective epitaxial growth manufacture craft, one is formed with the substrate 10 of the both sides of main gap wall 26
Epitaxial layer (not shown).Wherein, the material of epitaxial layer can be different according to the kenel of transistor.For example, if prepared
Transistor is a nmos pass transistor, then epitaxial layer preferably includes carborundum；And if prepared transistor is a PMOS transistor,
Then epitaxial layer preferably includes SiGe.
Then a metal silicide manufacture craft can be carried out, for example, is initially formed one by cobalt, titanium, nickel, platinum, palladium, molybdenum or its combination
Deng the metal level (not shown) for being constituted in substrate 10 and source/drain 30 and epitaxial layer is covered, followed by least one times
RTA (rapid thermal anneal, RTP) manufacture craft make metal level and source/drain 30 and epitaxial layer
Reaction, a metal silicide layer 32 is formed with the surface of substrate 10 of the both sides of major side wall 26.Finally unreacted metal is removed again.
Can be subsequently formed a stressor layers 34 and cover substrate 10 and the surface of grid structure 18.The material of stressor layers 34 can be same
It is different according to the kenel of transistor, for example, if prepared transistor is a nmos pass transistor, stressor layers compared with
Good is a tension stress layer；And if prepared transistor is a PMOS transistor, stressor layers are preferably a compressive stress layers.
Stressor layers 34 can also contact etching stopping layer during hole as etching.
Then an interlayer dielectric layer 36 can be formed in substrate 10 and stressor layers 34 are covered, then in interlayer dielectric layer 36 and
Multiple contact holes are formed in stressor layers 34 and the metal materials such as such as tungsten are inserted, to form connecing for multiple connection source/drains 30
Touch connector 38.So far the making of the semiconductor element of present pre-ferred embodiments is completed.
In the present embodiment, the MOS transistor of shallow isolating trough both sides is preferably the golden oxygen half of same conductive type
Conductor transistor, for example, be all nmos pass transistor or PMOS transistor, so that the stress material 14 for filling up shallow isolating trough 16 can be same
When the nmos pass transistor of both sides be provided give a tensile stress, or the PMOS transistor of both sides be provided simultaneously give the compression should
Power.
Please referring next to Fig. 2 and Fig. 3, Fig. 2 for the semiconductor element of another embodiment of the present invention top view and Fig. 3 then
It is Fig. 2 along the generalized section of tangent line AA '.As shown in FIG., a substrate 60, such as a silicon base or an insulating barrier are first provided
Overlying silicon (silicon-on-insulator, SOI) substrate etc..There is an at least active region 92 in substrate 60, and around it
The shallow isolating trough 94 of isolation is provided with, and shallow isolating trough 94 is alternatively the tool stress disclosed by Fig. 1 preferred embodiments of the present invention
Shallow trench isolation structure.
Then in an at least grid structure 68 is formed in substrate 60, wherein grid structure 68 can include a gate dielectric 70
With a gate electrode 72.Then an off normal clearance wall 74 is formed respectively with main gap wall 76 in the side wall of each grid structure 68, and
A lightly doped drain 78 and source/drain 80 are formed in the substrate 60 of off normal clearance wall 74 and the both sides of main gap wall 76.
Followed by a selective epitaxial growth manufacture craft, one is formed with the substrate 60 of the both sides of main gap wall 76
Epitaxial layer (not shown).Wherein, the material of epitaxial layer can be different according to the kenel of transistor.For example, if prepared
Transistor is a nmos pass transistor, then epitaxial layer preferably includes carborundum；And if prepared transistor is a PMOS transistor,
Then epitaxial layer preferably includes SiGe.
Then a metal silicide manufacture craft can be carried out, for example, is initially formed one and is made up of cobalt, titanium, nickel, platinum, palladium, molybdenum etc.
Metal level (not shown) in substrate 60 and source/drain 80 and epitaxial layer is covered, followed by quick liter at least one times
Temperature annealing (rapid thermal anneal, RTP) manufacture craft makes metal level be reacted with source/drain 80 and epitaxial layer, with
A metal silicide layer 82 is formed in the surface of substrate 60 of the both sides of major side wall 76.Finally unreacted metal is removed again.
Then it is optionally formed a stressor layers 84 and covers substrate 60 and the surface of grid structure 68.The material of stressor layers 84
Can be different also according to the kenel of transistor, for example, if prepared transistor is a nmos pass transistor, should
The preferably tension stress layer of power layer 84；And if prepared transistor is a PMOS transistor, stressor layers 84 preferably
Compressive stress layers.Stressor layers 34 can also contact etching stopping layer during hole as etching.
An interlayer dielectric layer 86 is subsequently formed in substrate 60 and stressor layers 84 are covered, once or more is then carried out
Etching process forming multiple contact holes 88 in interlayer dielectric layer 86 and stressor layers 84.Then a stress material is filled out
Hole 88 is completely contacted, to form multiple stress connectors 90 with stress in hole 88 is contacted.It is noted that be different from typically connecting
The contact plunger of source/drain 80 in substrate is connect, it is brilliant that there is the present embodiment the stress connector 90 of stress to be mainly disposed to whole MOS
Source/drain 80 around body pipe and is not electrically connected, needed for it is mainly used for applying the passage area of whole MOS transistor
Stress, rather than for electrically connecting, therefore the set location of stress connector 90 of the invention is preferably parallel grid structure 68
Bearing of trend, that is, parallel channels width.And the MOS transistor of the both sides of stress connector 90 is preferably same conduction
The MOS transistor of pattern, for example, be all nmos pass transistor or PMOS transistor, so that stress connector 90 can be carried simultaneously
Nmos pass transistor for both sides gives a tensile stress, or the PMOS transistor of offer both sides gives a compression stress simultaneously.
According to presently preferred embodiments of the present invention, the stress material for filling up contact hole 88 may be selected from by silicon nitride, boron nitride, oxygen
The group that SiClx, carborundum and silicon oxide carbide are constituted.The stress of wherein silicon nitride is between -3.5GPa to 2.0GPa；And
The stress of boron nitride is then between -1GPa to -2GPa.It is in no matter in atmosphere, in vacuum or in inert gas due to boron nitride
Stable state and be a kind of insulator of excellent heat conductivity, therefore the present invention is preferably used as filling up contact hole 88 using boron nitride
Stress material.So far the making of the semiconductor element of present pre-ferred embodiments is completed.
Then the etching process of once or more is carried out again with the shape in interlayer dielectric layer 86 and stressor layers 84
Into multiple contact hole (not shown).Then a conductive material is filled up into contact hole, forms multiple with conduction with hole is contacted
The contact plunger (not shown) of ability.It is worth noting that, the plurality of contact plunger for electrically connecting, can be located at active region
Optional position in 92, is used to the source/drain 80 that is electrically connected, for example, be arranged between grid structure 68 and stress connector 90, or
It is that stress connector 90 is located between grid structure 68 and contact plunger, even it is that contact plunger is arranged among stress connector 90 simultaneously
Through stress connector 90 with the source/drain 80 that is electrically connected.Referring to Fig. 4, it is stress connector with contact plunger simultaneously and deposits
Top view.As shown in FIG., can be arranged on multiple contact plungers 96 between stress connector 90 and grid structure 68 by the present invention,
And obtain stress connector 90 and conductive plunger 96 and the situation deposited.It is noted that the position that is configured of conductive plunger 96 not office
It is limited to shown in figure, any position of active region 92 is alternatively positioned in again, for example, may be provided in the neighbouring tail end of stress connector 90
Position, this embodiment also belongs to the scope that is covered of the present invention.
In sum, the present invention preferably forms shallow isolating trough in substrate or is filled out when contact hole is formed in interlayer dielectric layer
Stress material is filled, to produce the shallow trench isolation structure or contact plunger with stress, so just can be in epitaxial layer and stressor layers
Whole MOS transistor is more preferably lifted outside iso-stress structure in the carrier mobility of channel region.In addition, above-mentioned for forming tool
Have the shallow isolating trough of stress or the method for contact plunger can arbitrarily arrange in pairs or groups various different manufacture crafts and application to different elements,
Such as memory cell or high voltage device etc..Secondly, disclosed herein transistor can include polysilicon gate or metal gate
The transistor that pole is constituted, and metal gates can be selected from normal-gate (gate first) and make work according to manufacture craft demand
Skill, post tensioned unbonded prestressed concrete (gate last) manufacture craft, preceding dielectric layer with high dielectric constant (high-k first) manufacture craft and rear height
The manufacture crafts such as K dielectrics (high-k last).
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to the claims in the present invention with repair
Decorations, should all belong to covering scope of the invention.
Claims (23)
1. a kind of semiconductor element, comprising：
Substrate；
Transistor is in the substrate；
Shallow isolating trough, in the substrate and around the transistor, the shallow isolating trough is made up of a stress material；
Contact plunger, is arranged on source/drain top, is used to electrically connect source/drain；And
Stress connector, in active area upper dielectric layer and around the whole transistor, the stress connector answers dead-wood by one
Material is constituted, and does not electrically connect source/drain.
2. semiconductor element as claimed in claim 1, the wherein stress material are selected from by silicon nitride, boron nitride, silica, carbon
The group that SiClx and silicon oxide carbide are constituted.
3. semiconductor element as claimed in claim 2, the stress of the wherein silicon nitride is between -3.5GPa to 2.0GPa.
4. semiconductor element as claimed in claim 2, the stress of the wherein boron nitride is between -1GPa to -2GPa.
5. semiconductor element as claimed in claim 1, wherein transistor is included：
Grid structure；
Side wall of the clearance wall located at the grid structure；And
Source/drain is in the substrate of the grid structure both sides.
6. semiconductor element as claimed in claim 5, additionally comprises a stressor layers located at the substrate and the grid structure surface.
7. semiconductor element as claimed in claim 5, the wherein grid structure are a metal gates or a polysilicon gate.
8. a kind of semiconductor element, comprising：
Substrate；
Transistor, in the substrate；
Dielectric layer, in the substrate and covers the transistor；
Contact plunger, is arranged on source/drain top, is used to electrically connect source/drain；And
An at least stress connector, on active area in the dielectric layer and around the whole transistor, and does not electrically connect source
Pole/drain electrode, the stress connector is made up of a stress material.
9. semiconductor element as claimed in claim 8, the wherein stress material are selected from by silicon nitride, boron nitride, silica, carbon
The group that SiClx and silicon oxide carbide are constituted.
10. semiconductor element as claimed in claim 9, the stress of the wherein silicon nitride is between -3.5GPa to 2.0GPa.
11. semiconductor elements as claimed in claim 9, the stress of the wherein boron nitride is between -1GPa to -2GPa.
12. semiconductor elements as claimed in claim 8, the wherein transistor are included：
Grid structure；
Side wall of the clearance wall located at the grid structure；And
Source/drain is in the substrate of the grid structure both sides.
13. semiconductor elements as claimed in claim 12, additionally comprise a stressor layers located at the substrate and the grid structure surface.
14. semiconductor elements as claimed in claim 12, the wherein grid structure are a metal gates or a polysilicon gate.
15. semiconductor elements as claimed in claim 12, the stress connector is located at around the grid structure, and the contact plunger
Between the grid structure and the stress connector.
A kind of 16. methods for making semiconductor element, comprising：
One substrate is provided；
A transistor is formed to be located in the substrate；
A dielectric layer is formed in the substrate and covering the transistor；
A contact plunger is formed, source/drain top is arranged on, is used to electrically connect source/drain；
Form at least one and contact hole in the dielectric layer on active area and around the whole transistor, and do not electrically connect source
Pole/drain electrode；And
The contact hole is filled up using a stress material.
17. methods as claimed in claim 16, the wherein stress material are selected from by silicon nitride, boron nitride, silica, carborundum
And the group that silicon oxide carbide is constituted.
18. methods as claimed in claim 17, the stress of the wherein silicon nitride is between -3.5GPa to 2.0GPa.
19. methods as claimed in claim 17, the stress of the wherein boron nitride is between -1GPa to -2GPa.
20. methods as claimed in claim 16, the wherein transistor are included：
Grid structure；
Side wall of the clearance wall located at the grid structure；And
Source/drain is in the substrate of the grid structure both sides.
21. methods as claimed in claim 20, additionally comprise to form a stressor layers in the substrate and the grid structure surface.
22. methods as claimed in claim 20, the wherein grid structure are a metal gates or a polysilicon gate.
23. methods as claimed in claim 20, the contact hole is around the grid structure, and the contact plunger is located at the grid knot
Between structure and the contact hole.
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| CN101533853A (en) * | 2008-03-13 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Semiconductor structures |
| CN102110612A (en) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| US7342284B2 (en) * | 2006-02-16 | 2008-03-11 | United Microelectronics Corp. | Semiconductor MOS transistor device and method for making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101533853A (en) * | 2008-03-13 | 2009-09-16 | 台湾积体电路制造股份有限公司 | Semiconductor structures |
| CN102110612A (en) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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