TW565865B - Manufacturing method of mixed mode analog device - Google Patents

Abstract

The present invention proposes a manufacturing method of mixed mode analog device, which comprises: when a shallow trench isolation region to isolate the active region of the device and the basic components on it is formed on the semiconductor substrate, forming a polysilicon structure on the shallow trench isolation region for forming the capacitor, forming silicide and titanium nitride layer on it, so as to form the lower electrode of the stack-like capacitor; and then forming a dielectric layer and an upper electrode on the surface of the lower electrode, so that they are combined together to fabricate the stack-like capacitor structure. The present invention utilizes the stacked capacitor to replace the well-known 3-dimensional capacitor structure, and thereby increases the surface area of the capacitor without increasing the subsequent process, so as to increase the capacitance of the capacitor.

Description

565865 V. Description of the invention (1) Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a capacitor of a mixed mode analog device (MIM) using a MIM (Metal Insulator Metal) method. BACKGROUND OF THE INVENTION: A hybrid analog device is a circuit that has digital components such as amplifiers, analog-to-digital converters, etc., and analog components such as positive inverters, adders, etc. in the logic region of a semiconductor wafer. The circuit includes metal oxide semiconductor (MOS) components and capacitors.

The capacitor structure of a hybrid analog device conventionally manufactured in a deep sub-micron semiconductor process is shown in the first figure, which is a shallow trench isolation region (ST I) formed in a semiconductor substrate 10 in sequence. Crystal gate structure 14, lightly doped source / drain region 16, gate spacer 18, and heavily doped source / drain region 20, and other semiconductor basic components; thereafter, self-aligned metal silicide In the manufacturing process, a gate or titanium metal oxide compound 2 2 is formed on the gate structure 14, the source / drain region 20, and a part of the surface, and then a chemical vapor insulation layer 2 4 is deposited on the semiconductor substrate 10. Then, a metal layer 26, a dielectric layer 28, and a metal layer 30 are sequentially formed thereon to form a MIM (Metal Insulator Metal) capacitor 32 structure.

Because the capacitance of the capacitor increases with the surface area of the electrode, and because the dielectric material has a higher dielectric constant, or because the thickness of the dielectric layer decreases, a dielectric layer with a higher dielectricity is formed. However, without causing dielectric failure, the reduction of the thickness of the dielectric layer is easily limited. Therefore, the conventional methods for increasing the capacitance mostly focus on increasing the surface of the electrode.

Page 4 565865 V. Description of the invention (2), or use a higher dielectric constant dielectric layer. In order to increase the surface area of the electrode, the conventional system uses a three-dimensional structure, such as a cylindrical structure, or other Hemi i Spherical Grain (HSG) structures that increase the height and use polycrystalline silicon as the material. The effective area of the metal layer is increased. However, the cylindrical or polycrystalline silicon hemispherical granular three-dimensional structure of the lower electrode has some degree of difficulty in manufacturing; and these methods will cause the height of the lower electrode to increase and the height of the peripheral circuit to be very large. Differences in this type of topology (topology) make the complexity of the subsequent manufacturing process much higher, especially the process control in the photolithography process will become difficult to control. Therefore, the present invention is directed to the above-mentioned problems, and proposes a method for manufacturing a capacitor of a hybrid analog device, so as to solve the lack of knowledge. OBJECTS AND SUMMARY OF THE INVENTION: The main object of the present invention is to provide a capacitor manufacturing method for a hybrid analog device. The method is to form a multilayer capacitor by the MIM method to increase the surface area of the capacitor electrode and thereby increase the capacitance of the capacitor. Another object of the present invention is to provide a capacitor manufacturing method for a hybrid analog device, which uses a laminated capacitor instead of a three-dimensional structure capacitor, so that the difference between the height of the lower electrode and the height of the peripheral circuit can be effectively reduced, making it formless To reduce the control complexity of subsequent processes. Another object of the present invention is to provide a capacitor manufacturing method for a hybrid analog device capable of improving the device manufacturing process and its complexity. To achieve the above object, the present invention sequentially

565865 V. Description of the invention (3) Basic semiconductor elements such as a shallow trench isolation region, a gate structure, and a source / drain region are formed, and a polycrystalline silicon structure is formed on the shallow trench isolation region used to form a capacitor; and then on a semiconductor substrate A metal layer and a titanium nitride layer are sequentially formed thereon, and then a thermal tempering process is performed to form a metal silicide. At this time, the polycrystalline silicon structure and the metal silicide and titanium nitride layer thereon serve as the lower electrode of the capacitor. And then sequentially forming a dielectric layer and an upper electrode layer on the semiconductor substrate, and then forming a patterned photoresist layer thereon to expose the shallow trench isolation region and its components that do not belong to the capacitor range; Then use the patterned photoresist layer as a mask to remove the exposed upper electrode layer, dielectric layer, titanium nitride layer, and metal layer that has not been converted into metal silicide, and then remove the patterned photoresist layer. A laminated capacitor is completed. In the following, detailed descriptions will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features and functions of the present invention. Description of drawing number: 10 semiconductor substrate 12 shallow trench isolation region 14 gate structure 16 lightly doped source / drain region 18 gate spacer 20 heavily doped source / drain region 22 metal silicide 24 chemical vapor insulating layer 26 Metal layer 28 Dielectric layer 30 Metal layer 32 Capacitor 40 Semiconductor substrate 42, 42a Shallow trench isolation region 44 Gate structure 46 Polycrystalline silicon structure 48 Lightly doped source / drain region 50 Gate spacer

565865 V. Description of the invention (4) 52 Heavily doped source / drain region 54 metal layer 56 titanium nitride layer 58 metal silicide 60 dielectric layer 62 upper electrode metal layer 64 polycrystalline silicon buffer layer 66 patterned photoresist layer 68 stack Detailed description of layered capacitors: The present invention uses laminated capacitors to replace three-dimensional structure capacitors to improve the conventional use of electrodes under cylindrical or polycrystalline silicon hemispherical granular three-dimensional structures to increase the surface area of the electrodes, resulting in process difficulties and subsequent follow-up. The complexity of the process is increased by many other defects, so that the present invention can reduce the control complexity of subsequent processes while increasing the surface area of the electrode. Please refer to FIG. 2 (a) to FIG. 2 (f) for the process of manufacturing a hybrid analog device according to the present invention. This manufacturing method includes the following steps: First, as shown in FIG. 2 (a), a semiconductor A plurality of shallow trench isolation regions (STIs) 42 are formed in the substrate 40 to isolate active and passive components in the semiconductor substrate 40, and a shallow trench isolation region 42a is reserved as an area for forming a capacitor; A transistor gate structure 44 is formed between the shallow trench isolation regions 42 on the semiconductor substrate 40, and several polycrystalline silicon structures 4 6 are formed on the shallow trench isolation regions 4 2 a; and the gate structure 44 is used as a screen. The semiconductor substrate 40 is implanted with a low concentration ion to form a lightly doped source / drain region 48; and a gate spacer 50 is formed next to the two sidewalls of the gate structure 44 and the polycrystalline silicon structure 46; With the gate structure 44 and the gate gap wall 50 as a mask, a high-concentration ion implantation is performed on the semiconductor substrate 40 to form a heavily doped source / drain region 5 2;

565865 V. Description of the invention (5) A rapid thermal tempering process is performed, so far the basic components on the semiconductor substrate 40 have been completed. Continuing to refer to the second figure (b), a metal layer 54 of cobalt or titanium is first deposited on the semiconductor substrate, the thickness of which is between 50 Angstroms (A) and 50 Angstroms; then (I η- Situ) on the surface of the metal layer 54 using a chemical vapor deposition technology to form a titanium nitride (TiN) layer 56, the thickness of which is between about 200 angstroms and 2000 angstroms. Following a thermal tempering treatment, as shown in the second (c) diagram, after the high-temperature heating treatment, the gate structure 4 4, the source / inverted region 5 2, and the polycrystalline stone structure 4 6 are placed. The metal layer 5 4 on the surface is transformed into a si 1 pesticide 5 8 ′ At this time, the polycrystalline structure 4 6 and the metal silicate 5 8 and the titanium nitride layer 5 6 are used as Laminated lower electrode of a capacitor. Among them, the titanium nitride layer 56 is coated on the metal silicide 58, which is helpful for the stable formation of the metal silicide 58 under high temperature tempering, and can also be used as a lower electrode at the same time. After the dielectric of the container 60 is formed, the thickness of the semiconductor 60 is selected from the group consisting of oxide 1, hafnium oxide, and then the dielectric layer buffer layer 64, the thickness of the layer 62, and the metal silicide 58 of the lower electrode of the nitride group. , That is, the step of forming the electric layer and the upper electrode can be performed. As shown in the second figure, the surface of the titanium nitride layer 56 on the substrate 40 forms a dielectric between about 5 to 5 GG, and the material of the dielectric layer 6G is broken, nitrided, or gas.彳 卜 功 / $

"Called oxygen: 夕 d ^ 、, human oxidized 1 ^ (TW 6. The surface has been formed in succession: iJD special / high-density materials. As a capacitor on the capacitor electrode layer 62 and-polycrystalline stone is attached to From 200 Angstroms to 2000 Angstroms, the upper electrode metal (TaN), crane, and tungsten tungsten carbide are used, and the material is selected from tungsten nitride, ruthenium (Ru), and ruthenium oxide (Ru〇2). )

Page 8 565865 V. Description of the invention (6), metal materials such as iridium (Ir), iridium oxide (IrOD and platinum (Pt)); and the thickness of the polycrystalline silicon buffer layer 64 is between 50 Angstroms and 20 Angstroms. Between 0 0 angstroms. Then, a patterned photoresist layer 6 6 ′ is formed on the semiconductor substrate 40, as shown in the second (e) diagram, which covers the shallow trench isolation region used to form a capacitor. 42a and its components, and expose the shallow trench isolation area 42 and its components that do not belong to the capacitor range. Using the patterned photoresist layer 66 as a cover, first use dry etching to remove the exposure. The polycrystalline silicon buffer layer 64, the upper electrode metal layer 62, and the dielectric layer 60, and then the wet etching method is used to remove the titanium nitride layer 5 6 and the metal layer 5 4 that has not been converted into metal silicide 5 8. The wet etching method uses a chemical solution, such as an aqueous solution of ammonia and hydrogen peroxide, to selectively remove the titanium nitride layer 56 and the metal layer that has not been converted into metal; the metal layer 5 4 can be removed after completion. The pattern can be removed after completion. The photoresist layer 6 6 has a structure of $ = as shown in the second (f) diagram. On the shallow trench isolation area 4 2 a of the inductor, the lower electrode, the dielectric / J: the upper electrode composed of the polycrystalline silicon structure 46 and the metal dream 58 and the titanium nitride layer 56 thereon. The electrode layer composed of the electrode metal ㉟62 and a polycrystalline silicon buffer layer together forms a laminated capacitor 6.8 structure. The present invention is to form a laminated capacitor ^ bulk structure capacitor n in the MIMO manner, so it can effectively reduce Lower generation _ ^ From the gap of piety, to reduce the control complexity of the German and German jealousy, and at the same time increase the capacitance of the capacitor electrode *, the container of the king. The surface area is to increase the electrical point, The embodiments described above are only for the purpose of explaining the technical ideas of the present invention to those skilled in the art and the knowledge of the present invention.

565865 V. Description of the invention (7) Content and implementation based on it, when the scope of the patent of the present invention cannot be limited, that is, any equal change or modification made in accordance with the spirit disclosed by the present invention should still be covered by the patent scope of the present invention Inside. Page 10 565865 Brief description of the diagram The first diagram is a schematic diagram of the capacitor structure of a conventional hybrid analog device. The second (a) to second (f) diagrams show the structure of each step in the production of a hybrid analog device according to the present invention. Sectional view.

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Claims (1)

565865 VI. Application for Patent Scope 1. A capacitor manufacturing method for hybrid analog devices, which includes the following steps: A semiconductor substrate is sequentially formed with a number of shallow trench isolation regions, gate structures, sources, and semiconductors such as pole regions. The basic element is formed with a polycrystalline silicon structure on the shallow trench isolation region used to form a capacitor; a metal layer is formed on the semiconductor substrate, and then a titanium nitride layer is formed; A thermal tempering treatment is performed, so that the metal layer located on the gate structure, the source / drain region, and the surface of the polycrystalline silicon structure is converted into a metal silicide. At this time, the polycrystalline silicon structure and the metal silicide and titanium nitride thereon The layer system serves as the lower electrode of the capacitor; a dielectric layer 5 is formed on the surface of the titanium nitride layer on the semiconductor substrate, and an upper electrode layer is formed on the surface of the dielectric layer; a patterned photoresist layer is formed on the semiconductor On the substrate to expose the shallow trench isolation area and its components that do not belong to the capacitor; and Using the patterned photoresist layer as a mask, remove the exposed upper electrode layer, the dielectric layer, the titanium nitride layer, and the metal layer that has not been converted into a metal oxide, and then remove the patterned photoresist Layer, so that the lower electrode, the dielectric layer and the upper electrode layer located on the shallow trench isolation region for forming a capacitor form a stacked capacitor. 2. Capacitors for hybrid analog components as described in item 1 of the scope of patent application Page 12 565865 VI. Manufacturing method for applying patent scope, wherein the material of the metal layer is titanium metal or cobalt metal 03, the manufacturing method of capacitor of the hybrid analog component as described in item 1 of the applying patent scope, wherein the metal is formed The thickness of the layer is between 50 angstroms and 500 angstroms. 4. The method for manufacturing a capacitor of the hybrid analog device according to item 1 of the scope of the patent application, wherein the thickness of the titanium nitride layer is between 200 angstroms and 2000 angstroms. 5. The method for manufacturing a capacitor of the hybrid analog device according to item 1 of the scope of the patent application, wherein the material of the dielectric layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxide / silicon nitride, oxide button, hafnium oxide, and High dielectric materials such as hafnium oxide. 6. The method for manufacturing a capacitor of the hybrid analog device according to item 1 of the scope of the patent application, wherein the thickness of the dielectric layer is between 50 angstroms and 500 angstroms. 7. The method for manufacturing a capacitor of the hybrid analog device according to item 1 of the scope of patent application, wherein the step of forming the upper electrode layer further comprises: forming an upper electrode metal layer on the surface of the dielectric layer; and forming the upper electrode metal on the surface of the dielectric layer; A buffer layer is formed on the surface of the layer. 8. The method for manufacturing a capacitor of the hybrid analog device according to item 7 of the scope of the patent application, wherein the material of the upper electrode metal layer is selected from the group consisting of titanium nitride, nitride button, osmium, osmium osmium, ruthenium, ruthenium oxide, Silver 'oxidized watch and platinum and other metal materials. 9. Capacitors for hybrid analog components as described in item 7 of the scope of patent applications Page 13 565865. VI. Patent Application Manufacturing method, wherein the thickness of the upper electrode metal layer is between 200 angstroms and 2000 angstroms. 10. The method for manufacturing a capacitor of the hybrid analog device according to item 7 of the scope of the patent application, wherein the buffer layer is a polycrystalline silicon buffer layer. 11. The method for manufacturing a capacitor of the hybrid analog device according to item 7 of the scope of the patent application, wherein the thickness of the buffer layer is between 500 angstroms and 2000 angstroms. 1 2. The method for manufacturing a capacitor of the hybrid analog device according to item 1 of the scope of the patent application, wherein the step of removing the upper electrode layer and the dielectric layer is performed by dry etching. 1 3. The method for manufacturing a capacitor of the hybrid analog device according to item 1 of the scope of the patent application, wherein the titanium nitride layer and the metal layer not converted into a metal silicide are removed by wet etching. 14. The method for manufacturing a capacitor of the hybrid analog device according to item 13 of the scope of the patent application, wherein the wet etching method uses a chemical solution to selectively remove the titanium nitride layer and the metal that has not been converted into a metal silicide. Floor Page 14