564517 A7 ----— _B7__ 五、發明說明（1 ) 【發明領域】 本發明是提供一種積體電路及其製作方法，特別是指 種運用矽晶體型微細加工技術移除部份矽基層之積體電 路及其製作方法。 5【發明背景】 由於通訊市場的開放、資訊家電的快速成長和網際網 路的蓬勃發展，使得具高功能密度及小型化的通訊系統成 為趨勢，而各種元件的發展也隨之朝精密化、薄膜化、小 型化的方向發展，此一趨勢在電感、電容及電阻器等三種 10基礎被動元件尤其明顯。 由於目前通訊系統結構採用超外差結構（Super Heterodyne)，其中，主要進行如編碼、解碼及加密等訊號 處理之基頻（base band)部份，是採用以矽作為基底材料之 標準半導體製程所製成。而進行接收及傳遞無線訊號之中 15頻（IF)及射頻（RF)部份，由於若以石夕為基底材才斗時，元件與 石夕基層間的寄生效應會導致訊號衰減、雜訊和扭曲，造成 各個元件模組與整個電路在高頻性能上的嚴重退化，而成 =以提昇高頻效能的主因之_。故為使元件達到高訊號/ 噪音比之要求，一般均避免與基頻部份之元件一同製作於 20矽基層上，而採用所謂離散式電路的方式，將各個元件，、 如將陶磁元件和表面黏著裝置以及以表面聲波元件製作之 帶通遽波器及石英震蓋器等分開製作，之後再將其接合在 ^仁此法將佔用過大的晶片或是機板使用空間、導致 更尚昂的生產成本，以及更困難的電路系統整合。564517 A7 ----— _B7__ V. Description of the Invention (1) [Field of the Invention] The present invention provides an integrated circuit and a method for manufacturing the same, and particularly refers to a method for removing a part of a silicon base layer by using a silicon crystal type microfabrication technology. Integrated circuit and manufacturing method thereof. 5 [Background of the Invention] Due to the opening of the communication market, the rapid growth of information appliances, and the vigorous development of the Internet, the communication system with high functional density and miniaturization has become a trend, and the development of various components has also become more sophisticated, The trend of thin film and miniaturization is especially obvious in three basic passive components such as inductors, capacitors and resistors. Because the current communication system structure uses Super Heterodyne, among which the base band, which mainly performs signal processing such as encoding, decoding and encryption, is a standard semiconductor manufacturing process using silicon as the base material. production. For receiving and transmitting the 15 frequency (IF) and radio frequency (RF) parts of the wireless signal, if Shi Xi is used as the base material, the parasitic effect between the element and the Shi Xi base layer will cause signal attenuation and noise. And distortion, causing serious degradation of high-frequency performance of each component module and the entire circuit, which is the main reason to improve high-frequency performance_. Therefore, in order to achieve the high signal / noise ratio of components, generally avoid making on the 20 silicon base layer with the components of the fundamental frequency part. Instead, the so-called discrete circuit method is used to integrate each component, such as ceramic magnetic components and The surface adhesive device and the band pass oscillator and the quartz vibrator made of surface acoustic wave components are separately manufactured, and then they are bonded together. This method will occupy too much chip or board space, resulting in more expensive Production costs, and more difficult circuit integration.
564517 A7 B7 五、發明說明（2 ) —- 因此，倘若能將上述之元件整合於單一晶片上，同時 又能避免元件與石夕基層間所產生之寄生、干擾及麵合效 應，則能減少雜訊干擾、大幅提高產品性能，以及降低整 體製作成本。 5 於是，除了提昇元件本身之設計效能外，便有運用隔 絕層之概念來隔絕元件與矽基層以提昇元件效能之方法， 如中華民國專利新型申請第〇871 1 134〇號，於元件下方設 置具有介電係數之絕緣層。此外亦有運用矽晶體型微細： 工技術，移除元件下方之矽基材的方式，以提昇元件效能, ίο參閱第一圖，如美國專利第5539241申請號案，其主要方 法疋於-石夕基層n上形成一氧化I 12;而後於該氧化層 12上形成一電感13,並於該氧化層12上形成複數開口 I*， 由該等開口 14於該矽基層n上蝕刻出一 v型凹穴15，藉 =該V型凹穴15降低該矽基層n之有效介電係數。值 15得注意的是，一般積體電路所使用之矽基層的厚度約 500〜75〇/zm，而形成於矽基層表面上之複數氧化層與複數 金屬層，疊加後之總厚度約^ 1G//m。因此，由上述專利 案件所揭露之圖式可知，相對於該氧化層12之厚度，此項 技術所形成之該等開口 14過大，易因結構間殘留應力而 2〇導致形變，且元件表面全部裸露於大氣之中，不僅無法 與半導體製程配合，更不適合後段之封裝作業。 參閱第二圖，因此便有如美國專利第63263 14申請號 案，除於一矽基層21上形成複數半導體元件（圖未示）、一 氧化層22及-電感23外，更於該氧化層22上形成一垂直 本紙張尺度適用中國國家標準（CNS) A4規格（210χ 297公楚） 第5頁 564517 A7 B7 五、發明說明（3 ) ' ~~ 通道24，並沿4垂直通道24再以乾钱刻方式垂直向下 蝕刻出一不大於該垂直通道24截面積之凹槽25,而後 才利用此深入該矽基層21之凹槽25，以濕蝕刻方式蝕 刻出一較該垂直通道24截面積大之v型凹穴％。由於 5形成該凹槽25之方法必須以乾蝕刻方式進行，故該垂直通 道24亦必須保持垂直，導致形成該垂直通道24及形成該 凹槽25之位置與大小受到限制；更由於乾蝕刻之選擇性較 低且具破壞表面之特性，易損及形成於該v型凹穴26上方 之電感23。且為確實移除造成寄生效應區域内之矽基層 10 21，又受限於矽晶格結構關係僅能形成之v型凹穴26, ^ =必須蝕刻過多之矽基層21，此舉不僅造成蝕刻時間成本 提高，更會因變形塌陷而破壞該v型凹穴26上方已形成之 元件及結構。 製造微機電細微結構的矽晶體型微細加工技術之所以 15難應用於標準半導體電路的製程。主要是由於若在形成複 數氧化層及金屬層前，先於矽基層上進行微細加工，將會 導致因矽基層之表面平坦度降低，而無法實施後續的標準 半導體製程步驟。反之若先於該矽基層形成複數氧化層及 金屬層，則由於穿過該等氧化層及金屬層之開口的形成程 2〇序複雜繁瑣、該開口所須截面積過大，及易損及已形成的 電路及元件之故，一直無法有效整合於現有半導體製程中。 有鑑於此’本案發明人針對半導體元件之電性與物 性，以及矽晶體型微細加工技術；詳思細索，並累積多年 從事微機電整合開發之經驗，幾經試驗，終有本發明之產 i紙張尺度適用家標準（CNS) A4規格（21Gx 297公釐）---- 第6頁 564517564517 A7 B7 V. Description of the invention (2) —- Therefore, if the above-mentioned components can be integrated on a single chip, and at the same time the parasitic, interference and surface effects generated between the component and the Shixi base layer can be avoided, it can be reduced Noise interference, greatly improve product performance, and reduce overall production costs. 5 Therefore, in addition to improving the design performance of the component itself, there are methods of using the concept of an isolation layer to isolate the component from the silicon base layer to improve the performance of the component, such as the Republic of China Patent New Application No. 0871 1 1340, which is arranged below the component. Insulating layer with dielectric constant. In addition, there are also methods of using silicon crystal type micro-fabrication: technology to remove the silicon substrate under the component to improve the performance of the component. See the first picture, such as US Patent No. 5,529,241 application, the main method is An oxide I 12 is formed on the base layer n; then an inductor 13 is formed on the oxide layer 12, and a plurality of openings I * are formed on the oxide layer 12, and a v is etched from the openings 14 on the silicon base layer n. The V-shaped cavity 15 reduces the effective dielectric constant of the silicon substrate n by the V-shaped cavity 15. It is important to note that the thickness of the silicon-based layer used in general integrated circuits is about 500 ~ 75 0 / zm, and the thickness of the multiple oxide layers and metal layers formed on the surface of the silicon base layer is about ^ 1G. // m. Therefore, from the figures disclosed in the above patent cases, it can be known that, relative to the thickness of the oxide layer 12, the openings 14 formed by this technology are too large, and it is easy to cause deformation due to residual stress between structures. Exposed to the atmosphere, not only cannot cooperate with the semiconductor manufacturing process, but also is not suitable for subsequent packaging operations. Referring to the second figure, as in US Patent No. 63263 14 application, in addition to forming a plurality of semiconductor elements (not shown), an oxide layer 22 and an inductor 23 on a silicon-based layer 21, the oxide layer 22 A vertical paper scale is applied to the Chinese National Standard (CNS) A4 specifications (210χ 297 Gongchu) Page 5 564517 A7 B7 V. Description of the invention (3) '~~ Channel 24, and then along the 4 vertical channels 24 and then dry A groove 25 not larger than the cross-sectional area of the vertical channel 24 is etched vertically downward by money engraving, and then the groove 25 deeper than the silicon substrate 21 is used to etch a cross-sectional area larger than the vertical channel 24 by wet etching. Large V-type pits%. Because the method of forming the groove 25 must be performed by dry etching, the vertical channel 24 must also be kept vertical, which results in restrictions on the position and size of forming the vertical channel 24 and the groove 25; The selectivity is low and the surface is damaged. The inductor 23 is easily damaged and formed above the v-shaped cavity 26. Moreover, in order to remove the silicon base layer 10 21 in the area causing parasitic effect, and it is limited by the v-shaped recess 26 that can only be formed by the silicon lattice structure relationship, ^ = silicon base layer 21 must be etched too much, which not only causes etching The time cost increases, and the components and structures formed above the v-shaped cavity 26 are destroyed due to deformation and collapse. The reason why silicon microfabrication technology for manufacturing micro-electromechanical microstructures is difficult to apply to the process of standard semiconductor circuits. The main reason is that if microfabrication is performed on the silicon base layer before forming the multiple oxide layer and the metal layer, the surface flatness of the silicon base layer will be reduced, and subsequent standard semiconductor process steps cannot be implemented. Conversely, if a plurality of oxide layers and metal layers are formed before the silicon-based layer, the formation process of the openings through the oxide layers and metal layers is complicated and complicated, the cross-sectional area of the openings is too large, and the The resulting circuits and components have not been effectively integrated into existing semiconductor processes. In view of this, the inventor of the present case is directed to the electrical and physical properties of semiconductor devices and silicon crystal microfabrication technology; think carefully and accumulate years of experience in micro-electromechanical integration development. After several tests, the product of the present invention will eventually Paper size applies CNS A4 (21Gx 297mm) ---- Page 6 564517
生。 【發明概要】 因此，本發明之目的，在提供一 #攸1八種整合積體電路製程 及矽晶體型微細加工技術之積體電路及其製作方法。 5 本發明之另-目的’在提供-種不損及電路結構並能 移除部份矽基層之積體電路及其製作方法。 本發明之再一目的，在提供一種移除部份矽基層並能 配合封裝之積體電路及其製作方法。 本發明之又一目的，在提供一種能有效隔絕矽基層之 ίο寄生效應的積體電路及其製作方法。 於是，本發明一種積體電路的製造方法，包含下列步 驟： a)於一矽基層之垂直一米勒指數（11〇)面的一基面上形 成一介電層； 15 b)於該介電層上形成一電子元件； c) 形成一貫穿該介電層之通道，使該基面形成由一封 閉邊界所界定之一裸露區域，該邊界具有一與該米 勒指數（110)面夾45度角之直線部份；及 d) 以濕蚀刻方式由該裸露區域蝕刻該矽基層，使該矽 20 基層形成由一圍繞壁所界定且位於該電子元件下方 之一凹陷部。 故依上述步驟所製成之一積體電路，包含該具有該基 面之矽基層、該位於該基面上之介電層、該設置於該介電 層上之電子元件。該石夕基層更具有由該基面向下延伸之該 本紙張尺度適用中國國家標準（CNS) A4規格（210χ 297公爱） 第7頁 564517 A7 二^---------- B7 五、發明說明（5 ) ~ -- 圍、、凡J及由該圍繞壁所界定之該凹陷部；該圍繞壁具有一 與忒基面呈垂直之垂直面。該介電層具有一貫穿該介電層 並與該凹陷部相連通之通道；該通道鄰近且平行該基面之 截面積小於該凹陷部鄰进 旧五十仃該基面之截面積。該電子 5 元件則位於該凹陷部之上方。 【囷式之簡單說明】 本發明之其他技術内容、特徵及優點，在以下配合參 考圖式之較佳實施例的詳細說明中，將可清楚的呈 圖式中： ’ 10 第一圖是習知一積體電路的一立體圖； 第二圖是習知另一積體電路的一部分剖面圖； 第三圖是本發明積體電路及其製作方法的一較佳實施 例之一立體圖，說明一積體電路所使用之一矽基層； 第四圖是該較佳實施例之一流程圖； 15 第五圖是該較佳實施例之一部份剖面示意圖，却αα / 祝明形 成於該石夕基層上之一介電層； 第六圖是該較佳實施例之一部份剖面示意圖， 祝明形 成於該介電層上之複數通孔； 第七圖是該較佳實施例之一部份剖面示意圖， 祝明形 20 成於該介電層上之一第一金屬層； 第八圖是該較佳實施例之一部份剖面示意圖， 规明以 該第一金屬層形成複數第一插塞及複數内連線； 第九圖是該較佳實施例之一部份剖面示意圖，說明# 成於該第一金屬層上之一第一氧化層； 本紙張尺度適用中國國家標準（CNS) Α4規格（210x 297公釐） 第8頁 564517 A7 B7 五、發明說明（6 ) 第十圖是該較佳實施例之一部份剖面示意圖，說明形 成於该苐一氧化層上之複數穿孔； 第十一圖是該較佳實施例之一部份剖面示意圖，說明 形成於該第一氧化層上之複數第二金屬層及複數第二氧化 5層； 第十二圖是該較佳實施例之一部份剖面示意圖，說明 形成於該等第二金屬層及該等第二氧化層上之一保護層； 第十三圖是該較佳實施例之一部份剖面示意圖，說明 依前製程製成之一半成品； 10 第十四圖是該較佳實施例之一部份剖面示意圖，說明 以濕#刻法蝕刻出複數之通道；及 第十五圖是該較佳實施例之一部份剖面示意圖，說明 以濕餘刻法餘刻出一凹陷部。 【發明之詳細說明】 15 本發明積體電路之製作方法能區分為一以互補金屬氧 化半導體（Complemetary Metal —Oxide Semiconductor，以下 簡稱CMOS)製程製作一半成品之前製程，以及一以體型細 微加工技術對該半成品進行蝕刻之後製程。當然，本發明 並不限定使用於CMOS製程，凡是以矽為基底材料所形成 20金屬氧化半導體電晶體（Metal-Oxide-Semiconductor Transistor)及其電路之製程，如BICMOS製程等，亦均適 用於本發明。 參閱第三圖，本發明積體電路之製作方法的一較佳實 施例，一般晶圓廠於CMOS製程中所使用之一矽基層3， 本紙張尺度適用中國國家標準（CNS) A4規格（21〇χ 297公爱） 第9頁 564517 A7Raw. [Summary of the Invention] Therefore, the object of the present invention is to provide integrated circuits with eight integrated circuit processes and silicon crystal microfabrication technology and manufacturing methods thereof. 5 Another object of the present invention is to provide an integrated circuit that does not damage the circuit structure and can remove a part of the silicon base layer and a method for manufacturing the same. Another object of the present invention is to provide a integrated circuit capable of removing a part of a silicon base layer and capable of cooperating with a package, and a manufacturing method thereof. Another object of the present invention is to provide a integrated circuit capable of effectively isolating the parasitic effect of a silicon base layer and a manufacturing method thereof. Therefore, a method for manufacturing an integrated circuit according to the present invention includes the following steps: a) forming a dielectric layer on a base surface of a silicon base layer perpendicular to a Miller index (110) plane; 15 b) on the dielectric An electronic component is formed on the electrical layer; c) forming a channel penetrating the dielectric layer, so that the base surface forms an exposed area defined by a closed boundary, the boundary having a sandwich with the Miller index (110) plane A 45-degree straight line portion; and d) etching the silicon base layer from the exposed area by wet etching, so that the silicon 20 base layer forms a recessed portion defined by a surrounding wall and located below the electronic component. Therefore, an integrated circuit made according to the above steps includes the silicon base layer having the base surface, the dielectric layer located on the base surface, and the electronic component disposed on the dielectric layer. The Shixi base has the paper size extending downward from the base. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210χ 297 public love). Page 7 564517 A7 II ^ ---------- B7 V. Description of the invention (5) ~-Wei, Fan J, and the depression defined by the surrounding wall; the surrounding wall has a vertical plane perpendicular to the base surface of the concrete. The dielectric layer has a channel penetrating the dielectric layer and communicating with the recessed portion; a cross-sectional area of the channel adjacent to and parallel to the base surface is smaller than a cross-sectional area of the recessed portion adjacent to the base surface of the old fifty millimeters. The electronic 5 component is located above the recess. [Brief description of the formula] Other technical contents, features, and advantages of the present invention will be clearly presented in the following detailed description of the preferred embodiment with reference to the drawings: '10 The first figure is a study A perspective view of an integrated circuit is known; the second view is a partial cross-sectional view of another integrated circuit; the third view is a perspective view of a preferred embodiment of an integrated circuit and a manufacturing method thereof according to the present invention. A silicon-based layer used in integrated circuits; Figure 4 is a flowchart of the preferred embodiment; Figure 5 is a schematic cross-sectional view of a part of the preferred embodiment, but αα / Zhu Ming is formed on the stone A dielectric layer on the base layer; FIG. 6 is a schematic partial cross-sectional view of the preferred embodiment, and Zhu Ming is a plurality of through holes formed on the dielectric layer; FIG. 7 is one of the preferred embodiments A partial cross-sectional view of a first metal layer formed on the dielectric layer with a shape of Zhu Ming 20; FIG. 8 is a partial cross-sectional view of a preferred embodiment, which specifies that a plurality of first metal layers are formed by the first metal layer. A plug and a plurality of interconnections; the ninth figure is the better A schematic sectional view of a part of the embodiment, explaining # a first oxide layer formed on the first metal layer; this paper size applies the Chinese National Standard (CNS) A4 specification (210x 297 mm) page 8 564517 A7 B7 V. Description of the invention (6) The tenth figure is a partial cross-sectional schematic diagram of the preferred embodiment, illustrating a plurality of perforations formed on the first oxide layer; the eleventh figure is a part of the preferred embodiment A schematic cross-sectional view illustrating a plurality of second metal layers and a plurality of second oxide 5 layers formed on the first oxide layer; and the twelfth figure is a partial cross-sectional schematic diagram of the preferred embodiment, illustrating the formation on the second oxide layers. The metal layer and a protective layer on the second oxide layers; Figure 13 is a partial cross-sectional view of the preferred embodiment, illustrating a semi-finished product made according to the previous process; 10 Figure 14 is the comparative A partial cross-sectional schematic diagram of one of the preferred embodiments illustrates that plural channels are etched by the wet #etching method; and FIG. 15 is a partial cross-sectional schematic diagram of one of the preferred embodiments that illustrates that one of the channels is etched by the wet residual etching method. Depression. [Detailed description of the invention] 15 The manufacturing method of the integrated circuit according to the present invention can be divided into a process before manufacturing a semi-finished product by a complementary metal oxide semiconductor (hereinafter referred to as CMOS) process, and a micro-fabrication technology using The semi-finished product is processed after etching. Of course, the present invention is not limited to the CMOS process. Any 20-metal oxide semiconductor transistor (Metal-Oxide-Semiconductor Transistor) formed by using silicon as a base material and a circuit process thereof, such as a BICMOS process, are also applicable to this process invention. Referring to the third figure, a preferred embodiment of a method for manufacturing an integrated circuit according to the present invention is one of the silicon substrates 3 used by a general wafer factory in a CMOS process. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 〇χ 297 public love) Page 9 564517 A7
均呈圓形薄板狀。在此引進以整數指數標記晶袼各組原子 平面的米勒指數（Miller indices)，因此通常此矽基層3具有 米勒“數為（1〇〇)之基面31，並且於該石夕基層3之侧邊切 割出一垂直該基面3 1之主切面32，以標定該矽基層3之 5 米勒指數（11 0)面，故依此主切面32即能定義出該矽基層 3之晶袼方向。 參閱第四圖，本發明之較佳實施例的施行步驟如下： 步驟1 00，製備如上所述之矽基層3。 步驟102，參閱第五圖，於該矽基層3之基面31上形 1〇成一介電層4,在本實施例中，該介電層4為一氧化層（thin oxide)； 步驟104,參閱第六圖，於該介電層4上形成複數貫 穿该介電層4之通孔40，在本實施例中是應用半導體製程 中定義光罩圖形以形成接觸窗（contact Hole)之方法製成。 15該等通孔40能使該基面31形成複數分別對應該等通孔4〇 之裸露區域3 11，各該裸露區域3丨丨分別由一呈矩形之封閉 邊界3 1 2所界定，該封閉邊界3丨2之四邊均與上述米勒指 數（110)平面夾45度角。 步驟106，參閱第七圖，於該介電層4上形成一第一 20金屬層51，並藉由該第一金屬層51填滿該等通孔4〇。 步驟108，參閱第八圖，以定義光罩圖形方式使該第 一金屬層51形成複數與該等裸露區域311相接觸之第一插 塞511，以及複數位於該介電層4上方之第一内連線512。 步驟110，參閱第九圖，於該第一金屬層51上形成一 本紙張尺度適用中國國家標準（CNS) A4規格（210χ 297公釐） 第10頁 564517 A7 ______ B7五、發明說明（8 ) 第一氧化層6 1，藉由該第一氧化層6 1隔絕該等第一插塞 5 11及該等第一内連線5 12。 步驟112’參閱第十圖，以定義光罩圖形方式於該第一 氧化層61上形成複數貫穿該第一氧化層61並裸露該第一 5 插塞511之穿孔610。 步驟114 ’參閱第十一圖，重複類似步驟106至步驟 112之程序’於該第一氧化層61上形成複數第二金屬層52 及複數第二氧化層62，藉由該等第二金屬層52及該等第 二氧化層62形成複數分別與該等第一插塞5 11相連接之第 10二插塞521及複數第二内連線522。 步驟116，參閱第十二圖，於該等第二金屬層52及該 等第二氧化層62上形成一保護層63，及複數貫穿該保護 層63並分別對應並裸露該等第二插塞521之開口 630。在 本實施例中，該等開口 63〇之寬度不大於3 V m。 15 上述屬於前製程之步驟能依現行CMOS標準製程於晶 圓廠内實施，參閱第十三圖，藉由該等第一插塞511及該 等第二插塞521之配合能形成複數貫穿該等第一氧化層 61、該等第一氧化層62 ,以及該介電層4之金屬插塞53。 同時更能以該等第一内連線512及該等第二内連線522之 20配合能形成一電子元件54及一與該電子元件54電性連接 之電路單το 55。在本實施中，該電子元件54為一平面螺 旋型晶片式微電感。 以下繼續詳述本實施例的後製程，此後製程包含下列 步驟： 本紙張尺度適用中國而鮮（CNS) A4規格（職297公爱） 第11頁 564517All are round thin plates. Miller indices are used here to mark the atomic planes of each group of crystals with integer indices. Therefore, this silicon-based layer 3 usually has a base surface 31 with a Miller number of (100), and the base layer of the stone A main cutting plane 32 perpendicular to the base plane 31 is cut on the side of 3 to calibrate the 5 Miller index (110) plane of the silicon base layer 3. Therefore, the main cutting plane 32 can define the silicon base layer 3 based on this. Crystal orientation. Referring to the fourth figure, the implementation steps of the preferred embodiment of the present invention are as follows: Step 100, preparing the silicon base layer 3 as described above. Step 102, referring to the fifth figure, on the base surface of the silicon base layer 3. 31 is formed into a dielectric layer 4 in this embodiment. In this embodiment, the dielectric layer 4 is a thin oxide; step 104, referring to the sixth figure, a plurality of dielectric layers 4 are formed through the dielectric layer 4. The through holes 40 of the dielectric layer 4 are made in this embodiment by using a method of defining a mask pattern in a semiconductor process to form a contact hole. 15 The through holes 40 enable the base surface 31 to form a plurality Corresponding to the exposed areas 3 11 of the through holes 40 respectively, each of the exposed areas 3 丨 丨 is covered by a rectangular seal. Defined by the boundary 3 1 2, all four sides of the closed boundary 3 丨 2 are at a 45-degree angle with the Miller index (110) plane. Step 106, referring to the seventh figure, forming a first 20 on the dielectric layer 4. A metal layer 51, and the through holes 40 are filled by the first metal layer 51. Step 108, referring to the eighth figure, in a manner of defining a mask pattern, the first metal layer 51 is formed into a plurality with the exposed areas. The first plug 511 in contact with 311 and the plurality of first interconnecting lines 512 above the dielectric layer 4. Step 110, referring to the ninth figure, forms a paper size on the first metal layer 51 suitable for China National Standard (CNS) A4 specification (210x297 mm) Page 10 564517 A7 ______ B7 V. Description of the invention (8) The first oxide layer 61 is insulated from the first plugs by the first oxide layer 61 5 11 and these first interconnecting lines 5 12. Step 112 ′, referring to the tenth figure, a plurality of through-holes of the first oxide layer 61 are formed on the first oxide layer 61 in a manner of defining a mask pattern and the first 5 is exposed. The perforation 610 of the plug 511. Step 114 'Refer to the eleventh figure, repeat the similar process from step 106 to step 112 In sequence, a plurality of second metal layers 52 and a plurality of second oxide layers 62 are formed on the first oxide layer 61, and a plurality of the second metal layers 52 and the second oxide layers 62 are respectively formed with the first oxide layers 61 The tenth and second plugs 521 and the plurality of second interconnecting wires 522 connected by the plugs 5 and 11 are connected. At step 116, referring to the twelfth figure, a second metal layer 52 and the second oxide layer 62 are formed. The protective layer 63 and a plurality of openings 630 that penetrate through the protective layer 63 and respectively correspond to and expose the second plugs 521. In this embodiment, the width of the openings 630 is not greater than 3 V m. 15 The above steps that belong to the previous process can be implemented in the wafer fab according to the current CMOS standard process. Refer to the thirteenth figure, and through the cooperation of the first plug 511 and the second plug 521, a plurality can be formed to run through the The first oxide layers 61, the first oxide layers 62, and the metal plugs 53 of the dielectric layer 4. At the same time, it is possible to form an electronic component 54 and a circuit sheet το 55 electrically connected to the electronic component 54 by cooperating with the first internal wiring 512 and the second internal wiring 522. In this embodiment, the electronic component 54 is a planar spiral chip micro-inductor. The following describes the post-process of this embodiment in detail. The subsequent process includes the following steps: The paper size is applicable to the China Fresh (CNS) A4 specification (job 297). Page 11 564517
步驟118,參閱第十三、十四圖，以濕蝕刻法蝕刻該等 金屬插塞53 ,形成複數由該等開口 63〇向下貫通該等第一 氧化層61、該等第一氧化層62及該介電層4之通道， 藉以顯露該等裸露區域311。在本實施例中之濕㈣法是採 5用適於餘刻金屬#質之—定比例的硫酉^雙氧水㈣㈣ 刻該等金屬插塞5 3。 步驟120，|閱第十四、十五圖，透過該等通道以 濕蝕刻法由該等裸露區域3 i丨蝕刻該矽基層3，使該矽基層 3¾/成位於w亥電子元件54下方且由一圍繞壁33所界定 1〇之凹陷部30。在本實施例中，該凹陷部之底面積為25〇以爪 X 2 50 // m，深度則為1〇〇 # m。而蝕刻該矽基層3所採用之 蝕刻液則為非等向性蝕刻液，如K〇H蝕刻液，當然亦能選 用TMAH及EDP等其他種類之非等向性蝕刻液。 步驟122，進行封裝作業，完成該積體電路7。 15 在上述步驟118中是運用濕蝕刻法形成該通道6〇，由 於蝕刻液具有高度的蝕刻效率和選擇性，能藉由該第一氧 化層61及該等第二氧化層62之隔離，完全避免損及該等 第一内連線512及該等第二内連線522。更因蝕刻液具有 極佳之流動性，故能設計以非垂直之路徑佈置該等通道 20 60，並有效縮減該等通道6〇鄰近該開口 63〇之截面積達3 V m以下，使得步驟122能以現行之封裝作業進行，無需 進行任何調整與變動。 而在上述步驟120中，由於是將該介電層4作為蝕刻 遮罩’並藉由與米勒指數（110)面夾45度角之封閉邊界 本紙張尺度適用中國國家標準（CNS) A4規格（21〇χ 297公釐） 第12頁 564517 A7 ___ _B7五、發明說明（10 ) 3 12 ’使得以非等向性餘刻液蚀刻該石夕基層3時，能避免該 矽基層3出現不與該基面31垂直之米勒指數{111}面，而 形成與該基面3 1垂直之圍繞壁33。更運用側向侵蝕之效 果。使得蝕刻出之凹陷部30鄰近且平行該基面3丨之截面 5積大於該通道60鄰近且平行該基面31之截面積。 因此’依據上述步驟1〇〇至步驟122所製成之積體電 路7包含該具有該基面31之矽基層3、該位於該基面31 上之介電層4、該位於該介電層4之第一氧化層61、該等 位於該第一氧化層61上之第二氧化層62、該位於該等第 10二氧化層62上之保護層63、該等形成於該基面31上之半 導體元件34、該位於該介電層4上並連接該等半導體元件 34之電路單元55,及該設置於該介電層4上並與該電路單 元55相連接之電子元件54。 該石夕基層3更具有由該基面31向下延伸之該圍繞壁 15 33 ’以及位於該電子元件54下方且由該圍繞壁33所界定 之该凹陷部30，該圍繞壁33具有四與該基面31呈垂直之 垂直面331。該介電層4、該第一氧化層61及該等第二氧 化層62上形成有該等貫穿該介電層4、該第一氧化層61 及該等第二氧化層62,並與該凹陷部30相連通之通道60。 20該介電層4鄰近該基面3 1之一側形成有圍繞該通道60且 呈矩形的封閉邊界3 1 2，該邊界3 12四邊之直線部份均與 該石夕基層3之米勒指數（11〇)面夾45度角。該等通道60鄰 近且平行該基面31之截面積小於該凹陷部鄰近且平行 該基面3 1之截面積。該保護層63具有貫穿該保護層63並 本紙張尺度適用中國國家標準（CNS) A4規格（21GX 297公麓) -----— 第13頁 564517Step 118, referring to the thirteenth and fourteenth drawings, the metal plugs 53 are etched by a wet etching method to form a plurality of openings 63 through the first oxide layers 61 and the first oxide layers 62 downward. And the channel of the dielectric layer 4 to expose the exposed areas 311. In the present embodiment, the wet plugging method is to etch the metal plugs 53 using sulfur, hydrogen peroxide, and a certain proportion suitable for the remaining metal. Step 120, | See the fourteenth and fifteenth drawings, and etch the silicon-based layer 3 from the exposed regions 3 i through the channels through the wet etching method, so that the silicon-based layer 3¾ is located below the W Hai electronic component 54 and A depression 30 is defined by a surrounding wall 33. In this embodiment, the area of the bottom of the recessed portion is 25 ° claw X 2 50 // m, and the depth is 100 # m. The etching solution used for etching the silicon-based layer 3 is an anisotropic etching solution, such as a KOH etching solution. Of course, other types of anisotropic etching solutions such as TMAH and EDP can also be selected. In step 122, a packaging operation is performed to complete the integrated circuit 7. 15 In the above step 118, the channel 60 is formed by a wet etching method. Since the etchant has a high etching efficiency and selectivity, it can be completely separated by the first oxide layer 61 and the second oxide layers 62. Avoid damaging the first interconnects 512 and the second interconnects 522. Furthermore, because the etching solution has excellent fluidity, it can be designed to arrange the channels 20 to 60 in a non-vertical path, and effectively reduce the cross-sectional area of the channels 60 adjacent to the opening 63 to less than 3 V m, making the step 122 can be carried out with the current packaging operation without any adjustments and changes. In the above step 120, since the dielectric layer 4 is used as an etch mask 'and the closed boundary is included at a 45-degree angle with the Miller index (110) plane, the paper size is in accordance with the Chinese National Standard (CNS) A4 specification. (21〇χ 297 mm) Page 12 564517 A7 ___ _B7 V. Description of the invention (10) 3 12 'When the Shixi base layer 3 is etched with an anisotropic post-etching liquid, the silicon base layer 3 can be prevented from appearing A Miller index {111} plane perpendicular to the base plane 31 forms a surrounding wall 33 perpendicular to the base plane 31. Use the effects of lateral erosion more. The cross-sectional area of the etched recess 30 adjacent to and parallel to the base surface 3 is larger than the cross-sectional area of the channel 60 adjacent to and parallel to the base surface 31. Therefore, the integrated circuit 7 made according to the above steps 100 to 122 includes the silicon-based layer 3 having the base surface 31, the dielectric layer 4 on the base surface 31, and the dielectric layer The first oxide layer 61 on the fourth, the second oxide layers 62 on the first oxide layer 61, the protective layer 63 on the tenth oxide layers 62, and these are formed on the base surface 31 The semiconductor element 34, the circuit unit 55 located on the dielectric layer 4 and connected to the semiconductor elements 34, and the electronic element 54 disposed on the dielectric layer 4 and connected to the circuit unit 55. The Shixi base layer 3 further has the surrounding wall 15 33 ′ extending downward from the base surface 31 and the depression 30 located below the electronic component 54 and defined by the surrounding wall 33. The surrounding wall 33 has four and The base surface 31 is a vertical vertical surface 331. The dielectric layer 4, the first oxide layer 61, and the second oxide layers 62 are formed with the through layers of the dielectric layer 4, the first oxide layer 61, and the second oxide layers 62. The recessed portion 30 communicates with the passage 60. 20 One side of the dielectric layer 4 adjacent to the base surface 3 1 is formed with a rectangular closed boundary 3 1 2 surrounding the channel 60. The linear portions of the four sides of the boundary 3 12 and the Miller of the Shixi base layer 3 are all formed. The index (110) plane is at a 45-degree angle. The cross-sectional areas of the channels 60 adjacent to and parallel to the base surface 31 are smaller than the cross-sectional areas of the recessed portions adjacent to and parallel to the base surface 31. The protective layer 63 has a penetrating protective layer 63 and the paper size is in accordance with Chinese National Standard (CNS) A4 (21GX 297 feet) ------ Page 13 564517
630之 與該等通道60相連通之該等開口 63〇，且該等開口 寬度不大於3#m。 上述藉由移除部分該矽基層3以形成之凹陷部3〇，具 有隔絕的效果，能避免該矽基層3由於高頻耦合電容或是 5位移電流效應影響電子元件54之自振頻率和品質因數，並 亦能避免衍生渦電流而造成大量能量損失、效能降低及溫 度過熱等現象；從而有效地降低該電子元# 54和該石夕基層 3間的寄生效應，以提昇該電子元件54之效能。當然，該 電子元件54並不限定於平面螺旋形電感，誠如熟習此項技 1〇藝人士所能熟知，凡應用於矽晶材料上並會導致寄生效應 之元件，如電感、電容、電阻、高頻電路之傳輸線和㈣ 變壓器等的效能，均能以本方法加以改善。更由於該凹陷 部30能藉由空氣絕緣之效果達成溫度之隔絕，因此需隔絕 溫度變化之元件裝置，如紅外線感應器及溫度感應器等， 15亦能以本發明之方法提昇效能。同樣地，本發明之方法亦 不侷限於形成特定數目之氧化層與金屬層，以及相對應之 半導體製程與產品，舉凡以類似構造之材料形成的產品， 均能以本發明之方法製成。 綜上所述，本發明積體電路7及其製造方法，有效將 20步驟100至步驟116之半導體製程，以及步驟118及步驟 120之矽晶體型微細加工技術予以整合，使得製作此一移 除部分矽基層3之積體電路7的程序簡化，並使成本降低。 且由於在形成該等通道60時，是採用選擇性高的濕蝕刻方 式蝕刻該等金屬插塞5 3，故能藉由圍繞該金屬插塞5 3之 本紙張尺度適用中國國家標準（CNS) A4規格（210x 297公楚:i----- 第14頁 564517 五、發明說明（12 ) 該等第一氧化層61、該等箆一备儿成 寺第一虱化層62及該介電層4的 隔離’充分保護已佈局之該雷 击丄 叩勹又4電子兀件54及該電路單元55。 更由於該等通道60之佈置不限定 t 个限疋須呈垂直，使得該等開口 630與該等凹陷部3〇之相對 5 專^ 6G之設計彈性。同時由於該等開口㈣之孔徑小於 3…更使得此藉由移除部分石夕基層3而達到避免寄生： 干擾及耦合效應之積艚雷敗7 ^ Α 〜 < 檟骽冤路7，能配合現行後段封裝技術 進行量產。 更由於本發明之方法所形成的該凹陷部％均屬於米 10勒指數{10G}面，相較於習知敍刻出屬於米勒指數⑴面 的ν形凹a υ效加深餘刻深度，i由於餘刻米勒指 數{100}面之蝕刻速率遠較蝕刻米勒指數{111丨面快速，有 助於提昇單位產量及降低生產成本，提昇成本效益。確實 達到本發明之目的。 惟以上所述者，僅為本發明之一較佳實施例而已，當 不能以此限定本發明實施之範圍，即大凡依本發明申請專 利範圍及發明說明書内容所作之簡單的等效變化與修飾， 皆應仍屬本發明專利涵蓋之範圍内。 本紙張尺度適用中國國家標準（CNS) A4規格（210χ 297公釐） 第15頁 564517 A7 B7 五、發明說明（13 ) 【元 件標號對照】 11 矽 基 層 34 半 導 體 元 件 12 氧 化 層 4 介 電 層 13 電 感 40 通 孔 14 開 口 51 第 一 金 屬 層 15 V型凹穴 511 第 一 插 塞 21 矽 基 層 5 12 第 一 内 連 線 22 氧 化 層 52 第 二 金 屬 層 23 電 感 521 第 二 插 塞 24 垂 直 通道 522 第 二 内 連 線 25 凹 槽 53 金 屬 插 塞 26 V型1 HJ穴 54 電 子 元 件 3 矽 基 層 55 電 路 單 元 30 凹 陷 部 60 通 道 3 1 基 面 61 第 一 氧 化 層 3 11 裸 露 區域 610 穿 孔 3 12 封 閉 邊界 62 第 二 氧 化 層 32 主 切 面 63 保 護 層 33 圍 繞 壁 630 開 口 33 1 垂 直 面 7 積 體 電 路The openings 630 connected to the passages 630 of 630, and the widths of the openings are not greater than 3 # m. The above-mentioned recessed portion 30 formed by removing a part of the silicon base layer 3 has an insulation effect, and can prevent the silicon base layer 3 from affecting the natural frequency and quality of the electronic component 54 due to high-frequency coupling capacitance or 5 displacement current effects. Factors, and can also avoid a large amount of energy loss, reduced efficiency, and overheating caused by eddy currents; thereby effectively reducing the parasitic effect between the electronic element # 54 and the Shixi base layer 3 to enhance the electronic component 54 efficacy. Of course, the electronic component 54 is not limited to a planar spiral inductor. As is well known to those skilled in the art, any component that is applied to silicon materials and will cause parasitic effects, such as inductors, capacitors, and resistors. The efficiency of transmission lines, high-frequency circuits, and ㈣ transformers can be improved by this method. Furthermore, since the recessed portion 30 can achieve temperature isolation by the effect of air insulation, it is necessary to isolate temperature-changing component devices, such as infrared sensors and temperature sensors, etc. 15 can also improve the performance by the method of the present invention. Similarly, the method of the present invention is not limited to the formation of a specific number of oxide layers and metal layers, and the corresponding semiconductor processes and products. For example, products made of materials with similar structures can be made by the method of the present invention. In summary, the integrated circuit 7 and the manufacturing method thereof of the present invention effectively integrate the semiconductor manufacturing process of 20 steps 100 to 116 and the silicon crystal microfabrication technology of steps 118 and 120, so that this removal is made. The procedure of the integrated circuit 7 of part of the silicon base layer 3 is simplified and the cost is reduced. And since the metal plugs 5 3 are etched with a highly selective wet etching method when forming the channels 60, the Chinese paper standard (CNS) can be applied to the paper size surrounding the metal plugs 5 3. A4 specifications (210x 297 male Chu: i ----- Page 14 564517 V. Description of the invention (12) The first oxide layer 61, the first oxidized layer 62 of Beiercheng Temple and the reference The isolation of the electrical layer 4 'fully protects the lightning strikes 4 electronic elements 54 and the circuit unit 55 that have been laid out. Moreover, because the arrangement of the channels 60 is not limited, t limits must be vertical, so that these openings The relative design flexibility between 630 and these depressions 30 is 5 ^ 6G. At the same time, the apertures of these openings are smaller than 3 ... It also makes it possible to avoid parasitics by removing part of the basement layer 3: interference and coupling effects The accumulation of thunder and defeat 7 ^ Α ~ < injustice road 7, can cooperate with the current back-end packaging technology for mass production. Moreover, the depressions formed by the method of the present invention all belong to the Miller 10 index {10G} surface , Compared with the conventional description, the ν-shaped concave a υ that belongs to the Miller index ⑴ plane deepens the effect. The depth of engraving, i. Because the etching rate of the {100} plane of the Miller index is much faster than that of the {111 丨 plane of the Miller index, it helps to increase the unit yield, reduce the production cost, and increase the cost efficiency. The objective of the present invention is indeed achieved. However, the above is only a preferred embodiment of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, the simple equivalent changes made according to the scope of the patent application and the content of the invention specification of the present invention, and Modifications should still be within the scope of the invention patent. This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) Page 15 564517 A7 B7 V. Description of the invention (13) 11 Silicon base layer 34 Semiconductor element 12 Oxidation layer 4 Dielectric layer 13 Inductor 40 Through hole 14 Opening 51 First metal layer 15 V-shaped recess 511 First plug 21 Silicon base layer 5 12 First interconnect 22 Oxide layer 52 No. Two metal layers 23 Inductor 521 Second plug 24 Vertical channel 522 Second inner wiring 25 Groove 53 Metal plug 26 V type 1 HJ cavity 54 Electronic component 3 Silicon base layer 55 Circuit unit 30 Recessed portion 60 Channel 3 1 Base surface 61 First oxide layer 3 11 Exposed area 610 Perforation 3 12 Closed boundary 62 Second oxide layer 32 Main cut surface 63 Protective layer 33 Surrounding wall 630 Opening 33 1 Vertical plane 7 Integrated circuit
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線 本紙張尺度適用中國國家標準（CNS) A4規格（210x 297公釐） 第16頁Line This paper size is applicable to Chinese National Standard (CNS) A4 (210x 297 mm) Page 16