經濟部智慧財產局員工消費合作社印製 495961 A7 B7__ 五、發明說明（I ) 本發明是根據申請專利範圍第1項前言部份之在基板 上具有至少一積體化威應元件之配置。 對於整塊單體的積體化電路而言，由於其在共振效應 ，調整網路作業，感應載體，或是諸如此類中的作用方 式，須要高品質的感應率。此用於在矽基礎上的習知技 術所使用的基板是由導電之半導體材料所構成。由於此 等材料之低歐姆特性而造成一個經由至少一由導電材料 所構成之層所現實電感之高功率損失或低品質。對於許 多應用而言，此由矽所構成習知基板的品質，-其對於 常用的移動無線電頻率其位於10以下，-是不夠的。 其品質是經由，（/Γ7Ύ )/R而界定，其中L代表電感 值，C代表電容值，R代表電阻值。 感應的高的品質，尤其是對於共振器，是通常在"在 晶片之外"（"off chip")，即在基板使用的外部，其由 非導電，甚至是半絶緣的半導體材料所構成，例如是 GaAs或是半絶緣的矽所製造，其中産生品質一直到大約 2 0 〇 此一開始就提到技術之一個與此不同的配置，在其中 ，在相同基板表面上的電路，以及一個與此電路連接的 電感在一個形成一線圈的螺旋走向的層的形狀中，由導 電性材料所構成而積體化整合為一體。此由J. Y. Chang 以及其他人所著，於IEEE電子裝置研究報告1993年第5 號第14卷第246-248頁所載之π在矽上之大型懸掛電威 以及其在2撤米（2yum)CM0S無線電頻率放大器中之應用” 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） i Βϋ -^1 emmmw I 1 I · I ϋ 1. ϋ an 1.1 B —mmm ·ϋ ϋ· 1 n ·_1 n I ϋ _ 1 ^ Jei (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 495961 A7 B7__ 五、發明說明（> ) 而為熟知。此配置之基板具有在基板上由導電材料所構 成之層在其垂直投影的區域中之一個凹口，其具有形成 於基板表面中洞孔。經由它此由導電材料所構成的層懸 掛地配置。此凹口作用如同一個在導電基板中所形成之 局部電絶緣區域，而此電絶線區與基板彼此電氣聯結。 此凹口是經由基板蝕刻，由其表面至基板中某一個深 度而産生。 類似的配置各自由以下的文獻而得出：由A. Rofougaran 等人所著，載於1996年技術文摘第392-393之一個具有 轉向差輸出之9 0 0 MHz CMOS LC振盪器； M. Parameswaran等人所著，載於1989之”感測器與致 動器"，第19卷第2 8 9 - 3 07頁之"製造撤機槭結構之新的 方式π ;以及 由Y. Sun等人所著，載於1996年之"EDM0”第78-93頁 之"單體窄帶主動戲應器其使用在矽基板上之懸掛膜被 動元件"。還有在此配置之中，對於一個導電層將在基 板中之一凹口，經由基板的蝕刻從其表面而至基板之某 一深度而産生。 本發明的目的是説明規範在一開始時所提到技術之配 置，其可以用特別簡單的方式製造。 此目的是經由在申請專利範圍第1項之特徼部份中所 説明的特激而獲得解決。 此解決方法是基於此種想法，此凹口不是由基板之表 面-其面向此電絶緣層-，而是由一個背向此表面之基板 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------^11^·-------訂---------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 495961 A7 B7__ 五、發明說明（3 ) 表面之反面而産生。因此在根據本發明的配置中，不同 於所提到技術的習知配置，在一個背向基板表面之基板 反面之表面形成洞孔。 此根據本發明的凹口是特別簡單並且在基本上沒有影 響干涉可製造之製程技術，其在背向反面之表面的基板 表面上産生結構時可使用。特別是根據本發明的配置可 以有利地在習知之矽製程技術，而在保持在此技術中所 使用的材料及/或層的順序之下，並且沒有其他的並且 在基本上沒有干涉此製程技術而被製造。 其唯一的費用在於此被指定並且對於其他的製程沒有 影響的製造根據本發明之凹口。 此根據本發明所製造之凹口可以經由蝕刻半導體材料 ，有利的是非均向性的蝕刻一些對此合適的材料及/或 蝕刻劑，較佳是矽與氫氯化狎（Κ Ο Η )作為蝕刻劑來進行。 因此在一個較佳並且有利的根據本發明的配置中，此 凹口經由將基板從其反面之表面蝕刻而産生。 在考慮由導電材料所構成的層與基板彼此之連接，尤 其有利的是根據本發明的配置，此在基板表面中的凹口 具有一個洞孔，此基板表面面向由電絶緣材料構成的層 以及由導電材料所構成之層，而此洞孔是被由電絶緣材 料所構成的層所完全覆蓋。 在此情況之中此凹口有利的延伸，並且不同於所提到 技術之習知配置，而在兩個彼此背向的表面之間經由整 個的基板而延伸。因此使得能夠有較截止目前為止更佳 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · ^^1 1-^ 1·—·- ^^1 —Bel ·ϋ-1 一一口， ·_ι·1 I ϋ Βϋ I I m ϋ ϋ· ^^1 I ϋ ϋ ι —ϋ ϋ ^^1 ^^1 ϋ ϋ ^^1 ϋ n ^^1 m ^^1 ι 經濟部智慧財產局員工消費合作社印製 495961 A7 B7__ 五、發明說明（今） 的由導電材料所構成的層與基板之間的連接。因而在由 導電材料所構成的層在基板的投影區域中，可以完全沒 有基板材料。 根據本發明的配置可以在使用高的導電性之中，即具 有少於8歐歐公分（ohm cm)之導電能力之半導體材料， 此基板有利地以大於1 0的品質，以特別簡單的方式製造。 較佳的是根據本發明的配置之形成，其感應元件與電 路連接。其在面向由電絶緣材料所構成的層與由導電材 料所構成的層之基板的表面上整合。經由此配置而有利 地在導電基板上建立大於10之高品質的具有感應元件之 單體整合電路，其中此基板的半導體材料可以是高導電 性。因此此整合電路可以有利完全以傳統之製程技術製 造，在其中為了製造凹口而不須要介入干涉。 在根據本發明裝置的較佳配置之中.· -半導體材料由導電性矽所構成，以及電絶緣材料，由 二氧化矽（Si02 )所構成，及/或 -此導電材料具有一金颶，及/或 -在由導電材料所構成的層，與由電絶緣材料所構成的 層之間，配置了由與電絶緣材料所不同的介電材料所 構成的層。 根據本發明的配置是以適合於高頻波前端（HF-Frontends) 中使用為佳。 本發明在以下的説明中根據圖示而有利的作更進一步 的說明。其顯示，各自在垂直於基板表面的橫截面之中 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Φ----Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495961 A7 B7__ V. Description of the Invention (I) The present invention is based on the configuration of the preface of the first item of the scope of the patent application, which has at least one integrated chemical element. For the integrated circuit of a single block, due to its resonance effect, adjusting the network operation, the induction carrier, or the like, it needs a high-quality induction rate. The substrate used in the conventional technology based on silicon is made of a conductive semiconductor material. Due to the low ohmic properties of these materials, a high power loss or low quality of an actual inductance through at least one layer made of a conductive material is caused. For many applications, the quality of this conventional substrate made of silicon-which is below 10 for commonly used mobile radio frequencies-is not sufficient. Its quality is defined by (/ Γ7Ύ) / R, where L represents the inductance value, C represents the capacitance value, and R represents the resistance value. The high quality of induction, especially for resonators, is usually outside the chip ("off chip"), that is, outside the substrate, which is made of non-conductive, even semi-insulating semiconductor materials. The structure is, for example, made of GaAs or semi-insulating silicon, in which the production quality is up to about 200. At the beginning, a different configuration of the technology was mentioned, in which the circuits on the same substrate surface, And an inductor connected to this circuit is integrated and integrated in the shape of a spiral-shaped layer forming a coil. This by JY Chang and others, in the IEEE Electronic Device Research Report, 1993, No. 5, Vol. 14, pp. 246-248, the large hanging electric power of π on silicon and its 2 um (2yum) Application of CM0S Radio Frequency Amplifier "This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) i Βϋ-^ 1 emmmw I 1 I · I ϋ 1. ϋ an 1.1 B —mmm · ϋ ϋ · 1 n · _1 n I ϋ _ 1 ^ Jei (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495961 A7 B7__ 5. Description of the invention (>) is well known. The substrate of this configuration has a notch in a region of a vertical projection of a layer made of a conductive material on the substrate, which has a hole formed in the surface of the substrate. The layer made of a conductive material is suspendedly arranged through it This notch acts like a locally electrically insulated region formed in a conductive substrate, and this electrically insulated region and the substrate are electrically connected to each other. This notch is created by etching the substrate from its surface to a certain depth in the substrate . Similar configuration It is derived from the following literature: a 90 MHz CMOS LC oscillator with a steering difference output in 1996 Technical Digest Nos. 392-393 by A. Rofougaran et al .; M. Parameswaran et al. , "Sensors and Actuators" in 1989, Volume 19, pages 2 8 9-3 07 " A New Way to Make Maple Structures for Weaning Pi; and by Y. Sun et al. "In 1996," EDM0 "on pages 78-93 of the" single-band narrow-band active reactor, which uses a passive passive element on a silicon substrate ". Also in this configuration, for a conductive The layer will be created in a notch in the substrate from its surface to a certain depth of the substrate by etching of the substrate. The purpose of the present invention is to specify the configuration of the technology mentioned at the beginning of the specification, which can be particularly simple to use This purpose is solved by the special stimulus described in the special part of the scope of patent application No. 1. This solution is based on the idea that this notch is not the surface of the substrate-its facing This electrically insulating layer-but a substrate facing away from this surface This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- ^ 11 ^ · ------- Order ------ --- I (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495961 A7 B7__ V. Description of the invention (3) The reverse of the surface. Therefore, in the configuration according to the present invention, different from the conventional configuration of the mentioned technology, a hole is formed in the surface of the substrate opposite to the substrate surface. This notch according to the invention is particularly simple and can be used when producing structures on the surface of the substrate facing away from the surface facing the opposite side, without substantially affecting the process technology that can be manufactured. In particular, the configuration according to the present invention can be advantageously in the conventional silicon process technology, while maintaining the order of the materials and / or layers used in this technology, and nothing else and without substantially interfering with this process technology While being manufactured. Its only cost is the manufacturing of the notch according to the invention, which is specified and has no effect on other processes. The notch manufactured according to the present invention can be etched by etching semiconductor materials. It is advantageous to etch some materials and / or etchant suitable for this purpose, preferably silicon and osmium hydrochloride (Κ Ο Η). Etchant. Thus in a preferred and advantageous configuration according to the invention, this notch is created by etching the substrate from its opposite surface. When considering the connection between a layer made of a conductive material and the substrate, it is particularly advantageous according to the configuration of the invention that the notch in the surface of the substrate has a hole which faces the layer made of an electrically insulating material and A layer made of a conductive material, and the hole is completely covered by a layer made of an electrically insulating material. In this case, the notch extends advantageously and, unlike the conventional configuration of the mentioned technology, extends between two surfaces facing away from each other via the entire substrate. Therefore, it is possible to have a better paper size than that so far. This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page) · ^^ 1 1- ^ 1 ···-^^ 1 —Bel · ϋ-1 One bite, · _ι · 1 I ϋ Βϋ II m ϋ ϋ · ^^ 1 I ϋ ϋ ι —ϋ ϋ ^^ 1 ^^ 1 ϋ ϋ ^^ 1 ϋ n ^^ 1 m ^^ 1 ι Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 495961 A7 B7__ 5. Description of the invention (today) The connection between the layer made of conductive materials and the substrate. Therefore, in the projection area of the substrate made of the layer made of the conductive material, the substrate material can be completely absent. The configuration according to the present invention can be used in a high conductivity, that is, a semiconductor material having a conductivity of less than 8 ohm cm (ohm cm). This substrate is advantageously of a quality greater than 10 in a particularly simple manner. Manufacturing. It is preferred that the configuration according to the invention is formed such that its sensing element is connected to the circuit. It is integrated on the surface of the substrate facing the layer made of an electrically insulating material and the layer made of a conductive material. With this configuration, it is advantageous to establish a high-quality monolithic integrated circuit with an inductive element greater than 10 on a conductive substrate, wherein the semiconductor material of the substrate can be highly conductive. Therefore, the integrated circuit can be advantageously manufactured entirely by traditional process technology, in which interference is not required to make a recess. In a preferred configuration of the device according to the invention.-The semiconductor material is made of conductive silicon, and the electrically insulating material is made of silicon dioxide (Si02), and / or the conductive material has a golden hurricane, And / or-a layer made of a dielectric material different from the electrically insulating material is arranged between the layer made of a conductive material and the layer made of an electrically insulating material. The configuration according to the present invention is preferably suitable for use in high-frequency front ends (HF-Frontends). In the following description, the present invention will be further explained with reference to the drawings. It shows that in the cross section perpendicular to the surface of the substrate, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Φ --- -
^^1 ϋ ϋ mmmmf ^^1 ^^1 I ·ϋ mammt I —ϋ ϋ i^i ϋ i^i ^^1 ϋ ^^1 a^i ^^1 II —ϋ ^^1 ^^1 I 經濟部智慧財產局員工消費合作社印製 A7 __ΒΖ_ 五'發明說明（5 ) ，以概要圖式說明，並且未依照比例。 之簡塱說明 第1圖本方法之開始階段以製造根據本發明的配置。 第2圖本方法之第一中間階段，其中在基板表面的反 面塗佈一蝕刻罩幕，其具有界定在基板中凹口位置的罩 幕涧孔。 第3圖是本方法之終結階段，其形成一個根據本發明 實施例的配裝置β 在此圖中感應元件以1表示，一層此元件1之由導電 材料所構成的層以10表示，一由半導體材料所構成的層 以2表示，一個面向層10之基板2之表面以20，一個介 於表面20與層10之間配置且由電絶緣材料構成的層以3 表示，以及一個背向基板2之表面2〇之基板之表面以20 表示。 圖中的截面説明是各自如此，而使得基板2的表面20 垂直於顯示平面而配置。 為了將本發明可觀的優點明顯的顯示出來，它已經在 開始的步驟中根據第1圖而採用的方法，在基板2之表 面20上整合電路7 ，其經由一或多餾傳統製程技術而製 造並且與由導電材料所構成的層1〇電氣連接。 此電路7可以例如是一放大器及/或振盪器，如同由 上述文件中所産生，及/或一値另外的主動或被動電路 。層10是由導電材料所構成，其可以是例如對基板2之 表面2 0平行螺旋形件其形成電線圈。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —— — — — — — — — — II ·1111111 ·11111111 I 0^^^— (請先閱讀背面之注音？事項再填寫本頁) 495961 A7 B7 五、發明說明（b) 在基板2之反面的表面上在開始階段根據第1圖 塗佈一層對腐蝕半導體材料之蝕刻劑阻抗的蝕刻罩幕， 其具有罩幕洞孔。 因此，此在第2圖中所說明描逑的中間階段形成，在 其中此塗佈的蝕刻罩幕以8 。以及独刻洞孔以81來表示。 此罩幕孔81較佳是位於由導電材料所構成之層1〇所投 影的區域11之中，而位於基板2之反面表面20•之上〇 此投影是經由兩個虛線101與102來表明，其與層10以 及區域11之兩邊接界，並且較佳是此層之對基板2之 表面20之垂直投影之垂直線，是在此表面20之上。 此洞81可以位於雙線1〇1 ，1〇2之内，與其接界或者 大於線段101與1〇2之間的距離a。 於是基板2從這裡在罩幕洞孔81裸露，並且將此包含 投影區域11之反面表面20’以蝕刻劑，在對背向表面20’ 之基板2之表面20之方向中蝕刻。此蝕刻步驟較佳是一 直執行，一直到基板2在其整個厚度D上，即介於表面 20與反面表面20•之間的距離，被蝕刻去除為止。 在去除了罩幕8之後是達到了其在第3圖中所說明的 本方法之終結階段，其形成根據本發明實施例之配置。 根據此例基板2具有經由蝕刻所産生的凹口 21,其具 有在其中背向基板2之表面20之基板2之反面表面20’之洞 210 ，以及此外此在其中面向由電絶緣材料所構成的層 3之基板2之表面20所形成之洞211 ，其由此層3而完 全覆蓋。 -8 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·---- 經濟部智慧財產局員工消費合作社印製^^ 1 ϋ ϋ mmmmf ^^ 1 ^^ 1 I · ϋ mammt I —ϋ ϋ i ^ i ϋ i ^ i ^^ 1 ϋ ^^ 1 a ^ i ^^ 1 II —ϋ ^^ 1 ^^ 1 I The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 __ΒZZ_ Five 'Invention Description (5), which is illustrated in a schematic diagram, and is not to scale. Brief explanation Figure 1 The initial stage of the method to make a configuration according to the invention. FIG. 2 is a first intermediate stage of the method, in which an etch mask is coated on the reverse side of the substrate surface, the mask having a counterbore hole defining a notch position in the substrate. FIG. 3 is the final stage of the method, which forms a distribution device β according to an embodiment of the present invention. In this figure, the sensing element is represented by 1; A layer made of a semiconductor material is denoted by 2, a surface of substrate 2 facing layer 10 is denoted by 20, a layer disposed between surface 20 and layer 10 and composed of an electrically insulating material is denoted by 3, and a substrate facing away The surface of 2 The surface of the substrate of 20 is represented by 20. The cross-sectional illustrations in the figures are such that the surface 20 of the substrate 2 is arranged perpendicular to the display plane. In order to clearly show the considerable advantages of the present invention, it has been used in the initial steps according to the method shown in FIG. 1 to integrate a circuit 7 on the surface 20 of the substrate 2, which is manufactured by one or more traditional distillation process technologies And it is electrically connected to the layer 10 made of a conductive material. This circuit 7 may be, for example, an amplifier and / or an oscillator, as produced in the above-mentioned document, and / or an additional active or passive circuit. The layer 10 is composed of a conductive material, which may be, for example, a parallel spiral member on the surface 20 of the substrate 2 which forms an electric coil. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) —— — — — — — — — — II · 1111111 · 11111111 I 0 ^^^ — (Please read the note on the back first? Matters then (Fill in this page) 495961 A7 B7 V. Description of the invention (b) On the opposite surface of the substrate 2 at the beginning, according to Figure 1, a layer of an etching mask that resists the etchant that corrodes semiconductor materials is formed, which has a mask hole. hole. Therefore, this is formed in the intermediate stage of the drawing described in FIG. 2 in which the etch mask applied thereon is 8 ° in thickness. And the single carved hole is represented by 81. The mask hole 81 is preferably located in the area 11 projected by the layer 10 made of conductive material, and is located on the opposite surface 20 • of the substrate 2. The projection is indicated by two dashed lines 101 and 102. It is bordered on both sides of the layer 10 and the area 11, and preferably, the vertical line of the vertical projection of this layer to the surface 20 of the substrate 2 is above this surface 20. This hole 81 may be located within the double line 101, 102, border it or be greater than the distance a between the line segments 101 and 102. Then, the substrate 2 is exposed from the mask hole 81 from here, and the opposite surface 20 'including the projection area 11 is etched in the direction opposite to the surface 20 of the substrate 2 facing the surface 20' with an etchant. This etching step is preferably performed until the entire thickness D of the substrate 2, that is, the distance between the surface 20 and the reverse surface 20 • is removed by etching. After the mask 8 has been removed, the end stage of the method, which is illustrated in Fig. 3, has been reached, which forms a configuration according to an embodiment of the invention. According to this example, the substrate 2 has a notch 21 produced by etching, which has a hole 210 in the opposite surface 20 ′ of the substrate 2 which faces away from the surface 20 of the substrate 2, and furthermore in which the surface is made of an electrically insulating material. The hole 211 formed by the surface 20 of the substrate 2 of the layer 3 is completely covered by the layer 3. -8-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling this page) · ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
一^J_ ϋ I ί ϋ n I I ϋ n I n ϋ n I ϋ ϋ ϋ n ϋ ϋ n ϋ I m ϋ n I A7 B7 五 '發明說明（3 ) 在投影的區域11之中，不再存在基板2之半導體材料。 根據一個具體的例子，在基板2的表面20上，由矽構 $的圓盤的形狀（晶圓）中用習知的製造過程而産生積體 電路7 ,以及與此電路7電氣相連的感應元件1 ^此電 &緣層3在此製程中由Si02所構成。 因此，此晶圓2經由將背向表面20之反面之表面20， 研磨而大體上如可能地變薄。此項技術如今在安裝積體 胃路使用之前是例行作業。由矽所構成的晶圓2具有例 如150毫米（mm)直徑，因而典型地大約675微米（々m)的 厚度被研磨至一較小的大約18 0微米（# m)的厚度。 此在晶圓2中凹21的製造可以用苛性鉀溶液UOH)經 由蝕刻而進行，此矽具有非常高的選擇性，例如相較於 層3的si02可以一直至1000:1的蝕刻。因此層3在蝕 刻晶圓2以製造凹21時，可以作為蝕刻終止層使用。 只要在經由層3在垂直於晶圓2之表面20之方向中的 蝕刻一停止，隨之在表面20的横方向中就不再發生蝕刻 損害。因為KOH在矽中只産生金字塔形的蝕刻溝渠，其 具有表面（111)作為邊界。 -------丨 I — I I I 訂---------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 於本明具 此 肋是發中 ， 借中本構 出 術其於機 看 技，關槭 此 的下供機 以 刻之提此 可 蝕件有在 點 面條沒明 優 表造此發 的 之製。本 別 面在械， 特 反來機説 個 之以微地 一 板期裝是 的 基時散確 置 ¾長除更 配 成用清。。之 構使以示能明 矽被題提功發 由其主或的本 從，的動換據 此¾明推轉根 罩發的有 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495961 A7 B7 五、發明說明（® ) 經濟部智慧財產局員工消費合作社印製 感 應 元 件 1 本 身 是 在 由 導 電 與 介 電 材 料 所 構 成 的 層 之 中 9 而 它 是 在 一 個 以 習 知 電 晶 體 隔離所 形 成 之 並 由 電 絶 緣 材 料 以 傳 統 方 式 所 構 成 的 靥 3 之 上 9 而 且 可 以 在 産 生 凹 P 2 1 之 刖 産 生 〇 例 如 在 由 電 緣 材 料 所 構 成 的 層 3 之 上 形 成 —% 個 由 介 電 層 4 至 5 所 構 成 的 層 序 列 其 配 置 於 由 金 饜 所 構 成 的 層 1 0 與 層 7 1 之 間 〇 層 7 1 是 配 置 於 層 4 與 層 5 之 間 9 其 各 白 由 介 電 材 料 所 構 成 9 並 且 形 成 電 氣 連 接 70的 一 部 份 9 此 連 接 70將 配 置 於 各 白 由 介 電 材 料 所 構 成 的 層 5 與 6 之 間 的 感 應 元 件 1 之 層 10 9 與 電 路 7 連 接 0 此 電 連 接 70在 層 7 1 附 近 具 有 一 個 導 電 通 路 7 2 9 其 經 由 介 電 層 4 其 將 層 71與 電 路 7 連 接 〇 並 且 一 導 電 通 路 73 經 過 介 電 層 5 9 其 將 介 電 層 7 1與 層 10 連 接 〇 符 號 之 説 明 1 感 應 元 件 2 基 板 3 層 4 介 電 層 5 介 電 層 6 層 7 電 路 8 蝕 刻 罩 幕 1 0 層 -10- ----— — — — — — — — — Aw· — — — — — — — ^ . I I-------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495961 A7 B7 五、發明說明（9 ο 2 ο 2 2 ο 面 表 之 面面 路段孔 表反層通線洞 (請先閱讀背面之注意事項再填寫本頁) Φ — 訂----------線丨· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）一 ^ J_ ϋ I ϋ II n II ϋ n I n ϋ n I ϋ ϋ ϋ n ϋ ϋ n ϋ I m ϋ n I A7 B7 Five 'invention description (3) In the projected area 11, the substrate no longer exists 2 of the semiconductor material. According to a specific example, on the surface 20 of the substrate 2, an integrated circuit 7 is generated from the shape of a silicon wafer (wafer) by a conventional manufacturing process, and the inductance electrically connected to the circuit 7 is generated. Element 1 ^ The electrical & edge layer 3 is composed of SiO2 in this process. Therefore, this wafer 2 is substantially thinned as much as possible via the surface 20 which will face away from the opposite surface 20. This technology is now routine before installing the gastrointestinal tract for use. The wafer 2 made of silicon has, for example, a diameter of 150 millimeters (mm), and thus is typically ground to a thickness of about 675 microns (々m) to a smaller thickness of about 180 microns (#m). The manufacture of the recess 21 in the wafer 2 can be performed by etching with a caustic potassium solution (UOH). This silicon has a very high selectivity. For example, compared to the SiO2 of layer 3, it can be etched up to 1000: 1. Therefore, the layer 3 can be used as an etch stop layer when the wafer 2 is etched to make the recess 21. As long as the etching in the direction perpendicular to the surface 20 of the wafer 2 via the layer 3 is stopped, the etching damage will no longer occur in the lateral direction of the surface 20. Because KOH only produces pyramid-shaped etch trenches in silicon, it has a surface (111) as a boundary. ------- 丨 I — Order III --------- I (Please read the notes on the back before filling this page) The Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives is printed here The ribs are in the middle of the hair. Based on the technique of constructing in the middle, the machine is used to look at the machine, and the lower part of the machine is used to mention the erodible parts. This article is special, in particular, it is said that the basic time dispersion is determined by the minimum installation time. ¾ Long division is more suitable for clearing. . The structure is based on the performance of the masterpiece or master-slave, and the paper size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) 495961 A7 B7 V. Description of the Invention (®) The printed sensor element printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 itself is in a layer made of conductive and dielectric materials 9 and it is in a conventional way隔离 3 formed by transistor isolation and made of electrical insulating material in a conventional manner 9 and 9 can be generated on the basis of the recess P 2 1 formed, for example, on layer 3 made of electrical edge material—% A layer sequence consisting of dielectric layers 4 to 5 is arranged between layers 1 0 and 7 1 made of gold, and layer 7 1 is arranged between layers 4 and 5 9 The dielectric material is 9 and forms part of the electrical connection 70. This connection 70 will Disposed between layers 5 and 6 made of dielectric material. Layers 10 9 and 10 are connected to circuit 7. This electrical connection 70 has a conductive path 7 2 9 near layer 7 1 via a dielectric. Layer 4 It connects layer 71 to circuit 7 and a conductive path 73 passes through dielectric layer 5 9 It connects dielectric layer 7 1 to layer 10 0 Explanation of symbols 1 Inductive element 2 Substrate 3 Layer 4 Dielectric layer 5 Dielectric Electrical layer 6 Layer 7 Circuit 8 Etching mask 10 Layer -10- ---- — — — — — — — — — Aw · — — — — — — ^. I I -------- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 495961 A7 B7 V. Description of the invention (9 ο 2 ο 2 2 ο The surface of the surface of the road section of the surface section of the hole surface of the reverse layer through the hole (please read the precautions on the back before filling this page) Φ — Order ---------- Line 丨 · Ministry of Economic Affairs Printed by the Intellectual Property Bureau Staff Consumer Cooperatives Paper size applicable to Chinese National Standard (CNS) A4 (210 X 297 mm)