WO2000024042A1 - Arrangement with at least one integrated inductive element on a substrate - Google Patents

Arrangement with at least one integrated inductive element on a substrate Download PDF

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Publication number
WO2000024042A1
WO2000024042A1 PCT/DE1999/003341 DE9903341W WO0024042A1 WO 2000024042 A1 WO2000024042 A1 WO 2000024042A1 DE 9903341 W DE9903341 W DE 9903341W WO 0024042 A1 WO0024042 A1 WO 0024042A1
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Prior art keywords
substrate
layer
electrically conductive
arrangement according
recess
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PCT/DE1999/003341
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German (de)
French (fr)
Inventor
Ludwig Treitinger
Josef BÖCK
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Micronas Munich Gmbh
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Publication of WO2000024042A1 publication Critical patent/WO2000024042A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the invention relates to an arrangement with at least one inductive element integrated on a substrate according to the preamble of claim 1.
  • High-quality inductors are required for monolithically integrated circuits whose mode of operation is based on resonance effects, matching networks, inductive transformers or the like. Because of the low resistance of this material, the substrates made of electrically conductive semiconductor material used for standard silicon-based technologies cause high power losses or a low quality for an inductance realized by at least one layer of electrically conductive material. For many applications, the grades on standard silicon substrates, which are below 10 for common mobile radio frequencies, are not sufficient.
  • the quality is defined by L / Cj / R, where L is the inductance value, C is the capacitance value and R is the resistance value.
  • High quality inductors especially for resonators, are usually "off chip", i.e. produced externally using substrates made of non-conductive, but semi-insulating semiconductor material, for example GaAs or semi-insulating silicon, with grades of up to about 20 being obtained.
  • the substrate of this arrangement points in the area of the vertical projection the layer of the electrically conductive material on the substrate has a recess with an opening formed in the surface of the substrate, above which the layer of the electrically conductive material is suspended, This recess acts as a local electrically insulating layer formed in the conductive substrate Area that electrically decouples the electrically insulating layer and the substrate from one another.
  • the cutout is created by etching the substrate from its surface to a certain depth in the substrate.
  • Layer created a recess in the substrate by etching the substrate from its surface to a certain depth in the substrate.
  • the object of the invention is to provide an arrangement of the type mentioned at the outset, which can be manufactured particularly easily.
  • This object is achieved by the features specified in the characterizing part of claim 1.
  • This solution is based on the idea of not producing the cutout from the surface of the substrate which faces the electrically insulating layer, but rather from a rear surface of the substrate which faces away from this surface. Accordingly, in the arrangement according to the invention, in contrast to the known arrangements of the type mentioned, an opening is formed in a rear surface of the substrate facing away from the surface of the substrate.
  • the recess according to the invention can be produced particularly easily and without substantial intervention in process techniques which are used in the production of a structure on the surface of the substrate facing away from the rear surface.
  • the arrangement according to the invention can advantageously be produced in a standard silicon process technology while maintaining the materials and / or layer sequences used in this technology and with no other and without substantial interventions in this process technology.
  • the recess according to the invention can be produced by etching the semiconductor material, advantageously by anisotropically etching a suitable material and / or etchant, preferably silicon and KOH as the etchant.
  • the cutout is a cutout produced by etching the substrate from its rear surface.
  • the cutout in the surface of the substrate which faces the layers made of the electrically insulating and electrically conductive material has an opening which is in particular completely covered by the layer of electrically insulating material.
  • the recess advantageously extends and, in contrast to the known arrangements of the type mentioned, through the entire substrate between its two surfaces facing away from one another. This allows a stronger decoupling between the layer of electrically conductive material and the substrate than before, because in
  • the substrate material can be completely absent.
  • An arrangement according to the invention can also be used when using highly conductive, i.e. having a conductivity of less than 8 ⁇ cm semiconductor material, the substrate advantageously with a quality of more than 10 can be produced in a particularly simple manner.
  • An arrangement according to the invention is preferably designed such that the inductive element is connected to an electrical circuit on the surface of the layer facing the layers of the electrically insulating material and the electrically conductive material
  • Substrate is integrated.
  • This configuration advantageously creates a monolithically integrated electrical circuit with an inductive element of a high quality of more than 10 on a conductive substrate, it being possible for the semiconductor material of the substrate to be highly conductive.
  • the integrated circuit can advantageously be produced entirely using conventional process techniques, in which need not be intervened because of the manufacture of the recess.
  • the semiconductor material consists of electrically conductive silicon and the electrically insulating material made of SiO 2 and / or
  • the electrically conductive material has a metal and / or
  • At least one further layer made of a dielectric material different from the electrically insulating material is arranged between the layer made of the electrically conductive material and the layer made of the electrically insulating material.
  • the arrangement according to the invention is well suited for use in HF front ends.
  • FIG. 1 shows an output stage of a method for producing an arrangement according to the invention
  • FIG. 2 shows a first intermediate stage of the method, in which an etching mask with a mask opening defining the location of a recess in the substrate is applied to a rear surface of a substrate, and
  • an inductive element with 1 a layer made of the electrically conductive material of this element 1 with 10, a substrate made of semiconductor material with 2, a surface of the substrate 2 with 20 facing the layer 10, one between the surface 20 and the layer 10 arranged layer of electrically insulating material with 3 and a surface of the substrate facing away from the surface 20 of the substrate 2 with 20 '.
  • sectional representations in the figures are each such that the surface 20 of the substrate 2 is arranged vertically to the plane of the drawing.
  • an electrical circuit 7 is integrated on the surface 20 of the substrate 2, which circuit 7 has been produced by one or more conventional process techniques is and is electrically connected to the layer 10 of the electrically conductive material.
  • the circuit 7 can be, for example, an amplifier and / or oscillator, as can be seen from the documents specified above, and / or another active or passive circuit.
  • the layer 10 made of the electrically conductive material can be, for example, a flat spiral parallel to the surface 20 of the substrate 2, which forms an electrical coil.
  • An etching mask which is resistant to an etchant attacking the semiconductor material and has a mask opening is applied to the rear surface 20 'of the substrate 2 of the output stage according to FIG.
  • this applied etching mask is designated 8 and this mask opening 81.
  • the mask opening 81 is preferably located in the region 11 of a projection of the layer 10 made of the electrically conductive material onto the rear surface 20 'of the substrate 2.
  • the projection is indicated by two dashed lines 101 and 102 which show the layer 10 and the region 11 on both sides. limit and are preferably the vertical lines to the surface 20 of the substrate 2 of a perpendicular projection of the layer 10 onto this surface 20.
  • the opening 81 can lie within the two lines 101 and 102, be delimited by them or be greater than a distance a between these lines 101 and 102.
  • the substrate 2 is then etched from the rear surface 20 ′, which is exposed in the mask opening 81 and contains the region 11 of the projection, with the etchant in the direction of the surface 20 of the substrate 2 facing away from this surface 20 ′.
  • This etching step is preferably carried out until the substrate 2 over its entire thickness D, i.e. the distance between the rear surface 20 'and the surface 20 is etched off.
  • the substrate 2 has the recess 21 produced by the etching, which has the opening 210 in the rear surface 20 ′ of the substrate 2 facing away from the surface 20 of the substrate 2 and moreover that in the layer 3 from the electrical Isolating material facing surface 20 of the substrate 2 formed opening 211, which is completely covered by this layer 3. In the region 11 of the projection, there is no longer any semiconductor material of the substrate 2.
  • the integrated circuit 7 and the inductive element 1 electrically connected to this circuit 7 are produced on the surface 20 of a substrate 2 in the form of a disk made of silicon by means of standard processing.
  • the electrically insulating layer 3 consists of SiO 2
  • Disks 2 made of silicon with a diameter of 150 mm, for example, are typically ground down to a thickness of about 675 ⁇ m to a smaller thickness of about 180 ⁇ m.
  • the recess 21 in this disk 2 can be produced by etching with potassium hydroxide solution KOH, which etches silicon very selectively, for example up to 1000: 1 in comparison to the SiO 2 of layer 3. Therefore, the layer 3 can be used as an etching stop layer in the etching of the pane 2 to produce the recess 21.
  • the inductive element 1 can be located in layers of electrically conductive and dielectric material, which are formed on the layer 3 of electrically insulating material which forms a standard transistor insulation in a conventional manner and before the generation of the Recess 21 can be generated.
  • a layer sequence of dielectric layers 4 to 5 is formed on the layer 3 made of electrically insulating material, between which layers 10 and 71 made of metal are arranged.
  • Layer 71 is arranged between layers 4 and 5, each made of dielectric material, and forms part of an electrical connection 70, which connects layer 10 of inductive element 1, arranged between layers 5 and 6, each made of dielectric material, to circuit 7.
  • electrical connection 70 has an electrically conductive passage 72 through dielectric layer 4, which connects layer 71 to circuit 7, and an electrically conductive passage 73 through dielectric layer 5, which also includes layer 71 the layer 10 connects.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The passive inductive element (1) of the device comprises at least one layer (10) that is made of an electroconductive material and arranged on an electroconductive substrate (2). Said layer is separated from the substrate by a layer (3) that is made of an electrically insulating material. According to the invention, a recess (21) is formed in the substrate. The recess has an opening (210) in the rear (20') of the substrate opposite the surface (20') of said substrate. The arrangement is particularly simple and can be produced to provide high quality.

Description

Beschreibungdescription
Anordnung mit zumindest einem auf einem Substrat integrierten induktiven ElementArrangement with at least one inductive element integrated on a substrate
Die Erfindung betrifft eine Anordnung mit zumindest einem auf einem Substrat integrierten induktiven Element nach dem Oberbegriff des Anspruchs 1.The invention relates to an arrangement with at least one inductive element integrated on a substrate according to the preamble of claim 1.
Für monolithisch integrierte Schaltungen, deren Wirkungsweise auf Resonanzeffekten, Anpaßnetzwerken, induktiven Übertragern oder dgl. Beruhen, werden Induktivitäten hoher Güte benötigt. Die für Standardtechniken auf Siliziumbasis verwendeten Substrate aus elektrisch leitendem Halbleitermaterial bedin- gen wegen der Niederohmigkeit dieses Materials hohe Leistungsverluste oder eine niedrige Güte für eine durch zumindest eine Schicht aus elektrisch leitendem Material realisierte Induktivität. Für viele Anwendungen sind die Güten auf Standardsubstraten aus Silizium, die für gängige Mobilfunk- frequenzen unter 10 liegen, nicht ausreichend.High-quality inductors are required for monolithically integrated circuits whose mode of operation is based on resonance effects, matching networks, inductive transformers or the like. Because of the low resistance of this material, the substrates made of electrically conductive semiconductor material used for standard silicon-based technologies cause high power losses or a low quality for an inductance realized by at least one layer of electrically conductive material. For many applications, the grades on standard silicon substrates, which are below 10 for common mobile radio frequencies, are not sufficient.
Die Güte ist definiert durch L / Cj/R , wobei L den Induktivitätswert, C den Kapazitätswert und R den Widerstandswert bedeuten.The quality is defined by L / Cj / R, where L is the inductance value, C is the capacitance value and R is the resistance value.
Induktivitäten hoher Güte, insbesondere für Resonatoren, werden in der Regel "off chip", d.h. extern unter Verwendung von Substraten aus nicht leitendem, sondern semiisolierendem Halbleitermaterial, beispielsweise GaAs oder semiisolierendes Silizium, hergestellt, wobei sich Güten bis etwa 20 ergeben.High quality inductors, especially for resonators, are usually "off chip", i.e. produced externally using substrates made of non-conductive, but semi-insulating semiconductor material, for example GaAs or semi-insulating silicon, with grades of up to about 20 being obtained.
Eine davon abweichende Anordnung der eingangs genannten Art, bei der auf einer Oberfläche des gleichen Substrats eine elektrische Schaltung und eine mit der Schaltung verbundene Induktivität in Form einer eine Spule bildenden spiralig verlaufenden Schicht aus elektrisch leitendem Material integriert sind, ist aus J. Y. Chang et al.: "Large Suspended In- ductors on Silicon and Their Use in a 2-μm CMOS RF Ampli- fier", IEEE Electron Device Letters, Vol. 14, No. 5, 1993, S. 246-248 bekannt. Das Substrat dieser Anordnung weist im Bereich der senkrechten Projektion der Schicht aus dem elek- trisch leitenden Material auf das Substrat eine Aussparung mit einer in der Oberfläche des Substrats ausgebildeten Öffnung auf, über der die Schicht aus dem elektrisch leitenden Material hängend angeordnet ist. Diese Aussparung wirkt als ein im leitenden Substrat ausgebildetes lokales elektrisch isolierendes Gebiet, das die elektrisch isolierende Schicht und das Substrat elektrisch voneinander entkoppelt.A different arrangement of the type mentioned at the outset, in which an electrical circuit and an inductance connected to the circuit in the form of a spiral-forming layer of electrically conductive material forming a coil are integrated on a surface of the same substrate, is described in JY Chang et al. : "Large Suspended In- ductors on Silicon and Their Use in a 2-μm CMOS RF Amplifier ", IEEE Electron Device Letters, Vol. 14, No. 5, 1993, pp. 246-248. The substrate of this arrangement points in the area of the vertical projection the layer of the electrically conductive material on the substrate has a recess with an opening formed in the surface of the substrate, above which the layer of the electrically conductive material is suspended, This recess acts as a local electrically insulating layer formed in the conductive substrate Area that electrically decouples the electrically insulating layer and the substrate from one another.
Die Aussparung wird durch Ätzen des Substrats von dessen Oberfläche her bis zu einer bestimmten Tiefe im Substrat er- zeugt.The cutout is created by etching the substrate from its surface to a certain depth in the substrate.
Ähnliche Anordnungen gehen jeweils aus A. Rofougaran et al.: "A 900 MHz CMOS LC-Oscillator with Quadrature Outputs", ISSCC Technical Digest, 1996, S. 392-393, M. Parameswaran et al.: "A New Approach for the Fabrication of Micromechani- cal Structures", Sensors and Actuators, Vol. 19, 1989, S. 289-307 und Y. Sun et al . : "Monolithic Narrow-Band Active Inductors Using Suspended Membrane Passive Components on Silicon Substrate", EDMO, 1996, S. 79-83 hervor. Auch bei die- sen Anordnungen wird gegenüber einer elektrisch leitendenSimilar arrangements come from A. Rofougaran et al .: "A 900 MHz CMOS LC-Oscillator with Quadrature Outputs", ISSCC Technical Digest, 1996, pp. 392-393, M. Parameswaran et al .: "A New Approach for the Fabrication of Micromechanical Structures ", Sensors and Actuators, Vol. 19, 1989, pp. 289-307 and Y. Sun et al. : "Monolithic Narrow-Band Active Inductors Using Suspended Membrane Passive Components on Silicon Substrate", EDMO, 1996, pp. 79-83. These arrangements are also compared to an electrically conductive one
Schicht eine Aussparung im Substrat durch Ätzen des Substrats von dessen Oberfläche her bis zu einer bestimmten Tiefe im Substrat erzeugt.Layer created a recess in the substrate by etching the substrate from its surface to a certain depth in the substrate.
Aufgabe der Erfindung ist es, eine Anordnung der eingangs genannten Art anzugeben, die besonders einfach hergestellt werden kann.The object of the invention is to provide an arrangement of the type mentioned at the outset, which can be manufactured particularly easily.
Diese Aufgabe wird durch die im kennzeichnenden Teil des An- spruchs 1 angegebenen Merkmale gelöst. Dieser Lösung liegt der Gedanke zugrunde, die Aussparung nicht von der Oberfläche des Substrats, die der elektrisch isolierenden Schicht zugekehrt ist, sondern von einer von dieser Oberfläche abgekehrten rückseitigen Oberfläche des Substrats her zu erzeugen. Demgemäß ist bei der erfindungsgemäßen Anordnung im Gegensatz zu den bekannten Anordnungen der genannten Art in einer von der Oberfläche des Substrats abgekehrten rückseitige Oberfläche des Substrats eine Öffnung ausgebildet .This object is achieved by the features specified in the characterizing part of claim 1. This solution is based on the idea of not producing the cutout from the surface of the substrate which faces the electrically insulating layer, but rather from a rear surface of the substrate which faces away from this surface. Accordingly, in the arrangement according to the invention, in contrast to the known arrangements of the type mentioned, an opening is formed in a rear surface of the substrate facing away from the surface of the substrate.
Die erfindungsgemäße Aussparung ist besonders einfach und ohne wesentlichen Eingriff in Prozesstechniken herstellbar, die bei der Erzeugung einer Struktur auf der von der rückseitigen Oberfläche abgekehrten Oberfläche des Substrats verwendet werden. Insbesondere kann die erfindungsgemäße Anordnung vorteilhafterweise in einer Standard-Siliziumprozesstechnik unter Beibehaltung der bei dieser Technik verwendeten Materialien und/oder Schichtfolgen und keiner sonstigen und ohne wesentlichen Eingriffe in diese Prozesstechnik hergestellt werden.The recess according to the invention can be produced particularly easily and without substantial intervention in process techniques which are used in the production of a structure on the surface of the substrate facing away from the rear surface. In particular, the arrangement according to the invention can advantageously be produced in a standard silicon process technology while maintaining the materials and / or layer sequences used in this technology and with no other and without substantial interventions in this process technology.
Der einzige Aufwand besteht in der gezielten und den sonstigen Prozess nicht beeinflussenden Herstellung der erfindungsgemäßen Aussparung.The only effort is to produce the recess according to the invention in a targeted manner and which does not influence the other process.
Die Herstellung der erfindungsgemäßen Aussparung kann durch Ätzen des Halbleitermaterials, vorteilhafterweise durch anisotropes Ätzen eines dafür geeigneten Materials und/oder Ätzmittels, vorzugsweise Silizium und KOH als Ätzmittel, vorge- nommen werden.The recess according to the invention can be produced by etching the semiconductor material, advantageously by anisotropically etching a suitable material and / or etchant, preferably silicon and KOH as the etchant.
Demgemäß ist bei einer bevorzugten und vorteilhaften erfindungsgemäßen Anordnung die Aussparung eine durch Ätzen des Substrats von dessen rückseitiger Oberfläche her erzeugte Aussparung. Bei einer im Hinblick auf die Entkopplung der Schicht aus dem elektrisch leitenden Material und des Substrats voneinander besonders vorteilhaften erfindungsgemäßen Anordnung weist die Aussparung in der Oberfläche des Substrats, die den Schichten aus dem elektrisch isolierenden und elektrisch leitenden Material zugekehrt ist, eine Öffnung auf, die von der Schicht aus elektrisch isolierendem Material insbesondere vollständig abgedeckt ist.Accordingly, in a preferred and advantageous arrangement according to the invention, the cutout is a cutout produced by etching the substrate from its rear surface. In an arrangement according to the invention which is particularly advantageous with regard to the decoupling of the layer made of the electrically conductive material and the substrate from one another, the cutout in the surface of the substrate which faces the layers made of the electrically insulating and electrically conductive material has an opening which is in particular completely covered by the layer of electrically insulating material.
In diesem Fall erstreckt sich die Aussparung vorteilhafterweise und im Gegensatz zu den bekannten Anordnungen der genannten Art durch das ganze Substrat zwischen dessen beiden voneinander abgekehrten Oberflächen. Dadurch ist eine stärkere Entkopplung zwischen der Schicht aus elektrisch leitendem Material und dem Substrat als bisher ermöglicht, da imIn this case, the recess advantageously extends and, in contrast to the known arrangements of the type mentioned, through the entire substrate between its two surfaces facing away from one another. This allows a stronger decoupling between the layer of electrically conductive material and the substrate than before, because in
Bereich der Projektion der Schicht aus dem elektrisch leitenden Material auf das Substrat das Substratmaterial vollständig fehlen kann.Area of projection of the layer of the electrically conductive material onto the substrate, the substrate material can be completely absent.
Eine erfindungsgemäße Anordnung kann auch bei Verwendung von hoch leitendem, d.h. eine Leitfähigkeit von weniger als 8Ω cm aufweisenden Halbleitermaterial, des Substrats vorteilhafterweise mit einer Güte von mehr als 10 auf besonders einfache Weise hergestellt werden.An arrangement according to the invention can also be used when using highly conductive, i.e. having a conductivity of less than 8Ω cm semiconductor material, the substrate advantageously with a quality of more than 10 can be produced in a particularly simple manner.
Bevorzugterweise ist eine erfindungsgemäße Anordnung so ausgebildet, daß das induktive Element das induktive Element mit einer elektrischen Schaltung verbunden ist, die auf der den Schichten aus dem elektrisch isolierenden Material und dem elektrisch leitenden Material zugekehrten Oberfläche desAn arrangement according to the invention is preferably designed such that the inductive element is connected to an electrical circuit on the surface of the layer facing the layers of the electrically insulating material and the electrically conductive material
Substrats integriert ist. Durch diese Ausgestaltung ist vorteilhafterweise eine monolithisch integrierte elektrische Schaltung mit einem induktiven Element einer hohen Güte von mehr als 10 auf einem leitenden Substrat geschaffen, wobei das Halbleitermaterial des Substrats hoch leitend sein kann. Dabei kann die integrierte Schaltung vorteilhafterweise ganz mit herkömmlichen Prozesstechniken hergestellt sein, in die wegen der Herstellung der Aussparung nicht eingegriffen zu werden braucht.Substrate is integrated. This configuration advantageously creates a monolithically integrated electrical circuit with an inductive element of a high quality of more than 10 on a conductive substrate, it being possible for the semiconductor material of the substrate to be highly conductive. The integrated circuit can advantageously be produced entirely using conventional process techniques, in which need not be intervened because of the manufacture of the recess.
Bei einer bevorzugten Ausgestaltung der erfindungsgemäßen An- OrdnungIn a preferred embodiment of the arrangement according to the invention
- besteht das Halbleitermaterial aus elektrisch leitendem Silizium und das elektrisch isolierende Material aus Siθ2 und/oder- The semiconductor material consists of electrically conductive silicon and the electrically insulating material made of SiO 2 and / or
- weist das elektrisch leitende Material ein Metall auf und/oder- The electrically conductive material has a metal and / or
- ist zwischen der Schicht aus dem elektrisch leitenden Material und der Schicht aus dem elektrisch isolierenden Material zumindest eine weitere Schicht aus einem vom elektrisch isolierenden Material verschiedenen dielektrischen Material an- geordnet.- At least one further layer made of a dielectric material different from the electrically insulating material is arranged between the layer made of the electrically conductive material and the layer made of the electrically insulating material.
Die erfindungsgemäße Anordnung ist gut für einen Einsatz in HF-Frontends geeignet.The arrangement according to the invention is well suited for use in HF front ends.
Die Erfindung wird in der nachfolgenden Beschreibung anhand der Figuren beispielhaft näher erläutert. Es zeigen, jeweils im Querschnitt senkrecht zur Oberfläche eines Substrats, schematisch und nicht maßstäblich:The invention is explained in more detail in the following description using the figures as an example. They show, each in cross section perpendicular to the surface of a substrate, schematically and not to scale:
Figur 1 eine Ausgangsstufe eines Verfahrens zur Herstellung einer erfindungsgemäßen Anordnung,FIG. 1 shows an output stage of a method for producing an arrangement according to the invention,
Figur 2 eine erste Zwischenstufe des Verfahrens, bei der auf einer rückseitigen Oberfläche eines Substrats eine Ätzmaske mit einer die Stelle einer Aussparung im Substrat definierenden Maskenöffnung aufgebracht ist, undFIG. 2 shows a first intermediate stage of the method, in which an etching mask with a mask opening defining the location of a recess in the substrate is applied to a rear surface of a substrate, and
Figur 3 eine Endstufe des Verfahrens, welche ein Ausfüh- rungsbeispiel der erfindungsgemäßen Anordnung bildet . In den Figuren sind ein induktives Element mit 1, eine Schicht aus dem elektrisch leitenden Material dieses Elements 1 mit 10, ein Substrat aus Halbleitermaterial mit 2, eine der Schicht 10 zugekehrte Oberfläche des Substrats 2 mit 20, eine zwischen der Oberfläche 20 und der Schicht 10 angeordnete Schicht aus elektrisch isolierendem Material mit 3 und eine von der Oberfläche 20 des Substrats 2 abgekehrte Oberfläche des Substrats mit 20' bezeichnet.3 shows a final stage of the method, which forms an exemplary embodiment of the arrangement according to the invention. In the figures, an inductive element with 1, a layer made of the electrically conductive material of this element 1 with 10, a substrate made of semiconductor material with 2, a surface of the substrate 2 with 20 facing the layer 10, one between the surface 20 and the layer 10 arranged layer of electrically insulating material with 3 and a surface of the substrate facing away from the surface 20 of the substrate 2 with 20 '.
Die Schnittdarstellungen in den Figuren sind jeweils so, daß die Oberfläche 20 des Substrats 2 vertikal zur Zeichenebene angeordnet ist.The sectional representations in the figures are each such that the surface 20 of the substrate 2 is arranged vertically to the plane of the drawing.
Um den beträchtlichen Vorteil der Erfindung deutlich vor Au- gen zu führen, ist bereits bei der Ausgangsstufe nach Figur 1 des Verfahrens angenommen, daß auf der Oberfläche 20 des Substrats 2 eine elektrische Schaltung 7 integriert ist, die durch eine oder mehrere herkömmliche Prozesstechniken hergestellt worden ist und elektrisch mit der Schicht 10 aus dem elektrischen leitenden Material verbunden ist.In order to clearly demonstrate the considerable advantage of the invention, it is already assumed in the output stage according to FIG. 1 of the method that an electrical circuit 7 is integrated on the surface 20 of the substrate 2, which circuit 7 has been produced by one or more conventional process techniques is and is electrically connected to the layer 10 of the electrically conductive material.
Die Schaltung 7 kann beispielsweise ein Verstärker und/oder Oszillator, wie er aus den oben angegebenen Dokumenten hervorgeht, und/oder eine andere aktive oder passive Schaltung sein. Die Schicht 10 aus dem elektrischen leitenden Material kann beispielsweise eine zur Oberfläche 20 des Substrats 2 parallele ebene Spirale sein, die eine elektrische Spule bildet.The circuit 7 can be, for example, an amplifier and / or oscillator, as can be seen from the documents specified above, and / or another active or passive circuit. The layer 10 made of the electrically conductive material can be, for example, a flat spiral parallel to the surface 20 of the substrate 2, which forms an electrical coil.
Auf die rückseitige Oberfläche 20' des Substrats 2 der Ausgangsstufe nach Figur 1 wird eine gegen ein das Halbleitermaterial angreifendes Ätzmittel resistente Ätzmaske aufgebracht, die eine Maskenöffnung aufweist.An etching mask which is resistant to an etchant attacking the semiconductor material and has a mask opening is applied to the rear surface 20 'of the substrate 2 of the output stage according to FIG.
Danach ist die in der Figur 2 dargestellte Zwischenstufe entstanden, bei der diese aufgebrachte Ätzmaske mit 8 und diese Maskenöffnung mit 81 bezeichnet ist. Die Maskenöffnung 81 liegt vorzugsweise im Bereich 11 einer Projektion der Schicht 10 aus dem elektrisch leitenden Material auf die rückseitige Oberfläche 20' des Substrat 2. Die Projektion ist durch zwei gestrichelte Linien 101 und 102 angedeutet, welche die Schicht 10 sowie den Bereich 11 beidsei- tig begrenzen und vorzugsweise die zur Oberfläche 20 des Substrats 2 vertikalen Linien einer senkrechten Projektion der Schicht 10 auf diese Oberfläche 20 sind.Thereafter, the intermediate stage shown in FIG. 2 was created, in which this applied etching mask is designated 8 and this mask opening 81. The mask opening 81 is preferably located in the region 11 of a projection of the layer 10 made of the electrically conductive material onto the rear surface 20 'of the substrate 2. The projection is indicated by two dashed lines 101 and 102 which show the layer 10 and the region 11 on both sides. limit and are preferably the vertical lines to the surface 20 of the substrate 2 of a perpendicular projection of the layer 10 onto this surface 20.
Die Öffnung 81 kann innerhalb der beiden Linien 101 und 102 liegen, von diesen begrenzt sein oder größer als ein Abstand a zwischen diesen Linien 101 und 102 sein.The opening 81 can lie within the two lines 101 and 102, be delimited by them or be greater than a distance a between these lines 101 and 102.
Danach wird das Substrat 2 von der in der Maskenöffnung 81 freiliegenden und den Bereich 11 der Projektion enthaltenden rückseitigen Oberfläche 20' mit dem Ätzmittel in Richtung zu der von dieser Oberfläche 20' abgekehrten Oberfläche 20 des Substrats 2 geätzt. Dieser Ätzschritt wird vorzugsweise so- lange ausgeführt, bis das Substrat 2 über seine ganze Dicke D, d.h. den Abstand zwischen der rückseitigen Oberfläche 20' und der Oberfläche 20 abgeätzt ist.The substrate 2 is then etched from the rear surface 20 ′, which is exposed in the mask opening 81 and contains the region 11 of the projection, with the etchant in the direction of the surface 20 of the substrate 2 facing away from this surface 20 ′. This etching step is preferably carried out until the substrate 2 over its entire thickness D, i.e. the distance between the rear surface 20 'and the surface 20 is etched off.
Nach Entfernung der Maske 8 ist die in der Figur 3 darge- stellte Endstufe des Verfahrens erreicht, welche das Ausführungsbeispiel der erfindungsgemäßen Anordnung bildet.After removal of the mask 8, the final stage of the method shown in FIG. 3, which forms the exemplary embodiment of the arrangement according to the invention, is reached.
Gemäß diesem Beispiel weist das Substrat 2 die durch das Ätzen erzeugte die Aussparung 21 auf, welche die in der von der Oberfläche 20 des Substrats 2 abgekehrten rückseitigen Oberfläche 20' des Substrats 2 die Öffnung 210 und überdies die in der der Schicht 3 aus dem elektrisch isolierenden Material zugekehrten Oberfläche 20 des Substrats 2 ausgebildete Öffnung 211 aufweist, die von dieser Schicht 3 vollständig abge- deckt ist. Im Bereich 11 der Projektion liegt kein Halbleitermaterial des Substrats 2 mehr vor.According to this example, the substrate 2 has the recess 21 produced by the etching, which has the opening 210 in the rear surface 20 ′ of the substrate 2 facing away from the surface 20 of the substrate 2 and moreover that in the layer 3 from the electrical Isolating material facing surface 20 of the substrate 2 formed opening 211, which is completely covered by this layer 3. In the region 11 of the projection, there is no longer any semiconductor material of the substrate 2.
Gemäß einem konkreten Beispiel werden auf der Oberfläche 20 eines Substrats 2 in Form einer Scheibe aus Silizium mittels einer Standard-Prozessierung die integrierte Schaltung 7 und das elektrisch mit dieser Schaltung 7 verbundene induktive Element 1 erzeugt. Die elektrisch isolierende Schicht 3 besteht bei dieser Prozessierung aus SiÖ2-According to a specific example, the integrated circuit 7 and the inductive element 1 electrically connected to this circuit 7 are produced on the surface 20 of a substrate 2 in the form of a disk made of silicon by means of standard processing. In this processing, the electrically insulating layer 3 consists of SiO 2
Danach wird die Scheibe 2 durch Schleifen von der von der Oberfläche 20 abgekehrten rückseitigen Oberfläche 20' her so weit wie möglich gedünnt. Diese Technik wird heute routinemäßig vor einer Montage von integrierten Schaltungen angewen- det. Scheiben 2 aus Silizium mit einem Durchmesser von beispielsweise 150 mm werden dabei typischerweise von einer Dik- ke von etwa 675 μm auf eine geringere Dicke von etwa 180 μ abgeschliffen.Thereafter, the disk 2 is thinned as much as possible by grinding from the rear surface 20 ′ facing away from the surface 20. This technology is routinely used today before assembly of integrated circuits. Disks 2 made of silicon with a diameter of 150 mm, for example, are typically ground down to a thickness of about 675 μm to a smaller thickness of about 180 μm.
Die Herstellung der Aussparung 21 in dieser Scheibe 2 kann durch Ätzen mit Kalilauge KOH erfolgen, die Silizium sehr selektiv, beispielsweise bis zu 1000:1 im Vergleich zu dem Siθ2 der Schicht 3 ätzt. Daher kann die Schicht 3 bei der Ätzung der Scheibe 2 zur Herstellung der Aussparung 21 als eine Ätz- stoppschicht verwendet werden.The recess 21 in this disk 2 can be produced by etching with potassium hydroxide solution KOH, which etches silicon very selectively, for example up to 1000: 1 in comparison to the SiO 2 of layer 3. Therefore, the layer 3 can be used as an etching stop layer in the etching of the pane 2 to produce the recess 21.
Sobald die Ätzung durch die Schicht 3 in Richtung vertikal zur Oberfläche 20 der Scheibe 2 gestoppt wird, erfolgt auch in Richtung lateral zu dieser Oberfläche 20 kein Ätzabtrag mehr, da KOH in Silizium nur pyramidenförmige Ätzgruben mit den (111) -Flächen als Begrenzung erzeugt.As soon as the etching is stopped by the layer 3 in the direction vertical to the surface 20 of the pane 2, no etching removal takes place in the direction laterally to this surface 20 either, since KOH in silicon only produces pyramid-shaped etching pits with the (111) faces as a boundary.
Die Technik einer Ätzung eines Substrats aus Silizium von einer rückseitigen Oberfläche her mittels einer Maske wird seit längerer Zeit unter Produktionsbedingungen in der vom Gegenstand der vorliegenden Erfindung weit entfernten Bulk- Mikromechanik verwendet. Diese gibt keine Anregungen oder Hinweise in bezug auf diese Erfindung, vielmehr weist umgekehrt die Erfindung auf diese Mechanik hin.The technique of etching a silicon substrate from a rear surface by means of a mask has been used for a long time under production conditions in bulk micromechanics, which is far from the object of the present invention. This gives no suggestions or Notes with regard to this invention, rather, conversely, the invention refers to this mechanism.
Ein besonderer Vorteil der erfindungsgemäßen Anordnung ist darin zu sehen, daß sich das induktive Element 1 in Schichten aus elektrisch leitendem und dielektrischem Material befinden kann, die auf der eine Standard-Transistorisolation bildenden Schicht 3 aus elektrisch isolierendem Material auf herkömmliche Weise und vor der Erzeugung der Aussparung 21 erzeugt werden können.A particular advantage of the arrangement according to the invention can be seen in the fact that the inductive element 1 can be located in layers of electrically conductive and dielectric material, which are formed on the layer 3 of electrically insulating material which forms a standard transistor insulation in a conventional manner and before the generation of the Recess 21 can be generated.
Beispielsweise ist auf der Schicht 3 aus elektrisch isolierendem Material eine Schichtfolge aus dielektrischen Schichten 4 bis 5 ausgebildet, zwischen denen Schichten 10 und 71 aus Metall angeordnet sind.For example, a layer sequence of dielectric layers 4 to 5 is formed on the layer 3 made of electrically insulating material, between which layers 10 and 71 made of metal are arranged.
Die Schicht 71 ist zwischen den Schichten 4 und 5 aus jeweils dielektrischem Material angeordnet und bildet einen Teil einer elektrischen Verbindung 70, welche die zwischen den Schichten 5 und 6 aus jeweils dielektrischem Material angeordnete Schicht 10 des induktiven Elements 1 mit der Schaltung 7 verbindet.Layer 71 is arranged between layers 4 and 5, each made of dielectric material, and forms part of an electrical connection 70, which connects layer 10 of inductive element 1, arranged between layers 5 and 6, each made of dielectric material, to circuit 7.
Die elektrische Verbindung 70 weist neben der Schicht 71 ei- nen elektrisch leitenden Durchgang 72 durch die dielektrische Schicht 4 auf, der die Schicht 71 mit der Schaltung 7 verbindet, und einen elektrisch leitenden Durchgang 73 durch die dielektrische Schicht 5, der die Schicht 71 mit der Schicht 10 verbindet. In addition to layer 71, electrical connection 70 has an electrically conductive passage 72 through dielectric layer 4, which connects layer 71 to circuit 7, and an electrically conductive passage 73 through dielectric layer 5, which also includes layer 71 the layer 10 connects.

Claims

Patentansprüche claims
1. Anordnung mit zumindest einem passiven induktiven Element (1) , das wenigstens eine auf einem Substrat (2) aus Halblei- termaterial integrierte Schicht (10) aus elektrisch leitendem Material aufweist, wobei1. Arrangement with at least one passive inductive element (1) which has at least one layer (10) made of electrically conductive material integrated on a substrate (2) made of semiconductor material, wherein
- zwischen der Schicht (10) aus dem elektrisch leitenden Material und dem Substrat (2) eine Schicht (3) aus elektrisch isolierendem Material vorhanden ist, die flächig auf einer der Schicht (10) aus dem elektrisch leitenden Material zugekehrten Oberfläche (20) des Substrats (2) angeordnet ist, wobei- Between the layer (10) made of the electrically conductive material and the substrate (2) there is a layer (3) made of electrically insulating material, the surface (20) of the surface (20) facing the electrically conductive material Substrate (2) is arranged, wherein
- das Halbleitermaterial des Substrats (2) elektrisch leitend ist, und wobei, - das Substrat (2) eine Aussparung (21) im Bereich einer Projektion der Schicht (10) aus dem elektrisch leitenden Material auf das Substrat (2) aufweist, dadurch gekennzeichnet, daß die Aussparung (21) in einer von der Oberfläche (20) des Substrats (2) abgekehrten rückseitigen Oberfläche (20') des Substrats (2) eine Öffnung (210) aufweist.- The semiconductor material of the substrate (2) is electrically conductive, and wherein, - The substrate (2) has a recess (21) in the region of a projection of the layer (10) made of the electrically conductive material onto the substrate (2), characterized that the recess (21) has an opening (210) in a rear surface (20 ') of the substrate (2) facing away from the surface (20) of the substrate (2).
2. Anordnung nach einem der vorhergehenden Ansprüche, wobei die Aussparung (21) eine durch Ätzen des Substrats (2) von dessen rückseitiger Oberfläche (20' ) her erzeugte Aussparung ist.2. Arrangement according to one of the preceding claims, wherein the recess (21) is a recess produced by etching the substrate (2) from its rear surface (20 ').
3. Anordnung nach Anspruch 1 oder 2, wobei die Aussparung (21) in der Oberfläche (20) des Substrats (2), die der Schicht (10) aus dem elektrisch leitenden Material zugekehrt ist, eine Öffnung (211) aufweist, die von der Schicht (3) aus dem elektrisch isolierenden Material abgedeckt ist.3. Arrangement according to claim 1 or 2, wherein the recess (21) in the surface (20) of the substrate (2), which faces the layer (10) made of the electrically conductive material, has an opening (211) which from the layer (3) is covered from the electrically insulating material.
4. Anordnung nach Anspruch 3, wobei die Öffnung (211) in der einen Oberfläche (20) des Substrats (2) vollständig von der4. Arrangement according to claim 3, wherein the opening (211) in one surface (20) of the substrate (2) completely from the
Schicht (3) aus elektrisch isolierendem Material abgedeckt ist . Layer (3) made of electrically insulating material is covered.
5. Anordnung nach einem der vorhergehenden Ansprüche, wobei das Halbleitermaterial des Substrats (2) aus elektrisch leitendem Silizium und die elektrisch isolierende Schicht (3) aus Siθ2 besteht.5. Arrangement according to one of the preceding claims, wherein the semiconductor material of the substrate (2) consists of electrically conductive silicon and the electrically insulating layer (3) consists of SiO 2.
6. Anordnung nach einem der vorhergehenden Ansprüche, wobei die elektrisch leitende Schicht (10) ein Metall aufweist.6. Arrangement according to one of the preceding claims, wherein the electrically conductive layer (10) comprises a metal.
7. Anordnung nach einem der vorhergehenden Ansprüche, wobei zwischen der Schicht (10) aus dem elektrisch leitenden Material und der Schicht (3) aus dem elektrisch isolierenden Material zumindest eine weitere Schicht (4, 5) aus einem vom elektrisch isolierenden Material verschiedenen dielektrischen Material angeordnet ist.7. Arrangement according to one of the preceding claims, wherein between the layer (10) made of the electrically conductive material and the layer (3) made of the electrically insulating material at least one further layer (4, 5) made of a dielectric material different from the electrically insulating material is arranged.
8. Anordnung nach einem der vorhergehenden Ansprüche, wobei das induktive Element (1) mit einer elektrischen Schaltung (7) verbunden ist, die auf der den Schichten (3, 10) aus dem elektrisch isolierenden Material und dem elektrisch leitenden Material zugekehrten Oberfläche (20) des Substrats (2) integriert ist. 8. Arrangement according to one of the preceding claims, wherein the inductive element (1) is connected to an electrical circuit (7) which on the layers (3, 10) facing the electrically insulating material and the electrically conductive material surface (20 ) of the substrate (2) is integrated.
PCT/DE1999/003341 1998-10-21 1999-10-18 Arrangement with at least one integrated inductive element on a substrate WO2000024042A1 (en)

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