561486 五 經濟部智慧財產局員工消費合作社印製 A7 B7 、發明說明（1 ) 本發明係關於一種一次抹消非揮發性記憶體的多個位元 之方法以及包含非揮發性記憶體之積體電路。 美國專利申請案第5,844,842號揭示快閃記憶體EEPROM裝 置。该兄憶體含有記憶體電晶體矩陣經織成爲多行電晶體 ’其主電泥通道共通連結至一該行的位元線。同一列的電 晶體之fe制端係連結在一起。一快閃記憶體中，資訊係經 由調整記憶體電晶體的閾値而儲存。 典型兄憶體電晶體爲帶有浮動閘的場效電晶體，其閾値 可經由注入電荷載子或由浮動閘去除電荷載子調整。最初 全部5己憶體電晶體的閾値係在第一位準，稱作抹消位準， 表示第一邏輯値。若不同的邏輯値必須儲存記憶體的某個 位置，則對應該關聯記憶體位置的電晶體閾値必須變動。 1己憶體將此等閾値變動至第二位準，所謂的程式規劃位準 。如此稱作程式規劃。 凟取作業中’由一行選出一電晶體且感測該選定電晶體 的閾値。用於此項目的，記憶體對選定的電晶體供給程式 規劃與抹消位準間的一種閘極-源極電壓。結果依據電晶體 閾値是否經過程式規劃而定，選定的電晶體之主電流通道 將導通或不導通電流。連結至同一行的其它電晶體被阻止 輸送電流給該位元線。結果儲存於選定電晶體的邏輯値可 由流經位元線的電流決定。 1己憶體已經使用資訊程式規劃後，於儲存不同的邏輯資 訊之前該記憶體須經抹消。於快閃記憶體中，記憶體電晶 體之一區塊例如由數列矩陣組成的一扇區係整個抹消。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) ----I---訂--------I · 561486561486 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the invention description (1) The present invention relates to a method for erasing multiple bits of non-volatile memory at one time, and an integrated circuit including non-volatile memory . U.S. Patent Application No. 5,844,842 discloses a flash memory EEPROM device. The memory cell contains a memory transistor matrix that is woven into multiple rows of transistors. The main electrode channel is connected to a bit line of the row in common. The fe terminals of the transistors in the same row are connected together. In a flash memory, the information is stored by adjusting the threshold of the memory transistor. A typical body transistor is a field-effect transistor with a floating gate, and its threshold can be adjusted by injecting charge carriers or removing charge carriers by the floating gate. Initially, the thresholds of all five memory transistors are at the first level, which is called the erasing level, which indicates the first logic level. If different logical volumes must store a certain location in the memory, the transistor threshold corresponding to the memory location must be changed. 1 Ji Yi has changed these thresholds to the second level, the so-called programming level. This is called programming. In the capturing operation, a transistor is selected from one line and the threshold value of the selected transistor is sensed. For this project, a gate-source voltage between memory programming and erasing the selected transistor. The result depends on whether the transistor threshold 经过 is programmed or not. The main current channel of the selected transistor will conduct or not conduct current. Other transistors connected to the same row are prevented from delivering current to the bit line. The logic volume of the result stored in the selected transistor can be determined by the current flowing through the bit line. 1 After the memory has been planned using the information program, the memory must be erased before storing different logical information. In flash memory, a block of the memory electrical crystal, such as a sector composed of a series of matrixes, is completely erased. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love) (Please read the precautions on the back before filling this page) ---- I --- Order -------- I 561486
/如先前技術所述，要緊地，全部記憶體電晶 心分反向變動至抹消位準。爲確料成此項 = 體於重複步骤進行抹消。各步驟中，㈣㈣㈣外^ =區的全郅電晶M。於各步驟後，記憶體連續 的不同記憶體電晶體讀取資訊。抹消步驟重複至全部電〒 體的讀取邏輯資訊位準對應抹消位準爲止。 包明 本發明之一目的係縮短由記憶體抹消資訊所需時間。 申請專利範圍第1項說明根據本發明之抹消資訊之方法' 根據本發明，同-行的多個電晶體（較佳構成抹消扇區部分 的全部電晶體）集體被讀出而決定是否已經被適當抹消。此 係與先前技術相反，先前技術中同一行的電晶體係逐一被 讀出。同一時間經由選擇同一行多於一個電晶體進行決定 。結果所得由全部選定電晶體流經位元線的集合電流用於 決定該1己憶體的邏輯讀出値，表示電流是否於預定範圍（較 佳電流範圍對應單一儲存電晶體於正常使用時可能的邏輯 狀態之一）。依據邏輯讀取値而定，決定是否重複進行抹消。 較佳數行位元線彼此作傳導連結。然後由數條位元線所 得合併集合電流用以決定邏輯讀出値。此點特別可用於下 述記憶體，其中程式規劃資料的正常讀出涉及連結一感測 放大器至多行的位元線之一選定位元線。此種記憶體中， 對多行僅設置單一感測放大器。經由集合連結該等行的位 元線至感測放大器，可使用該可利用的感測放大器同時測 試多行是否被適當抹消。 較佳於抹消扇區的一行或多行之全部電晶體被共同選用 5- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) Γ裝/ As described in the prior art, it is important that all the memory transistor cores change in the opposite direction to the erasure level. To make sure this is correct = repeat the steps to erase. In each step, the outer unitary crystal M of the outer region ^ = region. After each step, different memory transistors in the memory read information continuously. The erasing step is repeated until the read logic information level of all the electronic bodies corresponds to the erasing level. It is an object of the present invention to reduce the time required for erasing information from memory. Item 1 of the scope of patent application describes the method of erasing information according to the present invention. 'According to the present invention, multiple transistors in the same line (preferably all transistors constituting the erasing sector part) are read out collectively to determine whether they have been deleted. Erase appropriately. This system is contrary to the prior art, in which the transistor systems of the same row are read out one by one. The decision is made at the same time by selecting more than one transistor in the same row. The result is that the collective current flowing through the bit line from all selected transistors is used to determine the logical readout of the memory, indicating whether the current is within a predetermined range (preferably the current range corresponds to the possibility of a single storage transistor under normal use) One of the logical states). Depending on the logic read, it is determined whether to repeat the erase. Preferably, the bit lines are conductively connected to each other. The combined set current obtained from several bit lines is then used to determine the logical readout. This point is particularly applicable to the following memory, in which the normal readout of programming data involves selecting a positioning element line by connecting one sense line to one of a plurality of bit lines. In such a memory, only a single sense amplifier is provided for multiple rows. By connecting the bit lines of the rows to the sense amplifier, the available sense amplifier can be used to test whether multiple rows are properly erased at the same time. All the transistors in one or more rows that are better than erasing the sector are used together. 5- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) (Please read the precautions on the back before filling (This page) Γ 装
Γ ΜΜ I I < a^i mmmme ϋ n .I ϋ I 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消费合作社印製 561486 A7 B7 五、發明說明（3 ) 來測試是否已經被適當抹消。藉此方式可於一次讀取作業 進行整個扇區的測試。 本發明背後的構想是集合電流提供足夠資訊來決定於選 定電晶體之任一者是否進行額外抹消步驟。用於決定抹消 步驟目的，無需檢驗電流是否來自分開個別電晶體。 一具體實施例中，此處閾電壓於抹消期間升高，一旦電 晶體已經被充分抹消，則選定的電晶體最終無需抽取任何 有意義電流。以充分抹消爲例，流經複數選定電晶體的集 合電流遠低於流經尚未被抹消的單一電晶體的電流。 若任一電晶體未被充分抹消，則較大電流流經位元線。 此種電流可與充分抹消後流經位元線的無意義電流區別， 較佳使用感測電路區別，感測電路正常用於區別個別電晶 體的抹消狀態及程式規劃狀態。若流過太多電流，則須進 行額外抹消步驟。 若有多於一個電晶體未被充分抹消，則將抽取較大電流 ，結果導致相同回應··進行額外抹消步驟。因此爲了決定 有關額外抹消步驟，決定集合電流是否大於預定値即足。 另一例中，閾電壓於抹消期間下降。此種情況下，一旦 電晶體被充分抹消，則電晶體將抽取電流。抹消係以數步 驟進行，而於任何電晶體的閾値被過度抹消之前停止進行 各步驟。用於此項目的，外加以個別電晶體正常讀出期間 更低的閘極-源極電壓集體外加至各電晶體。 只要並無任何電晶體被過度抹消，則將有無意義電流流 動，該電流係小於正常讀出期間於抹消態流經個別電晶體 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----------· --------訂 *-------- (請先閱讀背面之注意事項再填寫本頁) 561486 A7 B7 五、發明說明（ 的電流。此種情況下，重複進行抹消。當有至少一兩田 見日EI體 有變成過度抹消的威脅時，不再流過電流且不再進行額外 抹消步骤。若有多個電晶體變成過度抹消的威脅，則單純 爲較大電流典需進行抹消。因此用於決定有關額外抹消+ 驟用途，決定集合電流是否小於預定値即可。 圖式之簡單説明 此等及其它根據本發明之方法及電路之優異特點將許非 限制性實例使用下列各圖説明。 圖1顯示帶有記憶體的電路 圖2顯示用於由記憶體讀取的信號 圖3顯示流程圖説明抹消作業 圖4顯示用於證實記憶體抹消之信號 圖5顯示用於證實記憶體抹消之進一步信號 圖6顯示位元線感測電路。 發明之詳細説明 圖1顯示帶有記憶體的電路。電路含有一記憶體矩陣帶有 ^行5己憶體行10 ’ 11 ’ 12，一字線解碼器1 4，多條字線 140，141，一位元線感測電路1 6，一源極/汲極電壓供應電 路1 8及一控制電路1 9。 各行1 0，1 1，1 2含有一位元線103，113，123及多個浮 動閘記憶體電晶體101，102各自帶有一浮動閘（於一行1 〇僅 顯示二記憶體電晶體，但於各行1 0，1 1，1 2通常存在有更 多電晶體例如256或4096個電晶體）。各行1 〇，1 1，1 2之記 憶體電晶體101，102之汲極被集體連結至該行的位元線103 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) .裝 經濟部智慧財產局員工消費合作社印製 561486Γ ΜΜ II < a ^ i mmmme ϋ n .I ϋ I Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 561486 A7 B7 V. Invention Description (3) Erase appropriately. In this way, the entire sector can be tested in one read job. The idea behind the present invention is to gather enough current to provide enough information to decide whether or not to perform an additional erase step on any one of the selected transistors. For the purpose of determining the erase step, there is no need to check whether the current comes from separate individual transistors. In a specific embodiment, the threshold voltage is increased during the erasing period. Once the transistor has been sufficiently erased, the selected transistor does not need to draw any meaningful current in the end. Taking full erasure as an example, the collective current flowing through a plurality of selected transistors is much lower than the current flowing through a single transistor that has not been erased. If any transistor is not sufficiently erased, a larger current flows through the bit line. This kind of current can be distinguished from the meaningless current flowing through the bit line after being fully erased. It is better to use a sensing circuit to distinguish. The sensing circuit is normally used to distinguish the erasing status and programming status of individual electric crystals. If too much current is flowing, an additional erase step is required. If more than one transistor is not fully erased, a larger current will be drawn, resulting in the same response ... An additional erase step is performed. Therefore, in order to determine the additional erasing step, it is determined whether the collective current is larger than a predetermined value. In another example, the threshold voltage decreases during the erasing period. In this case, once the transistor is sufficiently erased, the transistor will draw current. The erasure is performed in several steps, and the steps are stopped before the threshold of any transistor is erased excessively. For this project, a lower gate-source voltage is applied to each transistor collectively during the normal readout period of individual transistors. As long as no transistor is over-erased, there will be a meaningless current flowing. This current is smaller than the individual transistor in the erased state during normal readout. 6- This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ---------- · -------- Order * -------- (Please read the notes on the back before filling this page) 561486 A7 B7 V. Description of the invention (The current of (). In this case, the erasure is repeated. When there is a threat of excessive erasure of at least one or two fields, the current will no longer flow and no additional erasure steps will be performed. If multiple transistors become a threat of over-erasing, it is simply for larger currents that they need to be erased. Therefore, it is used to determine the use of additional erasure + steps, and to determine whether the collective current is less than a predetermined value. Other excellent features of the method and circuit according to the present invention will be illustrated by non-limiting examples using the following figures: Figure 1 shows a circuit with memory Figure 2 shows a signal for reading from memory Figure 3 shows a flowchart illustrating erasure Figure 4 shows the verification Memory erase signal Figure 5 shows further signals used to confirm memory erase Figure 6 shows a bit line sensing circuit. Detailed description of the invention Figure 1 shows a circuit with memory. The circuit contains a memory matrix with ^ Row 5 has memory 10 '11' 12, one word line decoder 1 4, multiple word lines 140, 141, one bit line sensing circuit 16, one source / drain voltage supply circuit 18, and A control circuit 19. Each row 10, 1 1, 12 contains a bit line 103, 113, 123 and a plurality of floating gate memory transistors 101, 102 each with a floating gate (only two are shown in a row 10) Memory transistors, but there are usually more transistors (e.g., 256 or 4096 transistors) in each row of 10, 1 1, 12). Memory transistors 101, 102 of each row of 10, 1 1, 12 The drain electrode is collectively connected to the bit line 103 of this row. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (please read the precautions on the back before filling this page). Install the wisdom of the Ministry of Economic Affairs Printed by the Property Agency's Consumer Cooperatives 561486
五、發明說明（6 ) 經濟部智慧財產局員工消费合作社印製 操作中’資訊由儲存於浮動閘的電荷呈現於記憶體電晶 把101 ’、102。各種讀取資訊方法及由浮動閘注入電荷或移 開私荷之方法為業界人士已知。依據使用方法而定，業界 人士將可選擇字線解碼器丨4及源極/汲極電壓供應電路丨8的 適當貫施例。舉例言之，此處顯示一種簡單讀取方法。 士圖2顯示用於資訊讀取方法之簡單例的時間相依性信號。 项取期間，源極/汲極電壓供應電路丨8將記憶體電晶體ι〇ι ’ 102的源極維持於地（Vss)電位。位元線1〇3，，123彼 此隔離孚線解碼器1 4接收列位址，選定記憶體電晶體1 〇 J ，1〇2的一列。響應於此，字声解碼器14外加電壓Vss+VGS 至孩選定列的字線14〇，141。其它各列的字線丨4 〇 ,丨4 1 ( 圖1簡化例僅顯示另一列）接收Vss。結果造成不同列的記憶 體電晶體之閘極-源極電壓顯示於圖2 VRi , VR2。 VGS經選定為選定列的各電晶體將依據其閾值被調整至程 式規劃位準或抹消位準而決定是否導通。結果記憶體電晶 體將依據連結至該位元線的選定電晶體的閾值是否已經被 調整至程式規劃位準或抹消位準而導通電流。所得電流於 圖2顯示為IBL。 位元線感測電路16感測電流是否由位元線1〇3，113 , ι23 抽出。於位元線感測電路帶有多組位元線之例（如圖6所示）， 位元線感測電路16接收一選擇信號用以由各組中選定一位元 線66a-h。位元線選擇控制電路64接收選擇信號及解碼信號 而激勵通過多工電路62a , b由各組的選定位元線66a_h至該 組的感測放大器60a，b之導電路徑。位元線感測電路i 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） #-^--------tr--------- (請先閱讀背面之注意事項再填寫本頁) 561486 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（7 ) 輸出仏號指示電流是否高於預定位準。所得一位元線之邏 輯輸出於圖2顯示爲v〇。 資訊經由調整閾値而寫入記憶體電晶體101，1〇2。—例 中使用兩個閾値位準：抹消位準及程式規劃位準。此等位 準分別表示兩個不同的邏輯値。 取初（抹消後）全邵記憶體電晶體1 〇 1，102於其浮動閘帶 有電荷因而其閾値實質上皆於相同位準，稱爲「抹消位準 」。資訊於控制電路1 9的控制之下寫入。當資訊被寫入時 ’個別選定記憶體電晶體101，：102的閾値經由改變選定電 晶體的浮動閘的電荷量而被調整至程式規劃位準（例如降低 )。其方去爲業界人士已知且使用例如發羅語罕（ Nordheim)隧道化效應或熱電子注入0 爲了改寫資訊，記憶體首先必須被抹消。係經由調整_ 扇區的全部記憶體電晶體101，1〇2的閾値達成。一扇區全 邵各行1 0，1 1，1 2含有多列。該扇區的全部各列及各行閾 値集體被抹消至抹消位準（例如升高閾値）。 源極/汲極供應電路1 8及字線解碼器經由外加適當電壓的 組合給記憶體電晶體1〇1，102的源極、汲極及閘極而執行 抹消。使用例如發羅諾罕隧道化效應及電壓組合來執行此 種過程的抹消爲業界人士已知。 控制電路1 9於重複週期控制抹消。圖3顯示進行抹消的 流程圖。於第一步驟3 !，控制電路指令源極/汲極供應電路 1 8及字線解碼器丨4外加適當電壓組合給記憶體電晶體 ，102而變動其閾値至抹消位準。 ——'·-------·-裝--------訂---------· (請先閱讀背面之注意事項再填寫本頁) -10-V. Description of the invention (6) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In operation, the information stored in the floating gate is presented in the memory transistor 101 and 102. Various methods of reading information and methods of injecting charges or removing private charges from floating gates are known in the industry. Depending on the method of use, those in the industry will be able to choose appropriate implementations of the word line decoder 4 and the source / drain voltage supply circuit 8. For example, a simple reading method is shown here. Figure 2 shows a time-dependent signal for a simple example of an information reading method. During the selection period, the source / drain voltage supply circuit 8 maintains the source of the memory transistor 102 at the ground (Vss) potential. The bit lines 103, 123 each receive the column address from the isolated line decoder 14, and select a column of the memory transistor 10J, 102. In response to this, the word decoder 14 applies a voltage Vss + VGS to the word lines 14O, 141 of the selected column. The word lines 丨 4 〇 and 丨 1 in the other columns (the simplified example of FIG. 1 shows only another column) receive Vss. As a result, the gate-source voltages of the memory transistors in different columns are shown in Figure 2 VRi and VR2. Each transistor selected by VGS as the selected column will be turned on or off according to its threshold value being adjusted to the program planning level or erasing level. As a result, the memory transistor will conduct current according to whether the threshold value of the selected transistor connected to the bit line has been adjusted to the programming level or the erasing level. The resulting current is shown in Figure 2 as IBL. The bit line sensing circuit 16 senses whether a current is drawn from the bit lines 103, 113, ι23. In the case where the bit line sensing circuit has multiple sets of bit lines (as shown in FIG. 6), the bit line sensing circuit 16 receives a selection signal for selecting a bit line 66a-h from each group. The bit line selection control circuit 64 receives the selection signal and the decoded signal to excite the conductive path from the selected positioning element lines 66a_h of each group to the sense amplifiers 60a, b of the group through the multiplexing circuits 62a, b. Bit line sensing circuit i 6 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) #-^ -------- tr --------- (Please (Please read the notes on the back before filling this page) 561486 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (7) The output 仏 indicates whether the current is higher than a predetermined level. The resulting logical output of a one-bit line is shown in Figure 2 as v0. The information is written into the memory transistors 101, 102 by adjusting the threshold. —The example uses two threshold levels: the erase level and the programming level. These levels represent two different logical volumes. The initial (after erasing) full Shao memory transistor 101,102 has a charge in its floating gate band, so its thresholds are all at the same level, which is called "erasing level". The information is written under the control of the control circuit 19. When the information is written, the threshold value of the individually selected memory transistors 101 ,: 102 is adjusted to the programming level (for example, lowered) by changing the charge amount of the floating gate of the selected transistor. This method is known to those in the industry and uses, for example, the Nordheim tunneling effect or hot electron injection. In order to rewrite information, the memory must first be erased. This is achieved by adjusting the thresholds of all the memory transistors 101, 102 of the sector. Each sector in a row contains 10, 11, 12, and multiple columns. All the columns and rows of the sector threshold 値 are collectively erased to the erasure level (for example, raising the threshold 値). The source / drain supply circuit 18 and the word line decoder erase the source, drain, and gate of the memory transistor 101, 102 by a combination of an appropriate voltage. The erasure of performing such a process using, for example, the Fronohan tunneling effect and voltage combination is known to those skilled in the art. The control circuit 19 controls erasing in the repeat cycle. Figure 3 shows the flow chart of the erasure. In the first step 3, the control circuit instructs the source / drain supply circuit 18 and the word line decoder 丨 4 to apply a suitable voltage combination to the memory transistor 102, and changes its threshold to the erasure level. —— '· ------- · -install -------- order --------- · (Please read the precautions on the back before filling this page) -10-
561486 五、發明說明（ 流至感測放大器之電流圯!^最初係高於由單一程式規劃電晶 體（以虛線表示）抽取的位元線電流IBL〇。 於第二步驟32外加的閘極源極電壓VGS係高於於正常讀 出期間外加的閘極-源極電壓VGS〇(其位準顯示爲虛線 VGSO)。VGS實質上係於閾値位準範圍的下緣，該範圍包括 抹消位準以及可接受環繞該位準展開範圍。如此任何記憶 體電晶體101，102其閾値尚未升高至抹消位準者將由其連 結的位兀線103，113，123抽取電流。同一行的全部電晶體 將由行10，11，12之位元線1〇3，113，123抽取組合電流 。此種組合電流將於連續執行第二步騍3 2時降低直到落至 低於預疋位準以下’此時確定該扇區的全部記憶體電晶體 101，102之閾値皆至少達到抹消位準。 位元線感測電路1 6由全部選定的記憶體電晶體1 〇 1，1 〇2 感測組合電流IBL。位元線感測電路1 6輸出邏輯信號V 0， 該信號表示集合電流是否降至預定最大抹消電流以下。如 此邏輯信號V0表示選定的電晶體ιοί，1〇2任一者之閾値是 否尚未充分朝向抹消位準變動。 當然使用附圖顯示的實施例僅爲本發明之具體實施例範 例。無數不同的具體實施例皆屬可能。 例如本發明並不依賴精確調整記憶體電晶體閾値之道。 可使用外加閾値變動信號配置，該配置與圖2使用的配置不 同。可使用不同的讀取連結，不同行間共用位元線，使用 不同感測放大器及參考記憶體電晶體等。 至於不同實施例之另一例，控制電路1 9可實施爲特用目 12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝 tr--------- 經濟部智慧財產局員工消費合作社印製 561486 A7561486 V. Description of the invention (the current flowing to the sense amplifier 圯! ^ Was originally higher than the bit line current IBL drawn by a single program transistor (indicated by a dashed line). The gate source added in the second step 32 The voltage VGS is higher than the gate-source voltage VGS applied during normal readout (its level is shown as a dashed line VGSO). VGS is essentially the lower edge of the threshold level range, which includes the erasing level And it is acceptable to expand the range around this level. In this way, the threshold of any memory transistor 101, 102 has not risen to the level of 103, 113, 123 that the eraser will connect to draw current. All transistors in the same row The combined current will be drawn from the bit lines 10, 113, and 123 of rows 10, 11, and 12. This combined current will be continuously reduced during the second step (32) until it falls below the pre-set level. At that time, it is determined that the thresholds of all the memory transistors 101 and 102 in the sector have reached at least the erasure level. The bit line sensing circuit 16 is composed of all the selected memory transistors 1 〇1, 〇2 to sense the combined current. IBL. Bit line sensing circuit 16 outputs The signal V 0 indicates whether the collective current has fallen below a predetermined maximum erasing current. In this way, the logic signal V 0 indicates whether the threshold value of any one of the selected transistors ιοί has not sufficiently changed toward the erasing level. The embodiment shown in the figure is only an example of a specific embodiment of the present invention. Countless different specific embodiments are possible. For example, the present invention does not rely on the precise adjustment of the threshold value of the memory transistor. The external threshold value can be used to configure the signal. The configuration is different from the configuration used in Figure 2. Different read links can be used, bit lines can be shared between different rows, different sense amplifiers and reference memory transistors can be used. As another example of different embodiments, the control circuit 19 can Implemented as special purpose 12- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page) Loading tr --------- Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 561486 A7
爲控制讀取、程式規劃及抹消的狀態機器 杧制电路可實施爲程式規劃微控 微控制器含有其它程式，其使用記憶體作爲；料ΐ二 憶體。此外微控制器㈣記憶體的抹消中己 =制電路可實施作爲專用用途，例如使用抹消正反器或 買出撥紐電路。本例中，抹消正反器當設㈣致能抹 /肖/項出撥姐電路。抹消/讀出撥粗電路讓記憶體交替進行 肖乍業及卞出作業來確認抹消作業。位元線感測電路16 之輸出連結至抹消正反器之復置輸人，故_旦位元線感測 電路16之邏輯輸出指示全部關聯記憶體電晶體閾値已經充 刀凋整時，正反器被復置。顯然控制電路有多種替代實務 。控制電路當實施時可整合記憶體於單一半導體晶片上， 或可爲分布於不同晶片的系統的一部分。 至於另一例，雖然圖}顯示同一位元線感測電路丨6用於 讀出及用於驗證抹消，但當然可使用不同電路；或調整位 兀線感測電路16而於讀出期間以及驗證期間切換位元線感 測電路1 6由一邏輯輸出位準至另一不同的電流位準。 至於另一例，替代單一記憶體電晶體1〇1，1〇2，可使用 浮動閘電晶體及正常電晶體，其主電流通道彼此_聯連結 。此例中’正常電晶體的閘極可連結至字線而選擇浮動問 電晶體’而浮動閘電晶體之閘極係連結至參考電壓供應器 ，可介於程式規劃位準與抹消位準間作甄別但無法進行選 擇。 至於又另一例，抹消對應於降低閾電壓（故被抹消的記憶 13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂---------^_wi - 經濟部智慧財產局員工消費合作社印製In order to control the state machine for reading, programming and erasing, the control circuit can be implemented as a programming micro-controller. The microcontroller contains other programs, which use the memory as the memory; the second memory. In addition, the erase circuit of the microcontroller and the memory can be implemented as a dedicated purpose, such as using an erase flip-flop or buying a button circuit. In this example, the erasing flip-flop should be set to enable erasing the circuit. The erase / read coarse circuit allows the memory to alternate between Xiao Zhaye and the erase operation to confirm the erase operation. The output of the bit line sensing circuit 16 is connected to the reset input of the erasing flip-flop. Therefore, the logic output of the bit line sensing circuit 16 indicates that all the associated memory transistor thresholds have been charged, The inverter is reset. Obviously there are multiple alternatives to control circuits. The control circuit, when implemented, may integrate memory on a single semiconductor chip or may be part of a system distributed across different chips. As for another example, although the figure shows the same bit line sensing circuit 6 for reading and verifying erasure, different circuits can of course be used; or the bit line sensing circuit 16 can be adjusted during reading and verification During this period, the bit line sensing circuit 16 is switched from a logic output level to a different current level. As another example, instead of a single memory transistor 101, 102, a floating gate transistor and a normal transistor can be used, and the main current channels are connected to each other. In this example, the gate of the normal transistor can be connected to the word line and a floating transistor is selected. The gate of the floating transistor is connected to the reference voltage supply, which can be between the programming level and the erasing level. Screening but no choice. As for another example, erasing corresponds to lowering the threshold voltage (so erased memory 13- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)) (Please read the precautions on the back before filling this page ) Binding ---- Order --------- ^ _ wi-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs