KR20080090841A - The non volatile memory device and the method for reading out thereof - Google Patents

Abstract

A nonvolatile memory device and a read-out method thereof are provided to reduce chip size of the nonvolatile memory device by using a low voltage transistor to implement a part of circuits of a bit line selection part. A bit line selection part(310) connects an even bit line or an odd bit line and a sensing line selectively. A discharge part(330) applies a control signal of a specific level to the sensing line. The bit line selection part is formed by using a high voltage transistor, and the discharge part is formed by using a low voltage transistor. A register part(320) is connected to the sensing line and temporarily stores data to be stored in a specific memory cell, and is formed by using a low voltage transistor.

Description

The non volatile memory device and the method for reading out

1 is a circuit diagram illustrating a page buffer of a conventional nonvolatile memory device.

2 is a layout diagram of a page buffer of a conventional nonvolatile memory device.

3 is a circuit diagram illustrating a page buffer of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 is a layout diagram of a page buffer of a nonvolatile memory device according to an exemplary embodiment of the present invention.

5 is a waveform diagram illustrating various voltage signals applied during a read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

The present invention relates to a nonvolatile memory device and a method of reading the same, and more particularly, to a nonvolatile memory device and a method of reading the same, which reduces the overall chip size by replacing some circuits formed of the high voltage transistor with a low voltage transistor. .

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

In this case, the bit line selector is typically implemented in the form of a high voltage transistor. However, in the case of the high voltage transistor, the bit line selector has a large chip size.

An object of the present invention is to provide a nonvolatile memory device capable of implementing some circuits of a bit line selector as a low voltage transistor in order to reduce the chip size of the nonvolatile memory device. Another object of the present invention is to provide a method of reading the nonvolatile memory device.

The nonvolatile memory device of the present invention for achieving the above object is a bit line selection unit for selectively connecting the even bit line or odd bit line and the sense line, and the discharge for applying a control signal of a specific level to the sense line And a bit line selector using a high voltage transistor, and the discharge unit is formed using a low voltage transistor.

In addition, the method of reading the nonvolatile memory device according to the present invention includes applying a high level discharge signal to discharge a sense line to a low level, connecting a cell string and a bit line, and precharging the bit line to a high level. And a step of evaluating the voltage level of the bit line according to whether the cell is programmed, and sensing and storing the voltage level of the bit line through the sensing line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a page buffer of a conventional nonvolatile memory device.

The page buffer includes an even bit line (BLe) and an odd bit line (BLo) connected to a memory cell array (not shown) including memory cells formed in a matrix structure, and a register unit 120 for temporarily storing specific data. And a specific voltage level with respect to the sensing line SO and the bit lines BLe and BLo connected to the bit lines and the register unit to sense a voltage level of a specific bit line or a voltage level of a specific register unit. And a control signal input terminal for applying a control signal VIRPWR of the bell, and in response to the even discharge signal DISe or the odd discharge signal DISo, the control signal VIRPWR is transmitted to the even bit line BLe or the odd. And a bit line selector 110 applied to the bit line BLo.

In more detail, the bit line selection unit 110 is connected to one end of the control signal input terminal and supplies the control signal VIRPWR to the even bit line BLe in response to an even discharge signal DISe. An NMOS transistor N112 includes an NMOS transistor N114 connected to one end of the control signal input terminal and supplying the control signal VIRPWR to the odd bit line BLo in response to the odd discharge signal DISo.

In addition, the NMOS transistor N116 or N118 connects the bit lines BLe or BLo and the sense line SO, respectively, in response to the bit line selection signal BSLe or BSLo.

The register unit 120 temporarily stores corresponding data according to the voltage level of the sensing line in reading data stored in a specific memory cell array. In addition, in the operation of programming the externally input data into the specific memory cell array, the data is temporarily stored.

The register unit 120 is typically a latch composed of two inverters IV122 and IV124 for temporarily storing data, an NMOS transistor N128 connected to a node of each latch and turned on in response to a voltage level of the sense line; It is connected between the NMOS transistor N124, the NMOS transistor N128, and the ground voltage source, which is connected to the node of the latch and initializes the data stored in the latch in response to a reset signal RESET and to the read signal READ. An NMOS transistor N126 in response to delivering low level data to the latch.

Although shown in the drawing to include only one latch, it is possible to configure a register portion having a dual register type including one more latch configured in the same manner.

In addition, the register unit 120 includes a PMOS transistor P120 that connects the sensing line SO and a power supply voltage in response to a precharge signal PRECHb.

Meanwhile, the bit line selector 110 is formed in the high voltage transistor region, and the register unit 120 is formed in the low voltage transistor region. Let's look at the specific layout.

2 is a layout diagram of a page buffer of a conventional nonvolatile memory device.

16 bit line pairs (BLe [n], BLo [n]) including an even bit line and an odd bit line, and 16 bit line selection units 210, 212, and 214 connected to each bit line pair. Contains dogs. In addition, 16 bit registers 220, 222, and 224 connected through the bit line selection unit and the sensing line SO are included.

In this case, the bit line selectors 210, 212, and 214 correspond to the high voltage transistor region, which is enlarged again as shown in the right side of FIG. 2.

Each of the bit line selection units 210, 212, and 214 includes an area 230 connected to the bit lines BLe and BLo, an area 232 connected to the sensing line SO, and a sensing line SO. A region 234 to which the bit line selection signals BSLe and BSLo to which the bit lines BLe and BLo are connected are applied, and a discharge signal DISe to DISo which connects the bit lines BLe and BLo to the control signal input terminal. The region 236 is applied to, and the region 238 to which the control signal VIRPWR is applied.

At this time, when the NMOS transistors N112 and N114 controlled by the discharge signal and the control signal input terminal are included in the high voltage transistor region as shown in FIG. 1, the region where the control signal is applied is formed as shown in FIG. 2. This is necessary in duplicate. Since the level of the control signal applied through the control signal input terminal is only 1 to 5 V, it is not necessary to include it in the high voltage transistor region having the breakdown voltage characteristic of 15 to 30 V.

3 is a circuit diagram illustrating a page buffer of a nonvolatile memory device according to an exemplary embodiment of the present invention.

The page buffer bit line selection unit 310 determines whether the even bit line BLe or the odd bit line BLO and the sensing line SO are connected to each memory cell string included in the memory cell array. ), A discharge unit 330 for discharging the sensing line by applying a control signal of a specific level to the sensing line SO, and a register unit 320 for temporarily storing specific data connected to the sensing line. It includes.

However, unlike the case of FIG. 1, the bit line selector 310 formed in the high voltage transistor region may select the bit lines BLe or BLo and the sensing line SO in response to the bit line select signal BSLe or BSLo. An NMOS transistor (N312 or N314) connected to each other, the control signal (VIRPWR) in response to a control signal input terminal or an even discharge signal (DISe) or an odd discharge signal (DISo), respectively, the even bit line (BLe). ) Or the NMOS transistor N330 applied to the odd bit line BLo is not included.

In addition, the page buffer includes a discharge unit 330 connected to the sensing line SO to simultaneously discharge the even bit line BLe and the odd bit line BLO, which are formed in the low voltage transistor region.

The discharge unit 330 is connected between a control signal input terminal to which a control signal VIRPWR is applied, and is connected between the sensing line SO and a control signal input terminal, and the control signal VIRPWR in response to the discharge signal DISe / o. NMOS transistor N330 is applied to the sensing line SO.

In addition, the page buffer includes a register unit 320 configured in the same way as the register unit 120 of FIG. 1, and a detailed description thereof is the same as described above.

4 is a layout diagram of a page buffer of a nonvolatile memory device according to an exemplary embodiment of the present invention.

A total of 16 bit line pairs BLe [n] and BLo [n] including an even bit line and an odd bit line, and 16 bit line selection units 410, 412, and 414 connected to each bit line pair are included. Contains dogs. 16 discharge units 431, 432,..., 436 for applying a control signal VIRPWR to each of the sensing lines SO. In addition, it includes 16 registers (not shown) connected to each sensing line.

Each of the bit line selection units 410, 412, and 414 includes an area 420 connected to each of the bit lines BLe and BLo, an area 422 connected to the sensing line SO, and a sensing line SO. And a region 424 to which the bit line selection signals BSLe and BSLo, which connect each bit line BLe and BLo, are applied, which is formed in the high voltage transistor region. Thus, the NMOS transistors N312 and N314 are formed using high voltage transistors.

Next, the discharge units 431, 432,..., 436 are discharge signals for connecting the region 440 connected to the sensing line SO, the bit lines BLe and BLo, and the control signal input terminal. A region 442 to which (DISe / o) is applied and a region 444 to which a control signal VIRPWR is applied are formed in the low voltage transistor region. Thus, the NMOS transistor N330 is formed using a low voltage transistor.

As such, the overall chip size may be greatly reduced by implementing the portion that was implemented in the form of a high voltage transistor in the form of a low voltage transistor.

5 is a waveform diagram illustrating various voltage signals applied during a read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

(1) T1 section

First, a high level discharge signal DISe / o is applied to the NMOS transistor N330 connected between the input terminal of the control signal and the sensing line SO for a predetermined time to apply the control signal VIRPWR to the sensing line SO. Let's do it. At this time, since the control signal VIRPWR is maintained at a low level, each sensing line SO is discharged to a voltage level supplied by the control signal VIRPWR, that is, 0V.

On the other hand, the node Q of the register unit 320 is initialized to store low level data using a reset signal.

(2) T2 section

The drain select transistor DSL is turned on to connect a cell string including a specific memory cell to be read with a specific bit line BLe or BLo.

In addition, a voltage of OV is applied to a selected word line, that is, a word line connected to the specific memory cell, and a voltage Vread is applied to other word lines that are not selected.

In addition, the low level precharge signal PRECHb is applied to the PMOS transistor P322 to turn on the transistor to precharge the sensing line SO to a high level Vcc.

The NMOS transistor N312 or N314 is turned on by applying the bit line selection signal BSLe or BSLo of the first voltage level V1 to the specific bit line. In the drawing, although the even bit line selection signal BSLe of the first voltage level V1 is applied to connect the even bit line BLe and the sensing line SO, the odd bit line BLo and the sensing line SO are applied. Is connected to the first voltage level V1 odd bit line selection signal BSLo. Therefore, the specific bit line BLe or BLo and the sensing line SO are connected to precharge the specific bit line BLe or BLo to the high level Vcc.

(3) T3 section

Next, the source select transistor SSL is turned on to connect one terminal of the cell string to a common source line connected to a ground power source. As a result, one end of both ends of the cell string of the memory cell array is connected to the bit line and one end is connected to the common source line, thereby forming a current path from the sensing node to the common source line through the bit line.

Next, an evaluation step of determining whether to program a specific cell is performed according to the degree of change in the voltage level of the specific bit line BLe or BLo.

That is, the bit line selection signal BSLe or BSLo applied to the high level is transferred to the low level to disconnect the specific bit line BLe or BLo from the sensing line SO. Therefore, a change occurs in the voltage level of the corresponding bit line depending on whether or not the specific cell to be read is programmed.

When the corresponding cell is programmed, the threshold voltage of the corresponding cell is not high, and thus the cell is not turned on. Thus, no current flows through the formed current path, thereby maintaining the voltage level of the precharged bit line. However, when the cell is erased, current flows through the formed current path, thereby reducing the voltage level of the bit line.

(4) T4 section

Next, the precharge signal PRECHb is shifted to a high level to release the connection between the sensing line SO and the power supply voltage Vcc.

Next, the bit line selection signal BSLe or BSLo of the second voltage level V2 is applied to connect the sensing line SO to the specific bit line BLe or BLo.

Therefore, the voltage level of the sensing line SO also changes in accordance with the change of the voltage level of the bit line BLe or BLo.

After a predetermined time elapses, whether the specific cell is programmed or not is stored in the register unit 320 according to the voltage level of the sensing line SO.

In order to store whether or not a specific cell is programmed according to the voltage level of the sensing line SO, a read signal READ is applied to the NMOS transistor N328 of the register unit 320 so that the power supply voltage is changed according to the voltage level of the sensing node. It can be applied to the latch of the register unit 320.

Therefore, when a specific cell is programmed and the change of the voltage level of the sensing line SO is small, the NMOS transistor N326 of the register unit 320 is turned on, and the NMOS transistor N328 is also turned on by the read signal READ. As it is turned on, low level data is applied to the latch and high level data is stored in node Q by inverter IV324.

However, when a specific cell is not programmed, the voltage level of the sensing line SO is changed to the low level, so that the NMOS transistor N326 of the register 320 is turned off to maintain the low-level data stored earlier. .

According to the above-described configuration of the present invention, the overall chip size may be reduced by implementing the circuit part, which is conventionally implemented as a high voltage transistor, as a low voltage transistor. In addition, according to the above-described configuration of the present invention, data stored in a specific memory cell of the nonvolatile memory device of the present invention can be read out efficiently.

Claims (9)

A bit line selector for selectively connecting the even bit line or the odd bit line and the sense line, A discharge unit for applying a control signal of a specific level to the sensing line, And the bit line selector is formed using a high voltage transistor, and the discharge unit is formed using a low voltage transistor. The nonvolatile memory device of claim 1, further comprising a register unit connected to the sensing line to temporarily store data to be stored in a specific memory cell and formed using a low voltage transistor. The semiconductor device of claim 1, wherein the bit line selector comprises: a first NMOS transistor connecting the even bit line and the sense line in response to an even bit line select signal; And a second NMOS transistor connecting the odd bit line and the sense line in response to an odd bit line selection signal. The display device of claim 1, wherein the discharge unit comprises: a control signal input terminal configured to apply a control signal of the specific level; And an NMOS transistor connecting the sensing line and the control signal input terminal in response to a discharge signal. The nonvolatile memory device of claim 4, wherein the control signal input terminal is formed in a low voltage transistor region. Discharging the sensing line to a low level by applying a high level discharge signal; Connecting the cell string and the bit line and precharging the bit line to a high level; Evaluating the voltage level of the bit line according to whether the cell is programmed; And sensing and storing the voltage level of the bit line through the sense line. The nonvolatile memory of claim 6, wherein the discharging comprises applying a low level control signal to a sensing line through an NMOS transistor turned on in response to the high level discharge signal. How to read the device. The method of claim 6, wherein the precharging comprises: turning on a drain select transistor to connect a cell string and a bit line; Applying a read voltage to a word line connected to the memory cell and applying a pass voltage to other word lines; Precharging the sensing line to a high level by applying a low level precharge signal; And connecting the bit line and the sensing line by applying a bit line selection signal of a first voltage level. The method of claim 6, wherein the evaluating comprises: applying a low level bit line selection signal to disconnect the bit line and the sensing line; Turning on the source select transistor to connect one terminal of the cell string to a common source line connected to a ground power source.

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