08217twfl.doc/00608217twfl.doc / 006
修正曰期92.4.30 六丨 in* 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實 施方式及圖式簡單說明） 本發明是有關於一種元件設計方法，且特別是有關 於一種用於記憶體上全晶片元件設計方法。 一般產品的設計方式主要有由下至上（bottom-up )以 及由上至下（top-down )兩種。由下至上的設計方式通常是 將重要的組件（component )先設計好，再將各組件組裝成 各模組’再將各模組連接以形成產品本身，通常記憶體元 件或混合訊號（Mix-Mode )積體電路元件設計均採取由下 而上的設計流程，因爲這些元件的類比電路都屬於電晶體 層次（transistor level )的設計，而在傳統上並不能視爲邏 輯閘層次（gate level )而將它打散來自動繞線。而由上至 下的設計方式則是以產品本身效率作爲考量重點來進行其 中組件的設計。除了由下至上以及由上至下的設計方式以 外，亦可將由下至上與由上至下整合使用，以使產品達到 最佳化。 一般記憶體主要是由記憶胞陣列部份（memory cell array )以及邏輯部份（logic part )所構成。由於記憶體中 具有相當多的類比電路（analog circuit )、長度很長的配線 (long wire )以及邏輯部份，因此一般記憶體多採用由下至 上的設計方式。然而，已有人提出記憶體中的邏輯部份可 使用由上至下的方式進行設計，但類比電路的部份仍無法 使用由上至下的設計方式，故僅針對邏輯部份以由上至下 08217twfl .doc/006 tr㈣偏 修正日期92.4.3〇 的方式進行設計仍無法符合全晶片自動化設計（ful1 chlP automation design )的需求。 首先請參照第1A圖與第1B圖，其繪示爲習知記憶 體的設計流程圖。習知將記憶胞陣列部份與邏輯部份分開 進行設計。在記憶胞陣列的部份包括了線路設計（schematic design )100、Hard macro 佈局 102、全晶片繞線 1〇4 與 Tape out 106的步驟。 接著請參照第第1B圖，其繪示爲習知邏輯的設計流 程圖。習知邏輯設計流程包括了高階硬體描述語言編程 110、合成（synthesis )112、自動繞線 114 以及 Tape out 116 的步驟。 接著請參照第2圖，其繪示爲習知記憶體的設計流 程圖。在記憶胞陣列的部份包括了線路設計200以及Hard macro佈局與功能描述202的步驟。而邏輯部份則包括了 高階硬體描述語言編程204、合成206。之後，將記憶胞 陣列的部份與邏輯部份合倂，以搭配Hard macro進行全晶 片繞線208，最後則爲Tape out 210的步驟。由於整體設 計係拆解成兩部份進行，且構成Hard macro的類比設計 (analog schematic )必須以人工方式進f了繞線設計。 習知記憶體的設計流程中，在記憶胞陣列部份中Hard macro，包括脈衝產生器（pulse generator )、電容、電阻、 電晶體以及高壓元件等必須事先進行設計，之後再:搭配 Hard macro進行全晶片繞線（routing )時，其繞線設計的 彈性將受到相當大的限制。因此，整體設計_法完全自動 559711 厂一- -- - 一 1 08217twfl.doc/006 ^ · I 修正日期 92.4.30 化將會導致設計時間拉長、進度遲緩的現象。 此外’目則的自動配置與繞線工具（auto placement & routing tool，APR tool )，例如 Avanti 公司的 Apollo 或是 Cadence公司的SE軟體，並無法在超過2個電源線路（同 一晶片中）的情況下進行自動繞線，然而以一般的快閃記 憶體陣列的設計爲例，其皆爲具有2個以上的電源線路 (high voltage circuit )。因此，在同一晶片中具有超過2 個電源線路的情況下，其繞線仍然必須以半人工的方式進 行0 因此’本發明的目的在提出一種用於記憶體上全晶 片兀件設計方法，以避免Hard macro所導致繞線無法自動 化的困擾。 爲達本發明之上述目的，提出一種用於記憶體上全 晶片兀件設計方法，係將Hard macro中的元件拆成電晶體 層次的元件，以進行自動化的設計。在超過2個電源線路 的情況下’藉由自動繞線軟體提供多個旁通的線路以作爲 Vss與VDD ’其中Vss與vDD爲軟體可辨識的兩個電源 (power )’而將多個電源線路當作信號線路進行繞線，以 達到將Hard maCro中所有元件進行自動繞線的目的。換言 之’也就是藉由自動配置與繞線工具同時對邏輯閘層次部 份與電晶體層次部份進行自動繞線。 本發明之用於記憶體上全晶片元件設計方法，將上 述Hard macro中的線路設計轉換成例如verii〇g或EDIF 的格式之後’將其與Hard macro以外之其他部份（如邏輯 559711 08217twfl.doc/006Amendment date 92.4.30 六 in * 发明, description of the invention (the description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiment and the simple description of the drawings) The present invention relates to a method for designing components, In particular, it relates to a method for designing a full-chip device on a memory. There are two main product design methods: bottom-up and top-down. The bottom-up design method is usually to design important components first, then assemble each component into each module ', and then connect the modules to form the product itself, usually memory components or mixed signals (Mix- Mode) Integrated circuit component design adopts a bottom-up design process, because the analog circuits of these components belong to the transistor level design, and traditionally cannot be regarded as the logic gate level. Break it up and wind it automatically. The top-down design approach focuses on the efficiency of the product itself to design the components. In addition to bottom-up and top-down design methods, bottom-up and top-down integration can also be used to optimize the product. Generally, the memory is mainly composed of a memory cell array and a logic part. Because there are quite a lot of analog circuits, long wires and logic parts in the memory, most of the memory is designed from bottom to top. However, some people have proposed that the logic part of the memory can be designed using a top-down approach, but the analog circuit part still cannot be designed using a top-down design, so only the logic part is top-down. The design in the way of 08217twfl.doc / 006 tr bias correction date 92.4.3〇 still can not meet the requirements of ful1 chlP automation design. First, please refer to FIG. 1A and FIG. 1B, which show a design flow chart of a conventional memory. It is conventional to design the memory cell array part separately from the logic part. The memory cell array includes the steps of schematic design 100, hard macro layout 102, full-chip winding 104 and tape out 106. Please refer to FIG. 1B, which shows a design flow chart of conventional logic. The conventional logic design process includes the steps of high-level hardware description language programming 110, synthesis 112, automatic winding 114, and tape out 116. Please refer to FIG. 2 for a design flow chart of the conventional memory. The memory cell array includes the steps of circuit design 200 and Hard macro layout and function description 202. The logic part includes high-level hardware description language programming 204 and synthesis 206. After that, the part of the memory cell array and the logic part are combined to complete the full-chip winding 208 with Hard macro, and finally the step of Tape out 210. Because the overall design is disassembled into two parts, and the analog schematic of the hard macro must be manually entered into the winding design. In the design process of conventional memory, in the memory cell array part, the hard macro, including the pulse generator, capacitor, resistor, transistor, and high-voltage components, must be designed in advance, and then: with Hard macro When the whole chip is being routed, the flexibility of its winding design will be considerably limited. Therefore, the overall design method is fully automatic. 559711 Factory 1---1 1 08217twfl.doc / 006 ^ · I The revision date 92.4.30 will lead to a long design time and slow progress. In addition, the automatic placement and routing tools (APR tool) such as Apollo from Avanti or SE software from Cadence cannot be used in more than 2 power lines (on the same chip). In this case, automatic winding is performed. However, taking a general flash memory array design as an example, all of them have more than two high voltage circuits. Therefore, when there are more than two power lines in the same chip, the winding must still be performed in a semi-manual manner. Therefore, the object of the present invention is to propose a method for designing a full-chip component on a memory to Avoid the trouble that the winding cannot be automated caused by Hard macro. In order to achieve the above object of the present invention, a method for designing a full-chip element on a memory is proposed, which is to disassemble the components in the hard macro into transistor-level components for automated design. In the case of more than 2 power lines, 'multiple bypass lines are provided by the automatic winding software as Vss and VDD', where Vss and vDD are the two power sources that the software can recognize, and multiple power sources are used. The wire is wound as a signal wire to achieve the purpose of automatically winding all the components in the Hard maCro. In other words, it means that the logic gate level part and the transistor level part are automatically wound by the automatic configuration and winding tools at the same time. The method for designing a full-chip component on a memory of the present invention, after converting the circuit design in the above-mentioned Hard macro into a format such as verii0g or EDIF, 'combines it with other parts (such as logic 559711 08217twfl.) doc / 006
修正日期92.4.30 部份）結合。結合之後，進行全晶片的配置與繞線設計以 及全晶片後設計合成（post-layout synthesis )，即完成全晶 片的自動化配置與繞線。 本發明中，以單體自動繞線方式（cell base autorouting ) 對高壓元件 （ high voltage device )， 例如 N 型金氧 半電晶體、P型金氧半電晶體以及由N型與P型金氧半電 晶體所構成之反向器（inverter )進行自動繞線方式。 本發明中，將整個N型金氧半電晶體、P型金氧半 電晶體以及反向器的尺寸定義爲標準單元（standard cell ) 的整數倍（亦可爲非整數倍，視軟體而定），並在其上進 行繞線。提供多個旁通的線路以作爲Vss與VDD，其中Vss 與VDD爲軟體可辨識的兩個電源（power )，而將其中的井 接觸（well contact )當作信號線路進行繞線。 爲讓本發明之上述目的、特徵以及優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1A圖繪示爲習知記憶體的設計流程圖； 第1B圖繪示爲習知邏輯的設計流程圖； 第2圖繪示爲習知記億體的設計流程圖； 第3圖繪示爲依照本發明一較佳實施例用於記憶體 上全晶片元件的設計流程圖； 第4圖繪示爲依照本發明一較佳實施例用於記憶體 上全晶片元件中N型基底上之多電源N型金氧半電晶體； 559711 08217twfl.doc/006 修5] 補充i 修正日期92.4.30 第5圖繪示爲依照本發明一較佳實施例用於記憶體 上全晶片元件中N型基底上之多電源P型金氧半電晶體； 第6圖繪示爲依照本發明一較佳實施例用於記憶體 上全晶片元件中N型基底上之反向器； 第7圖繪示爲依照本發明一較佳實施例用於記憶體 上全晶片元件中N型基底上之單電源N型金氧半電晶體； 以及 第8圖繪示爲依照本發明一較佳實施例用於記憶體 上全晶片元件中N型基底上之單電源P型金氧半電晶體。 圖式之標示說明： 100、200、300 :線路設計 102 : Hard macro 佈局 10 4 :全晶片繞線 106 、 116 、 210 、 314 : Tape out 110、204、304 :高階硬體描述語言編程 112、206、306 :合成 114 :自動繞線 202 : Hard macro佈局與功能描述 208 :搭配Hard macro進行全晶片繞線 302 :將線路設計轉換爲verilog或EDIF格式 308 :全晶片之netlist結合 310 :全晶片配置與繞線設計 312 :全晶片後設計合成 400、500、600 ·· N 型基材底 9 559711 08217twfl.doc/006 〜 \ 修正日期 92.4.30 ； ! I :丨 v … „ …·-:二.i 401、501、601、701、801 :繞線邊界 402 、 702 、 802 : P 井 404、504、604a、604b :源極/汲極 406、506、606a、606b :井接觸 408、508、608a、608b :閘極 410、412、510、512、610、612 :線路 704、706、804 ' 806 :線路 414、 514 ' 516 ' 614 ' 616 :信號線路 415、 515、615、517、617 :插塞 502a 、 602a : P 井 502b 、 602a :深 P 井 518 、 618 : N 井 708 : N型金氧半 808 : P型金氧半 較佳實施例 首先請參照第3圖，其繪示爲依照本發明一較佳實 施例用於記憶體上全晶片元件的設計流程圖。本實施例 中，用於記憶體上全晶片元件的設計流程包括線路設計 300、將線路設計轉換爲verilog或EDIF格式302、高階 硬體描述語百編程304、合成306、全晶片之netlist結合 308全晶片配置與繞線設計310、全晶片後設計合成312， 以及Tape out 314等步驟，其設計順序如圖所示。 通常Hard macro係由脈衝產生器、電容、電阻、電 晶體以及高壓元件等集中設計而構成，故對習知技術而言 10 559711 08217twfl.doc/006Revised 92.4.30 part). After the combination, the configuration and winding design of the whole wafer and the post-layout synthesis of the whole wafer are performed to complete the automatic configuration and winding of the whole wafer. In the present invention, a single-cell automatic winding method (cell base autorouting) is applied to a high voltage device, such as an N-type metal-oxide semi-transistor, a P-type metal-oxygen semi-transistor, and an N-type and P-type metal oxide. An inverter composed of a semi-transistor performs an automatic winding method. In the present invention, the size of the entire N-type metal-oxide semiconductor transistor, P-type metal-oxide semiconductor transistor and inverter is defined as an integer multiple of a standard cell (or a non-integer multiple, depending on software) ) And wind it on it. Multiple bypass lines are provided as Vss and VDD, where Vss and VDD are two power sources that can be recognized by the software, and the well contact is used as a signal line for winding. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1A is shown as Design flow chart of conventional memory; Figure 1B is a design flow chart of the conventional logic; Figure 2 is a design flow chart of the conventional memory module; Figure 3 is a comparison chart according to the present invention. Design flow chart of a preferred embodiment for a full-chip device on a memory; FIG. 4 shows a multi-power N-type metal oxide on an N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention Semi-transistor; 559711 08217twfl.doc / 006 Rev. 5] Supplement i Correction date 92.4.30 Figure 5 shows the multiple power supplies on an N-type substrate in a full-chip device on a memory in accordance with a preferred embodiment of the present invention P-type metal-oxide semiconductor; FIG. 6 shows an inverter used on an N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention; FIG. 7 shows a first inverter according to the present invention. The preferred embodiment is used for single power on N-type substrates in full-chip components on memory. Source N-type metal-oxide-semiconductor; and FIG. 8 shows a single-power P-type metal-oxide-semiconductor on a N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention. Description of the diagrams: 100, 200, 300: circuit design 102: Hard macro layout 10 4: full chip winding 106, 116, 210, 314: Tape out 110, 204, 304: high-level hardware description language programming 112, 206, 306: Synthesis 114: Automatic winding 202: Hard macro layout and functional description 208: Full-chip winding with Hard macro 302: Converting the circuit design to verilog or EDIF format 308: Netlist of full-chip combination 310: Full-chip Configuration and winding design 312: Designed after full chip synthesis 400, 500, 600 ·· N-type substrate bottom 9 559711 08217twfl.doc / 006 ~ \ Correction date 92.4.30;! I: 丨 v……… II. 401, 501, 601, 701, 801: Winding boundary 402, 702, 802: P wells 404, 504, 604a, 604b: Source / drain 406, 506, 606a, 606b: Well contact 408, 508 , 608a, 608b: Gates 410, 412, 510, 512, 610, 612: Lines 704, 706, 804 '806: Lines 414, 514' 516 '614' 616: Signal lines 415, 515, 615, 517, 617 : Plugs 502a, 602a: P wells 502b, 602a: Deep P wells 518, 618: N wells 708: N-type metal-oxygen half 8 08: P-type metal-oxygen semi-preferred embodiment First, please refer to FIG. 3, which shows a design flowchart for a full-chip device on a memory according to a preferred embodiment of the present invention. In this embodiment, The design flow of all-chip components on the memory includes circuit design 300, converting the circuit design to verilog or EDIF format 302, high-level hardware description 100 programming 304, synthesis 306, full-chip netlist combined with 308 full-chip configuration and winding design Step 310, design and synthesis of 312 after the whole chip, and Tape out 314. The design sequence is shown in the figure. Usually, Hard macro is composed of pulse generator, capacitor, resistor, transistor and high voltage components. In terms of know-how 10 559711 08217twfl.doc / 006
修正日期92.4.30 這些元件皆爲無法合成（non-synthesisable )的。然而，本 實施例中藉由自動配置與繞線工具同時對邏輯閘層次部 份、電晶體層次部份以及其他不可合成電路部份同時進行 自動繞線。換言之，本實施例在線路設計300的步驟中， 係將Hard macro中拆成多個電晶體層次的元件以進行自動 化的設計，而其他不可合成電路部份亦以類似方式進行設 計，其作法詳述如下。 在同一晶片超過2個電源線路的情況下，以單體自 動繞線的方式（cell base auto_routing )進行繞線。本實施 例藉由自動繞線軟體，例如是Avanti公司的Apollo或是 Cadence公司的SE，提供多個旁通的線路以作爲Vss與 VDD，其中Vss與Vdd爲軟體可辨識的兩個電源（power )， 並將超過2個的電源線路當作信號線路而進行繞線，以達 到將Hard macro中所有元件進行自動繞線的目的。將超過 2個的電源線路當作信號線路進行繞線不但能夠突破自動 配置與繞線工具（APR Tool )僅能辨識兩個電源的瓶頸， 且能夠對Hard macro中的各個元件進行自動繞線。上述僅 以Apollo軟體或SE軟體作爲說明，但並非限定本發明僅 適用於此軟體。 本發明之用於記憶體上全晶片元件設計方法，將上 述Hard macro中的線路設計轉換成例如verilog或EDIF 的格式之後，將其與Hard macro以外之其他部份（如邏輯 部份）結合。而在結合之後，進行全晶片的配置與繞線設 計以及全晶片後設計合成（post-layout synthesis )，即完成 11 559711 08217twfl.doc/00Revision date 92.4.30 These components are non-synthesisable. However, in this embodiment, an automatic configuration and a winding tool are used to automatically wind the logic gate level part, the transistor level part, and other non-synthesizable circuit parts simultaneously. In other words, in the step of the circuit design 300 of this embodiment, the hard macro is divided into multiple transistor-level components for automated design, and other non-synthesizable circuit parts are also designed in a similar manner. The method is detailed As described below. When there are more than two power lines on the same chip, the wire is wound in a cell base auto_routing method. In this embodiment, by using automatic winding software, for example, Apollo from Avanti or SE from Cadence, multiple bypass lines are provided as Vss and VDD, where Vss and Vdd are two power sources identifiable by the software (power ), And more than 2 power lines are used as signal lines for winding, so as to achieve the purpose of automatically winding all the components in the Hard macro. Using more than 2 power lines as signal lines for winding can not only break through the bottleneck of the automatic configuration and winding tool (APR Tool), which can only identify two power sources, but also can automatically wind each component in the Hard macro. The above description is only based on the Apollo software or the SE software, but it is not limited that the present invention is only applicable to this software. According to the method for designing a full-chip device on a memory of the present invention, after the circuit design in the above-mentioned hard macro is converted into a format such as verilog or EDIF, it is combined with other parts (such as a logic part) other than the hard macro. After the combination, the configuration and winding design of the whole chip and the post-layout synthesis of the whole chip are completed, that is, 11 559711 08217twfl.doc / 00 is completed
修正日期92.4.30 全晶片的自動化配置與繞線。 此外，Hard macro中有關脈衝產生器、電容、電阻、 電晶體以及高壓元件的輸入容量（input C )、配線延伸的 負荷（fan-out load )、最大電容（maximum capacitance )以 及時間資訊（timing information )等皆記錄於.lib的檔案 中。 接著請參照第4圖’其繪不爲依照本發明一*較佳實 施例用於記憶體上全晶片元件中N型基底上之多電源N 型金氧半電晶體。N型基底400中具有一 P井402。P井402 接近基底400的表面具有一源極/汲極404與一井接觸（weii contact )406，而在N型基底400上具有一聞極408。 藉由自動繞線軟體（APR Tool ) ’例如是例如Avanti 公司的Apollo或是Cadence公司的SE軟體，於繞線邊界 (PR boundary )401內提供多個旁通的線路410、412，線 路410、412例如是與Vss與VDD的電壓連接，其中Vss與 VDD爲軟體可辨識的兩個電源（Power )，並將電源線路當 作信號線路414進行繞線。其中’信號線路414例如是藉 由一插塞415與井接觸406，且信號線路414係與一電壓 VDP連接，如此，即可達到將Hard macro中所有元件進行 自動繞線的目的。Amendment date 92.4.30 Full chip automatic configuration and winding. In addition, the hard macro includes the input capacity (input C) of pulse generators, capacitors, resistors, transistors, and high-voltage components, fan-out load, maximum capacitance, and timing information. ) And so on are recorded in the .lib file. Next, please refer to FIG. 4 ', which shows a multi-power N-type metal-oxide-semiconductor on a N-type substrate in a full-chip device on a memory according to a * preferred embodiment of the present invention. The N-type substrate 400 has a P-well 402 therein. A surface of the P-well 402 near the substrate 400 has a source / drain 404 and a wei contact 406, and an N-type substrate 400 has a snare electrode 408. By using the automatic winding software (APR Tool), for example, Apollo from Avanti or SE software from Cadence, a plurality of bypass lines 410, 412, 410, 412 is, for example, connected to the voltages of Vss and VDD, where Vss and VDD are two power sources (Power) recognizable by software, and the power supply line is used as a signal line 414 for winding. The signal line 414 is in contact with the well 406 through a plug 415, for example, and the signal line 414 is connected to a voltage VDP. In this way, the purpose of automatically winding all components in the Hard macro can be achieved.
接著請參照第5圖’其繪不爲依照本發明一較佳實 施例用於記憶體上全晶片元件中N型基底上之多電源p型 金氧半電晶體。N型基底500中具有一 P井502a以及一 深P井502b，而在P井502a與深p井5〇2b內具有一 N 12 559711 修正日期92.4.30 08217twfl.doc/006 t 井518。其中，在N并518靠近基底500表面具有一源極/ 汲極504與一井接觸506，而在N型基底500上具有一閘 極 508 〇 藉由自動繞線軟體’例如是例如Avanti公司的Αρο 11 〇 或是Cadence公司的SE軟體，於繞線邊界（PR boundary )501內提供多個旁通的線路510、512,線路510、 512例如是與Vss與VDD的電壓連接，其中vss與VDD爲 軟體可辨識的兩個電源，並將電源線路當作信號線路514、 516進行繞線。其中，信號線路514例如是藉由插塞515 與P井502a電性連接，且信號線路514係與一電壓VDP 連接，而信號線路516例如是藉由插塞517與井接觸506 電性連接，且信號線路516係與一電壓VB連接，如此即 可對Hard macro中所有元件進行自動繞線的目的。 接著請參照第6圖，其繪示爲依照本發明一較佳實 施例用於記憶體上全晶片元件中N型基底上之反向器。N 型基底600中具有一 P井602a及一深P井602b，而在P 井602a與深P井602b內具有一 N井618。其中，在P 井602a靠近基底600表面具有一源極/汲極604a與一井接 觸606a，且在P并上方具有一閘極608a。此外，在N井 618靠近基底600表面具有一源極/汲極604b與一井接觸 606b，且在N型基底600表面具有一源極/汲極604b。 藉由自動繞線軟體，例如是例如Avanti公司的Apollo 或是Cadence公司的SE軟體，於繞線邊界（PR boundary )601內提供多個旁通的線路610、612,線路610、 13 559711 修正日期92.4.30 08217twfl.doc/006 612例如是與Vss與VDD的電壓連接，其中\^5與\^0爲 軟體可辨識的兩個電源，並將電源線路當作信號線路614、 616進行繞線。其中，信號線路6〗4例如是藉由插塞615 與P井602a電性連接，且信號線路614係與一電壓Vdp 連接’而信號線路616例如是藉由插塞617與井接觸606 電性連接，且信號線路616係與一電壓Vb連接，如此即 可對Hard macro中所有元件進行自動繞線的目的。 接著請參照第7圖，其繪示爲依照本發明一較佳實 施例用於記憶體上全晶片元件中N型基底上之單電源N 型金氧半電晶體。N型基底700中具有一 p井702，P井 分佈的區域如圖所示，而在P井702於基底700表面上具 有一 N型金氧半電晶體708。 藉由自動繞線軟體’例如是例如Avanti公司的Apollo 或是Cadence公司的SE軟體，於繞線邊界（pR boundary )701內提供多個的線路704、706。其中，線路704、 706例如配置於繞線邊界的邊緣，線路704與Vss的電壓 連接，而線路706例如係配置於p井702上方而與VDD的 電壓連接。上述Vss與VDD爲軟體可辨識的兩個電源。 最後請參照第8圖，其繪示爲依照本發明一較佳實 施例用於記憶體上全晶片元件中N型基底上之單電源P型 金氧半電晶體。N型基底800中具有一* P井802，P井分 佈的區域如圖所示，而在P井802分佈區域以外之基底800 表面上具有一 P型金氧半電晶體808。 藉由自動繞線軟體，例如是例如Avanti公司的Apollo 559711 08217twfl.doc/006 Ί 修正曰期92.4.30 ·;- i -ϋί 或是Cadence公司的SE軟體，於繞線邊界（PR boundary )801內提供多個的線路804、806。其中，線804、 806例如配置於繞線邊界的邊緣，線路804與Vss的電壓 連接，而線路806例如係配置於P井802上方而與VDD的 電壓連接。上述Vss與VDD爲軟體可辨識的兩個電源。 上述實施例中，僅以N型基底（N-type substrate )上 單電源或多電源的P型金氧半電晶體、N型金氧半電晶體 以及反向器作爲說明，但並非限定本發明。本發明亦可應 用在P型基底上之元件設計。 綜上所述，本發明用於記憶體上的全晶片元件設計 方法至少具有下列優點： 1·本發明用於記憶體上的全晶片元件設計方法，係將 Hard macro打散成電晶體層次的元件以進行自動繞線，克 服習知Hard macro本身無法自動化繞線的瓶頸。 2·本發明用於記憶體上的全晶片元件設計方法中，提 供作爲Vss與VDD之線路後，再將其他電源線路當作信號 線路進行繞線，克服自動繞線軟體只能辨認兩個電源 (power )的限制。 3.本發明用於記憶體上的全晶片元件設計方法中，藉 由自動配置與繞線工具同時對邏輯閘層次部份、電晶體層 次部份以及其他不可合成電路部份進行自動繞線，可以大 幅度的縮短元件設計的時間。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 15 08217twfl.doc/006 [ ρ I 3>年斗R丨乂 — 修正曰期92.4.30 1 補无1 559711 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 16Next, please refer to FIG. 5 ', which depicts a multi-power p-type metal-oxide semiconductor transistor on an N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention. The N-type substrate 500 has a P well 502a and a deep P well 502b, and within the P well 502a and the deep p well 502b, there is an N 12 559711 correction date of 92.4.30 08217twfl.doc / 006 t well 518. Among them, there is a source / drain 504 and a well contact 506 on the surface of N and 518 near the substrate 500, and a gate 508 on the N-type substrate 500. By using automatic winding software, for example, Avanti Αρο 11 〇 or SE software from Cadence Company, which provides multiple bypass lines 510, 512 within the winding boundary (PR boundary) 501. The lines 510, 512 are, for example, connected to Vss and VDD, where vss and VDD These are two power sources that can be recognized by the software, and the power supply lines are used as signal lines 514 and 516 for winding. The signal line 514 is, for example, electrically connected to the P well 502a through the plug 515, and the signal line 514 is connected to a voltage VDP, and the signal line 516 is, for example, electrically connected to the well contact 506 through the plug 517. And the signal line 516 is connected to a voltage VB, so that the purpose of automatically winding all the components in the Hard macro can be achieved. Please refer to FIG. 6, which shows an inverter for an N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention. The N-type substrate 600 has a P well 602a and a deep P well 602b, and an N well 618 in the P well 602a and the deep P well 602b. Among them, there is a source / drain 604a and a well contact 606a on the surface of the P-well 602a near the substrate 600, and a gate 608a above P-parallel. In addition, a surface of the N-well 618 near the substrate 600 has a source / drain 604b in contact with a well 606b, and a surface of the N-type substrate 600 has a source / drain 604b. With automatic winding software, such as, for example, Apollo from Avanti or SE software from Cadence, multiple bypass lines 610, 612, 610, and 13 559711 are provided within the winding boundary (PR boundary) 601. 92.4.30 08217twfl.doc / 006 612 For example, it is connected to the voltage of Vss and VDD, where \ ^ 5 and \ ^ 0 are two power sources that can be recognized by the software, and the power supply lines are used as signal lines 614 and 616 for winding. . Among them, the signal line 6 is electrically connected to the P well 602a through the plug 615, and the signal line 614 is connected to a voltage Vdp, and the signal line 616 is electrically connected to the well 606 through the plug 617, for example. Connection, and the signal line 616 is connected to a voltage Vb, so that the purpose of automatic winding of all components in the Hard macro can be achieved. Please refer to FIG. 7, which shows a single-power N-type metal-oxide-semiconductor transistor on a N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention. The N-type substrate 700 has a p-well 702, and the area where the P-well is distributed is shown in the figure, and the P-well 702 has an N-type metal-oxide semiconductor 708 on the surface of the substrate 700. With the automatic winding software, for example, Apollo from Avanti or SE software from Cadence, a plurality of lines 704 and 706 are provided within a winding boundary (pR boundary) 701. Among them, the lines 704 and 706 are arranged at the edge of the winding boundary, the line 704 is connected to the voltage of Vss, and the line 706 is arranged above the p-well 702 and connected to the voltage of VDD. The above Vss and VDD are two power sources that can be recognized by software. Finally, please refer to FIG. 8, which shows a single-power P-type metal-oxide semiconductor transistor on an N-type substrate in a full-chip device on a memory according to a preferred embodiment of the present invention. The N-type substrate 800 has a * P well 802. The area distributed by the P well is shown in the figure, and a P-type metal-oxide semiconductor 808 is located on the surface of the substrate 800 outside the P-well 802 distribution area. By using automatic winding software, for example, Apollo 559711 08217twfl.doc / 006 of Avanti Company 修正 amended date 92.4.30 ·;-i -ϋί or SE software of Cadence Company, at the PR boundary 801 Provides multiple lines 804, 806. Among them, the lines 804 and 806 are arranged at the edge of the winding boundary, the line 804 is connected to the voltage of Vss, and the line 806 is arranged above the P well 802 and connected to the voltage of VDD. The above Vss and VDD are two power sources that can be recognized by software. In the above embodiments, only P-type metal-oxide-semiconductor, N-type metal-oxide-semiconductor, and inverter with a single power source or multiple power sources on an N-type substrate are used as illustrations, but the present invention is not limited thereto. . The present invention can also be applied to element design on a P-type substrate. In summary, the method for designing a full-chip device for use in a memory of the present invention has at least the following advantages: 1. The method for designing a full-chip device for use in a memory of the present invention is to break the Hard macro into a transistor level Components for automatic winding, to overcome the bottleneck that the conventional Hard macro itself cannot automatically wind. 2. The present invention is used in the design method of all-chip components on the memory. After providing the Vss and VDD lines, the other power supply lines are used as signal lines for winding. Overcoming the automatic winding software can only identify two power supplies. (power). 3. In the method for designing a full-chip component on a memory according to the present invention, automatic winding of a logic gate level part, a transistor level part, and other non-synthesizable circuit parts is performed by an automatic configuration and winding tool, Can greatly shorten the time of component design. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art will not depart from the present invention. 15 08217twfl.doc / 006 [ρ I 3 > 年 斗 R 丨 乂— Amendment date 92.4.30 1 Supplement No. 1 559711 In the spirit and scope, various changes and retouching can be made, so the scope of protection of the present invention shall be defined by the scope of the attached patent application. 16