CN111934684B - Buffer, clock grid circuit and signal driving method - Google Patents
Buffer, clock grid circuit and signal driving method Download PDFInfo
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- CN111934684B CN111934684B CN202010760899.2A CN202010760899A CN111934684B CN 111934684 B CN111934684 B CN 111934684B CN 202010760899 A CN202010760899 A CN 202010760899A CN 111934684 B CN111934684 B CN 111934684B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Abstract
The application provides a buffer, a clock grid circuit and a signal driving method, wherein the buffer comprises at least one buffer unit, at least one side of each buffer unit is provided with a decoupling unit, and each buffer unit is distributed with a power line and a ground line; the decoupling unit arranged for the buffer unit shares a power line and/or a ground line with the buffer unit, and when the decoupling unit shares the power line with the buffer unit, the decoupling unit shares the ground line which is the layout of the adjacent buffer unit with the buffer unit adjacent to the buffer unit; when sharing the ground line with the buffer cell, the decoupling cell shares the power line laid out for the adjacent buffer cell with the buffer cell adjacent to the buffer cell, wherein: the decoupling unit is used for stabilizing the power supply voltage of the buffer; each power line is used for being connected with the input end of the power supply; each ground wire is used for being connected with the ground end. Therefore, the driving capability of the buffer is improved, and the power supply stability of the buffer is improved.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a buffer, a clock grid circuit, and a signal driving method.
Background
The general driving capability of ordinary buffer is less than less, can not apply to the circuit of big driving capability, and the buffer that exists at present is generally applied to analog integrated circuit in addition, and the structure is complicated, and only uses as an solitary module, and for digital integrated circuit, need customize the buffer specially to satisfy the demand.
Therefore, how to provide a buffer with large driving capability is one of the considerable technical problems.
Disclosure of Invention
In view of the above, the present application provides a buffer, a clock grid circuit and a signal driving method for solving the problem of small driving capability of the conventional buffer.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, there is provided a buffer, comprising at least one buffer unit, at least one side of each buffer unit being provided with a decoupling unit, each buffer unit being laid out with a power line and a ground line; a decoupling unit provided for the buffer unit shares a power supply line and/or a ground line with the buffer unit, and when sharing a power supply line with the buffer unit, the decoupling unit shares a ground line laid out for the adjacent buffer unit with a buffer unit adjacent to the buffer unit; when sharing the ground line with the buffer cell, the decoupling cell shares the power line laid out for the adjacent buffer cell with the buffer cell adjacent to the buffer cell, wherein:
the decoupling unit is used for stabilizing the power supply voltage of the buffer;
each power line is used for being connected with the input end of the power supply;
each ground wire is used for being connected with the ground end.
According to a second aspect of the present application, there is provided a clock grid circuit comprising the buffer provided by the first aspect of the embodiments of the present application.
According to a third aspect of the present application, there is provided a signal driving method applied to an integrated circuit including the buffer provided in the first aspect of the embodiment of the present application, the method including:
outputting a clock signal through the buffer;
and driving the integrated circuit to work by using the clock signal.
The beneficial effects of the embodiment of the application are as follows:
the buffer, the clock grid circuit and the signal driving method provided by the embodiment of the application have the characteristics of large driving capability, small signal delay and small introduced parasitic parameters. The decoupling unit is arranged on at least one side of the buffer unit, so that the stability of the power supply voltage can be improved; and by laying a power line and a ground line for each buffer unit, when the power supply is switched on, each buffer unit is connected with one power line, which is equivalent to that each buffer unit outputs current, and finally the current output by the buffer is the sum of the currents of the buffer units, namely the buffer has larger driving current.
Drawings
FIG. 1 is a schematic illustration of an orientation provided by an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a buffer according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a single buffer cell placement decoupling cell provided by an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a buffer including 2 buffer units according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an antenna unit provided in an embodiment of the present application;
FIG. 6 is a schematic structural diagram of a transversely aligned buffer according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a longitudinally arranged buffer according to an embodiment of the present application;
fig. 8 is a schematic diagram illustrating routing and punching manners of M1-layer and M2-layer metal lines according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram illustrating routing and punching manners of M2-layer and M3-layer metal lines according to an embodiment of the present disclosure;
fig. 10 is a schematic view illustrating routing and punching manners of M8 layer and M9 layer metal lines according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if," as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination," depending on the context.
To facilitate understanding of the buffer provided in the present application, prior to describing the technical solutions of the present application, technical terms related to the present application will be described:
1. the Clock buffer (Clock buffer) is mainly used for ensuring synchronous transmission of data or clocks to achieve the effect of driving an amplification signal line.
2. A Clock tree (Clock tree) is a mesh structure which is built by a plurality of Clock buffers in a balanced mode, a Clock input end can be arranged, the output end of an internal circuit can also be built by one-stage Clock buffers, and the specific stage number is determined according to requirements and setting.
3. Antenna Effect (Antenna Effect), an Effect that occurs during the manufacturing process of integrated circuit chips, occurs mainly at exposed metal lines or polysilicon.
4. An Antenna cell (Antenna cell) for eliminating the Antenna effect.
5. Latch-up (Latch up) refers to a low impedance path generated between a power supply VDD and a ground GND (VSS) of a MOS transistor in an integrated circuit due to the mutual influence of parasitic PNP and NPN bipolar BJTs (bipolar junction transistors), so that a large current is generated between VDD and VSS.
6. A decoupling cell (Decap cell) is used to stabilize a power supply, and is usually disposed between a power line and a ground line to avoid the influence of a dynamic voltage drop on the circuit performance.
7. And a substrate cell (TAP cell) connected to the substrate potential applying unit to prevent the occurrence of latch-up.
8. In the present application, at least one side of the buffer unit may be understood as a left side, a right side, an upper left side, a lower left side, an upper side, a lower side, a right side, an upper right side, a lower right side, etc., and specifically, reference may be made to the schematic orientation diagram shown in fig. 1. It should be noted that fig. 1 is only a schematic orientation, and the length and width of the box in fig. 1 may be arbitrarily adjusted, which is not limited in the present application.
The following provides a detailed description of the buffer provided in the present application.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a buffer provided in the present application, where the buffer includes: at least one Buffer cell (Buffer cell) 201, wherein at least one side of each Buffer cell 201 is provided with a decoupling cell 202 (Decap cell), and each Buffer cell 201 is distributed with a power line VDD and a ground line VSS; the decoupling unit 202 provided for the buffer unit 201 shares a power supply line and/or a ground line with the buffer unit 201, and when sharing a power supply line with the buffer unit 201, the decoupling unit 202 shares a ground line laid out for the adjacent buffer unit 203 with the buffer unit 203 adjacent to the buffer unit 201; when sharing the ground with the buffer cell 202, the decoupling cell 202 shares the power line laid out for the adjacent buffer cell 203 with the buffer cell 203 adjacent to the buffer cell 201, wherein:
the decoupling unit 202 is configured to stabilize a power supply voltage of the buffer;
each power line VDD is used for being connected with the input end of a power supply;
each ground line VSS is used for connecting with a ground terminal.
Specifically, the number of Buffer cells in the Buffer unit Buffer cell is set according to actual requirements, and different driving capabilities of the Buffer can be realized by increasing the Buffer cells step by step. In addition, in order to improve the stability of the power supply voltage, a decoupling cell Decap cell may be added in the buffer, and for this purpose, a decoupling cell may be disposed on at least one side of each buffer cell in the present application, please refer to the schematic diagram of disposing a decoupling cell in a single buffer cell shown in fig. 3, so as to improve the stability of the power supply voltage. In addition, in order to make the buffer realize great driving capability, every buffer cell layout power cord VDD and a ground wire VSS in this application, namely, adopt the design scheme of multichannel, the quantity of power cord and ground wire has been increased, like this when the power input buffer, because every buffer cell all connects a power cord, be equivalent to every buffer cell all output current, the electric current of final buffer output is the sum of the electric current of each buffer cell, that is to say the buffer has great drive current, like this, when the buffer inserts the load, can drive great load, namely, effectively promoted the driving capability of buffer, the electric current bearing capacity of buffer has also been increased simultaneously.
In addition, when the buffer cell is the first or last buffer cell of the buffer, and the decoupling cell provided by the buffer cell may be located at the start position or the end position, the decoupling cell provided at the start position may separately lay out a power line VDD such that the decoupling cell is connected to the power line VDD, and the decoupling cell provided at the end position may need to provide a ground line VSS such that the decoupling cell is connected to the ground line VSS.
When the buffer units are not arranged at the head part and the tail part, the decoupling units arranged for the buffer units can share the power line and the ground line with the buffer units; or, since there may be a case where the decoupling unit is shared between the buffer units, on this basis, there may also be a case where the decoupling unit is located: the decoupling unit may also share a power line with the buffer unit and a ground line with an adjacent buffer unit of the buffer unit; alternatively, it is also possible to share one ground line with the buffer unit and then share a power supply line with an adjacent buffer unit of the buffer unit.
It is understood that the decoupling unit in this application may be located in different directions for different buffer units, for example, when the buffer includes a plurality of buffer units, such as the buffer shown in fig. 4, the buffer includes 2 buffer units, which are respectively denoted as buffer unit 1 and buffer unit 2, and the two buffer units are adjacent to each other, if the lower right side of the buffer unit 1 is provided with the decoupling unit, that is, the decoupling unit is located at the lower right side of the buffer unit 1 for the buffer unit 1, but is located at the upper right side of the buffer unit 2 for the buffer unit 2 because the buffer unit 1 and the buffer unit 2 share the decoupling unit.
It should be noted that the adjacent buffer cells in this application can be understood as buffer cells with relatively close distances, and referring to fig. 4, the buffer cells 1 and 2 belong to adjacent buffer cells, and in practical applications, the adjacent buffer cells also include the concept of close proximity, such as replacing the decoupling cell on the right side of the buffer cell 1 in fig. 4 with the buffer cell 2, in which case, the buffer cell 1 and the buffer cell 2 are close proximity.
Based on the above embodiment, the buffer further provided in this embodiment may further include a substrate unit TAP cell, and a substrate unit is further disposed on at least one side of each buffer unit, so that the decoupling unit and the substrate unit disposed for the buffer unit surround the buffer unit, where: the substrate unit is used to prevent the buffer from latch-up, as shown in fig. 3, wherein:
the substrate unit and the buffer unit arranged for the buffer unit share a power line and/or a ground line, and when the substrate unit and the buffer unit share the power line, the adjacent buffer unit of the substrate unit and the buffer unit shares the ground line for the layout of the adjacent buffer unit; when the substrate unit and the buffer unit share the ground wire, the substrate unit and the buffer unit adjacent to the buffer unit share the power wire laid out by the adjacent buffer unit.
Specifically, when the buffer unit is the first or last buffer unit of the buffer, and the substrate unit disposed in the buffer unit may be located at the start position or the end position, the substrate unit disposed at the start position may be separately laid out with one power line VDD so that the substrate unit is connected to the power line VDD, and the substrate unit disposed at the end position may be required to be laid out with one ground line VSS so that the substrate unit is connected to the ground line VSS.
When the buffer units are positioned at the non-head part and the non-tail part, the substrate units arranged for the buffer units can share the power line and the ground line with the buffer units; alternatively, since there may be a case where the substrate unit is shared between the buffer units, the substrate unit may be located as follows: the substrate unit may further share one power line with the buffer unit and a ground line with an adjacent buffer unit of the buffer unit; alternatively, it is also possible to share one ground line with the buffer unit and then share a power supply line with an adjacent buffer unit of the buffer unit.
On the basis, in the present embodiment, decoupling units may be disposed on the left upper side, the left lower side, and the right side of each buffer unit, and substrate units may be disposed on the right upper side and the right lower side of the buffer unit, as shown in fig. 3.
Alternatively, adjacent buffer cells may share the decoupling cell and the substrate cell, and as also shown in fig. 4, the buffer cell 1 and the buffer cell 2 in fig. 4 share the substrate cell and the decoupling cell.
The substrate unit is arranged for each buffer unit, so that the latch-up effect of the buffer can be effectively prevented, namely, the substrate unit is added, so that the PMOS substrate is connected with the power supply VDD, and the NMOS substrate is connected with the ground terminal VSS, and the latch up prevention effect is achieved.
Alternatively, during the fabrication of integrated circuit chips, when large areas of metal are connected to the gate, charge may be collected in exposed metal lines or conductors such as polysilicon, causing the potential to rise. The longer the antenna, the more charge collected and the higher the voltage. If the conductor that collects the charge touches the gate of the MOS transistor, the high voltage may break down the thin gate oxide, causing the circuit to fail, which is called the "Antenna Effect". With the development of process technology, the size of the grid is smaller and smaller, the number of metal layers is larger and larger, and the possibility of antenna effect is higher and higher. Therefore, when the buffer is manufactured, the influence of the antenna effect on the buffer is reduced. Therefore, for this purpose, the buffer provided by the present application may further include an antenna unit for canceling the antenna effect of the buffer, wherein:
the number of the antenna units and the positions of the antenna units in the buffer are determined by the number of the buffer units included in the buffer.
Specifically, as the buffer comprises more buffer units, the layout and the wiring are relatively more, and as the influence of the Antenna effect caused by excessive wiring on the buffer is reduced, the Antenna unit Antenna for eliminating the Antenna effect is arranged in the buffer, wherein when the circuit of the Antenna unit is implemented, the Antenna unit comprises an NMOS tube and a PMOS tube, as shown in fig. 5, an input end I of the Antenna unit is connected with a pin, when the Antenna effect occurs inside the buffer, the input end I accumulates a large amount of charges to cause the voltage of the input end I to be high, and the input end I is respectively connected with the gate gates of the PMOS tube and the NMOS tube, so that a large amount of charges also occur at the gate ends of the PMOS tube and the NMOS tube, the voltage of the gate terminals of the PMOS tube and the NMOS tube becomes high, the PMOS tube is cut off, the NMOS tube is connected, and the gate of the NMOS tube is connected with the source, so that a charge can be discharged between the gate of the NMOS tube and the source, and the threatened charge can not be discharged to achieve the purpose of eliminating the Antenna effect.
In addition, although the antenna units can eliminate the antenna effect, a large number of antenna units cannot be arranged in the buffer, if one antenna unit is arranged in each buffer unit, the buffer area is large, resources are wasted, and charge accumulation may occur when too many antenna units are wired, so that the antenna effect is formed. Therefore, in order to avoid this problem, when the antenna units are disposed in the buffer, the number and positions of the antenna units may be set according to the number of buffer units in the buffer, for example, the ratio of the antenna units to the buffer units is 1:2, and the antenna units may be disposed according to the ratio of the antenna units to the buffer units 1:2, as shown in fig. 4.
Optionally, the buffer in the embodiment of the present application includes buffer units arranged in a transverse and/or longitudinal manner. Referring to fig. 6 and 7, fig. 6 is a schematic structural diagram of a buffer with laterally arranged buffer units (H-type); FIG. 7 is a schematic diagram of the structure of a vertically aligned (V-plate) buffer.
Specifically, more wires are arranged in the transverse direction to bear current, and clocks with different driving capacities start to extend from the transverse direction to drive large-size buffers in the H version.
Optionally, the driving capability of the buffer provided in the embodiment of the present application is determined by a layout relationship between the buffer units therein.
Specifically, according to the difference of the driving capability, when the buffer unit is closer to the output signal, the driving capability of the buffer unit is stronger, so that the buffer can be in a gradual amplification trend through the layout buffer unit, the driving capability of different clock signals is required to be met when the buffer is designed, the chip can normally work, and in the layout design, the number of the buffer units can be sequentially increased to correspondingly increase the driving capability.
Optionally, the buffer provided in the embodiment of the present application may further include multiple layers of metal lines, and the metal lines of each layer are laid out in a grid-like wiring manner.
Specifically, a latticed routing manner can be adopted on the upper layer during automatic layout and wiring, so that routing space can be saved, the parasitic capacitance between the wires can be reduced by the crossed routing manner, and a smaller parasitic parameter RC is introduced, for example, the buffer comprises 9 layers of metal wires, which are marked as M1-M9, routing manners from M1 to M9 are adopted, the wire width is increased, the number of holes is increased as much as possible when the metal wires are punched, then long holes are adopted to replace square holes so as to increase the current bearing capacity of the metal wires, so that the buffer can bear larger current, and the resistance of the routing is reduced, referring to the routing and punching manners shown in fig. 8, 9 and 10, wherein fig. 8 is a routing and punching manner of the M1 layer and the M2 layer of metal wires, the M1 layer can be either horizontal or vertical, the M1 layer routing manner is represented by a solid line, the M2 layer is horizontal, the M2 layer of routing manner is represented by a dotted line, and the middle connection position between the M1 layer and the M2 layer is a through hole; fig. 9 shows routing and punching manners of metal lines of the M2 layer and the M3 layer, where the M2 layer adopts transverse routing and is indicated by a dotted line; the M3 layer adopts longitudinal wiring, indicated by a solid line, and wiring paths can be increased by multiple holes; fig. 10 shows the routing and punching manner of the metal lines of the M8 layer and the M9 layer, where the M8 layer employs horizontal routing, which is indicated by dotted lines; the M9 layer adopts longitudinal wiring, is represented by a solid line, and can increase the line width as much as possible to realize multi-punching. The M2 layer adopts the horizontal wiring layout, the M3 layer adopts the longitudinal wiring layout, and the rest layers are analogized in the same way until the M9 layer (top metal) connects out a signal pin, so that the line-to-line capacitance can be effectively reduced, and the wiring space is increased. Increasing the routing paths between lines as much as possible also reduces the resistance between lines. It should be noted that the M2 layer may also adopt a longitudinal routing, then the M3 layer adopts a transverse routing, and so on until the M9 layer is completed.
Based on the buffer provided by the application, the large driving capability is realized, and the characteristics of small signal delay and small introduced parasitic parameter are achieved. The decoupling unit is arranged on at least one side of the buffer unit, so that the stability of the power supply voltage can be improved; and by laying a power line and a ground line for each buffer unit, when the power supply is switched on, each buffer unit is connected with one power line, which is equivalent to that each buffer unit outputs current, and finally the current output by the buffer is the sum of the currents of the buffer units, namely the buffer has larger driving current.
Optionally, based on the same inventive concept, the present application further provides a clock grid circuit, where the clock grid circuit includes the buffer provided in any of the above embodiments. Specifically, the Clock grid circuit can be, but is not limited to, a Clock tree and a Clock mesh, that is, the buffer provided by the present application is applied to the Clock tree and the Clock mesh, and other components except the buffer in the Clock tree and the Clock mesh still adopt the existing components, but due to the application of the buffer with large driving capability provided by the present application, a large Clock signal can be better provided for the Clock grid circuit, so as to meet the requirement of the Clock grid circuit.
Optionally, based on the same inventive concept, the present application further provides a signal driving method, applied to an integrated circuit including the buffer provided in any of the above embodiments, where the method may include the following processes: outputting a clock signal through a buffer; and driving the integrated circuit to work by using a clock signal.
By implementing the method, the buffer provided by the application is used for providing the clock signal for the integrated circuit, and the requirement of the integrated circuit on the clock signal can be met.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A buffer, comprising: at least one buffer unit, wherein at least one side of each buffer unit is provided with a decoupling unit, and each buffer unit is distributed with a power line and a ground line; the decoupling unit arranged for the buffer unit shares a power line and/or a ground line with the buffer unit, and when the decoupling unit shares the power line with the buffer unit, the decoupling unit shares the ground line which is the layout of the adjacent buffer unit with the buffer unit adjacent to the buffer unit; when sharing the ground line with the buffer cell, the decoupling cell shares the power line laid out for the adjacent buffer cell with the buffer cell adjacent to the buffer cell, wherein:
the decoupling unit is used for stabilizing the power supply voltage of the buffer;
each power line is used for being connected with the input end of the power supply;
each ground wire is used for being connected with the ground end.
2. The buffer according to claim 1, wherein at least one side of each buffer cell is further provided with a substrate unit so that the decoupling unit and the substrate unit provided for the buffer cell surround the buffer cell, wherein: the substrate unit is used for preventing the buffer from latch-up, wherein:
the substrate unit and the buffer unit arranged for the buffer unit share a power line and/or a ground line, and when the substrate unit and the buffer unit share the power line, the substrate unit and the buffer unit adjacent to the buffer unit share the ground line for the layout of the adjacent buffer unit; when the substrate unit and the buffer unit share the ground wire, the adjacent buffer units of the substrate unit and the buffer unit share the power wire laid out by the adjacent buffer units.
3. The buffer according to claim 2, wherein the upper left side, the lower left side, and the right side of each buffer cell are provided with decoupling cells, and the upper right side and the lower right side of the buffer cell are provided with substrate cells.
4. A buffer according to claim 2 or 3 wherein adjacent buffer cells share decoupling cells and substrate cells.
5. The buffer of claim 1, further comprising an antenna unit to cancel an antenna effect of the buffer, wherein:
the number of antenna elements and the positions of the antenna elements in the buffer are determined by the number of buffer elements comprised by the buffer.
6. The buffer of claim 1, further comprising a plurality of layers of metal lines, wherein the layers of metal lines are laid out in a grid-like pattern.
7. The damper of claim 1, wherein the respective damping units are arranged in a lateral and/or longitudinal manner.
8. The buffer of claim 1, wherein the driving capability of the buffer is determined by a layout relationship between buffer cells therein.
9. A clock grid circuit comprising a buffer as claimed in any one of claims 1 to 8.
10. A signal driving method applied to an integrated circuit including the buffer according to any one of claims 1 to 8, the method comprising:
outputting a clock signal through the buffer;
and driving the integrated circuit to work by using the clock signal.
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