558703 A7 B7 五、發明說明（ 诚 領 明 發 中 板 示 顯 晶 液 在 動 log 於 用 置 裝 • 1111 種1 於 關 傺 明 發 本 法 方 之 其 訪 33 作 及 線 料 資 之 比 類 收 接 為 計 設 是 般1 件 元 示 顯 晶 液 色 彩 全 衞型 抟比 前類 先 明 型信放 比比衝 類類緩 之在一 此理之 如處成 在是形 。號上 號信片 信料基 料資器 資比接 比類連 類 ，一 些中過 這件通 理元並 處示 .， 及顯中 ,晶路 號液電 信色理 料彩處 資全號 經濟部智慧財彦局員工消費合作社印製 大器及一佈線匯流排而傳輸至一 LCD(液晶顯示器）之驅 動器積體電路中。LCD驅動器積體電路是水平配置在液 晶顯示板中並驅動液晶顯示板之一資料線。LCD驅動器 積體電路接收類比資料信號，取樣及保持所接收之類比 資料信號，及適當地傳送一電壓信號至液晶顯示板。第1圖是一習知類比型LCD驅動器積體電路之方塊圖。圖說之類比型LCD驅動器積體電路10之組成包含：η 個通道之移位暫存器3}{1至31?11; —資料線11，接收一 類比資料信號；開關3¥1迄3¥11分別電氣連接至每一資 料線11;取樣及保持電路3/Η1·3/Ηιι，分別電氣連接 至Sh-SWn;及一輸出放大器12，電氣連接至取樣及 保持電路S/fUgS/Hn,用以驅動一液晶顯示板之資料 線。 當移位暫存器SR i迄SRn收到一起動脈衝時，第一移位 暫存器8^迄31111傳送一起動脈衝，作為移位脈衝SROi 迄SROn與時脈信號同步，至開關3»1迄3»11。 ---i-------* — --------* 訂—1------—^wi (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 558703 A7 __ B7_ 五、發明說明（2 ) 開關SW ：l迄SWn是分別由移位暫存器SR i迄SRn傳送之 移位脈衝SRO i迄SROn控制於其操作中。即是在收到移 位脈衝SROi迄SROn時，開關SWi-SWn偽根據移位脈衝 SROi迄31?〇11,自第一開關SWi迄第η個開關SWn,連續 地閉合及關斷。 舉例言之，當第一開關S W i是持續閉合，類比資料在 第一次取樣中被取樣並保持在一保持電容器中，而保持 電路S/Hi電氣地連接至第一開關SWi。在全部取樣及 保持電路S/Hi -S/Hri完成取樣及保持類比資料在其保 持電容器中後，液晶板同時地經輸出放大器12被驅動。 一類比型全彩色LCD包括習知之類比型LCD驅動器積體 電路10僳伴隨有下面之困難。 資料轉移速率被增加，此像因LCD之解析度自XG A增加 至SXGA及UXGA之故。但是習知之類比型金彩色LCD不能 提高其處理速率。 其原因如下，由於資料線11及開關皆是電 氣連接至安裝在一信號處理基片上之緩衝放大器，包括 ---Γ------h 丨— ----l·---'訂 ---------線 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 負在 晶圖液影 之持 液至之比 高保 種加議類 甚以70一 施提到 一 電 t 議壓是收 之充 Η 提電別在 抗於 Μ 號階特 ， 阻用tt3 分。路 之，M27一像電 線果M22之影持 佈結 M6-誤之保 之其 ο 第錯值及 成 。^1，之品樣 形上U告小高取 上器11公常示個 片大sf1利非顯多 基放_專具成含 器衝BIS之中達包 接緩1«査其而是 連在DS審，因件 一加LC未件，元 在施型本元極示 成是比日示電顯 形載類 顯素晶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 558703 經濟部智慧財產局員工消費合作社印製 A7 _ _ B7 ___ 五、發明說明（3 ) 像信號時，實行取樣及保持操作，並在每一水平掃描期 間之每一線産生一分階電壓。類比影像信號經過一第一 信號線傳輸至實行第η次取樣及保持操作之取樣及保持 電路，而類比影像信號則是經過一第二信號線傳送至實 行第m次取樣及保持操作之取樣及保持電路，其中η是 一奇數而m是一偶數。 日本未審査之專利公告第7-191631號提議一活性矩陣 型液晶顯示元件，其中之第一及第二紅色類比影像信號 相互有一半週期之相位分離及是首先發生者，而第一紅 色類比影像信號經過一第一信號線被取樣及保持在第η 次取樣及保持電路中，而第二紅色類比影像信號則經過 一第二信號線被取樣及保持在第m次取樣及保持電路中 ，其中η是一奇數而m是一偶數。 日本未審査之專利公告第10-143118號提議一活性矩 陣顯示元件。在此提議之活性矩陣顯示元件中，每一閘 極線是在其中心被分割成兩段，及一垂直掃描電路是與 閘極線之每一段相聯合。每一信號線是分割為兩段。一 預充電器以不同之時序施加一預充電信號至信號線之各 段。一水平掃描電路取樣此信號線，自信號線之左至其 左段中之分割點，取樣此信號線，自右至信號線右段之 分割點，及寫入影像至如此之取樣信號線。 日本未審査專利公告第10-198321號曾提議一活性矩 陣顯示元件。其包括··閘極線配置成行，信號線配置成 列，圖素配置在閘極線與信號線之相交處，在一水平掃 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---y-------r----------^訂 -------線 (請先閱讀背面之注意事項再填寫本頁) 558703 經濟部智慧財彦局員工消費合作社印製 A7 _B7_ 五、發明說明（4 ) 描期間，一垂直掃描電路掃描閘極線並選擇一行圖素； 當一水平掃描期間，一水平掃描電路取樣在信號線中之 影像信號並寫入影像信號至選擇之圖素之一行。及一預 充電路在影像信號寫入至圔素中之前，施加一預充電信 號至每一信號線。每一鬧極線是在螢幕之中心處分割成 左段及右段。垂直掃描電路與分割之閘極線聯合，亦是 分割成左段及右段。此左段及右段分別選擇在左半及右 半列中之圖素於一水平掃描期間。預充電器在影像寫入 至信號線之左半列中之圖素前，施加一預充電信號至信 號線之左段；並在影像寫入至信號線之右半列中之圖素 前，施加一預充電信號至信號線之右段。 上面提及之問題即使在上面所提及之公告中提議之顯 示元件中仍未解決。 發明簡沭 本發明之一目標是提供一種用在液晶顯示元件中驅動 一資料線之裝置，此裝置是能增高在類比型全彩色LCD 中操作之速率。 本發明之另一目標是提供一種用在液晶顯示元件中驅 動一資料線之方法，此方法能有相同之作用。 在本發明之一局面中，提供有一用在一液晶顯示板中 驅動一資料線之裝置，其包括：（a)—資料線，其中輸 入一類比資料信號，（b)至少一移位暫存器，發送一移 位脈衝，及（c)至少一電路，用於根據移位脈衝，取樣 及保持類比資料信號，並傳送一電壓信號，其資料線包 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --1-------L----------•訂—------線 (請先閱讀背面之注意事項再填寫本頁) 558703 經濟部智慧財產局員工消費合作社印製 A7 ____B7___ 五、發明說明（5 ) 含第一及第二分段之資料線，其類比資料信號是輸入至 此第一及第二分段資料線之一。 進一步提供有一種裝置，用於在一液晶顯示板中驅動 一資料線，其包括（a)—資料線，其中輸入一類比資料 信號，（b)至少一移位暫存器，發送一移位脈衝，及（c) 呈少一電路，用於根據移位脈衝，取樣及保持類比資料 信號，並傳送一電壓信號，其資料線包含第一迄第Ν’値 分段資料線，其類比資料信號是輸入至此第一迄第Ν個 分段資料線之一，其中Ν是一等於或大於3之整數。 在本發明之另一局面中，提供有一液晶顯示元件，包 括（a)—液晶顯示板，（b)多個驅動器積體電路，以串接 安置在液晶顯示板上，用於驅動在液晶顯示板中之資料 線，及（c ) 一信號處理器，接收同步信號及類比影像信 號，處理此類比影像信號，並傳送經如此處理之類比影 像信號至每一個驅動器積體電路，及又傳送一起動脈衝 至驅動器積體電路中之一第一驅動器積體電路，起動脈 衝像自驅動器積體電路中之一驅動器積體電路傳送至一 鄰近之驅動器積體電路，每一個驅動器積體電路之組成 包含上面提及之裝置，用於驅動在一液晶顯示板中之一 資料線。 在本發明之又一局面中，提供有一種在液晶顯示板中 驅動一資料線之方法，其包括之步驟為：（8)輸入一類 比資料信號至第一迄第N個分段資料線中選出之一個， 其中N是一等於或大於2之整數，（b)根據一移位脈衝， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ：-------«-----------•訂i·-------線 (請先閱讀背面之注意事項再填寫本頁) 558703 A7 B7__ 五、發明說明（6 ) 取樣及保持此類比資料信號，藉以傳送一電壓信號，及 (〇根據此電壓信號，驅動一資料細。 上面提及之本發明所獲得之利益將說明如下。 根據本發明，在本裝置中之一資料線是分割成兩個或 更多個之分段資料線。因之資料線之佈線電阻值及電容 量皆減小，此外，電氣連接在資料線與取樣及保持電路 間之開關得以減少，故確保由開關導致之寄生電容量亦 是減小了。 — 更加，由於轉變成活性之分段資料線僅是資料線之一 部分，故可能降低在緩衝放大器上施加之負載，確保類 比型全彩色LCD操作速率之提高。加之由於相同之理由， 施加在緩衝放大器之負載能予降低，確保在類比型全彩 色LCD中電力消耗之降低。 S外，資料線之分段更增強用於充電一保持電容器之 特性，此電容器定位在距輸入端子之最遠處，類比資料 信號即在該端子輸入至資料線中。藉由輸入一類比資料 信號至裝置之中心處，就可能減輕在裝置中諸充電特性 間之差異，其能確保一類比型全彩色LCD影像品質之增 ---：------——--------tT· — ·^-------線 (請先閱讀背面之注意事項再填寫本頁) 強 經濟部智慧財產局員工消費合作社印製 同 相 之 置 裝 知 習 如 是 號 信 料 資 比 類 明 發 本 據 根 又 置顯裝明 裝晶該說 至液代II 入之替簡 輸置以之 式裝置 一亚 方之裝圍 線之 料明 資發 一 本 動據 驅根 於用 用霈 括僅 包 ， 之用 存使 現以 是加 由能 。板 中 示 可 即 置 釐 公 97 2 X 10 2 ___' 格 規 4 NS)A (C 準 標 家 國 國 中 用 適 度 尺 張 紙 本 經濟部智慧財產局員工消費合作社印製 558703 A7 _ B7 五、發明說明（7 ) 第1圖是習知之類比型LCD驅動器積體電路之方塊圖。 第2圖是根據本發明之一實施例，用於在一液晶顯示 板中驅動一資料線之一裝置之方塊圖。 第3 A圖是一開關控制電路之一實例之方塊圖。 第3 B圖是又一開關控制電路之一實例之方塊圖。 第3 C圖是另一開關控制電路之一實例之方塊圖。 第4圖是第2圖中圖說裝置之時序圖。 第5圖是包括第2圖中圖説裝置之一類比型全彩色 液晶顯示元件之方塊圖。 第6圖是根據本發明之另一實施例，用於在一液晶顯 示板中驅動一資料線之一裝置之局部方塊圖。 遷L佳管渝例說明 第2圖是根據本發明之一最佳實施例，用於在一液晶 顯示板中驅動一資料線之一裝置（以後引用為"驅動器 1C，·）。 圖中之驅動器IC2 0之組成包含.· 一第一組移位暫存器 SRi迄SRn/2，一第二組移位暫存器SR n/2+1迄S R η，一 第一分段資料線21a，一第二分段資料線21b，一第一組 取樣及保持電路S/1U迄3/11?1/2，一第二組取樣及保持 電路S/H n/2+1g S/Hn, —第一組開關SW !迄SW n/2定位 於第一分段資料線21 a與第一組取樣及保持電路S/Hi迄 S/Hn/2之間，一第二組開關SWn/2+l迄SWn，定位於第二 分段資料線21b與第二組取樣及保持電路S/H n/2+1· S/Hn 之間，一主開關SWd，用於選擇第一與第二分段資料線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---7------J-----------:訂·1·-------線 (請先閱讀背面之注意事項再填寫本頁) 558703 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（) 2 la與2 lb之一，一開關控制電路22傳送一控制信號CON T 至主開關SWd，藉以控制主開關SWd之操作，而一輸出放 大器23電氣連接至第一組取樣及保持電路S/Ηχ迄S/Hn/2 及第二組取樣及保持開關S/Η 11/2+1迄S/Hn二者。在此， Μ η”傺指在一値驅動器1C中之通道數目。 一類比資料信號是通過一位在驅動器I C 2 0縱向側中央 之端子25，輸入至驅動器IC20中，並是通過主開關SWd， 輸入至第一及第二分段資料線21 a及21b之一中。 開關控制電路22根據第一及第二組移位暫存器SRi迄 SRn,傳送控制信號C0NT至主開關SWd。 移位暫存器SRi gSRn在當第一移位暫存器SRi接收 一起動脈衝HSP時，根據時脈信號連續傳送移位脈衝SROi 迄SROiu自第η個移位暫存器SRn傳送之一輸出信號是 作為起動脈衝，傳送至次级中之一驅動器1C。 第一組開關SWi迄SWn/2電氣連接第一分段線21a至第 一組取樣及保持電路S/Hi-S/Hn/s，或隔離第一分段 線21&與第一組取樣及保持電路3/111迄3/1111/2。第二組 開關SW n/2+1迄SWn則電氣連接第二分段線21b至第二組 取樣及保持電路S/H n/2+1迄S/Hn,或隔離第二分段線 21b與第二組取樣及保持電路S/Hn/2+l迄S/Hn。第一及 第二組取樣及保持電路S/Hi迄S/Η η是傳送他們的輸出， 通過輸出放大器23至驅動器IC20之外。 第3 Α圖是主開關SWd之一實例。主開關SWd之組成有： 一端子，通過此端子輸入類比資料信號；一第一類比開 -1 0 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------J-----------；訂-丨·-------線 (請先閱讀背面之注意事項再填寫本頁) 558703 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 關24a，電氣連接至第一分段資料線21a;及一第二類比 開關24b，電氣連接至第二分段資料線21b。第一及第二 類比開關24a及24b皆是由自開關控制電路2 2傳送之控制 信號CON T A及CON TB分別控制。 第3 B圖是開關控制電路22之一實例。開關控制電路22 之組成有：一第一 OR(或）電路26a，接收來自第一組移 位暫存器S R i迄S R n/2傳送之移位脈衝S R 0 i迄S R 〇n/2， 並傳送指示移位脈衝SR0丄迄SRO n/2之總和之第一控制 信號C0NTA;以及一第二OR電路26b，接收來自第二組移 位暫存器SRn/2+1迄SRn傳送之移位脈衝SR〇n/2+1迄SROn ，並傳送指示移位脈衝S R 0 n/2+1 gSROii之總和之第二控 制信號C 0 N T B。 第3 C圖是開關控制電路22之另一實例。此開關控制電 路22之組成有：一第一 SR正反器27a，由第一移位脈衝 SROi之前導緣定置，並由移位脈衝SROn/2之尾端緣重 置，其結果是傳送第一控制信號C0NTA;及一第二SR正 反器27b，由移位暫存器SR〇n/2+1之前導緣定置，並由 移位暫存器SROii之尾端緣重置，其結果是傳送第二控制 信號C 0 N T B。 雖未有圖説，開關控制電路22可組成包含一計數器， 其計算Η時脈之數目，於是傳送第一及第二控制信號 CONTA* C0NTBo 下文中再解釋圖說於第2圖中之驅動器1C之操作，並 要參考第4圖之圖說每一個信號及脈衝之波形之時序圖。 -1 1 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---1*-------Μ----------.訂 i:-------線 (請先閱讀背面之注意事項再填寫本頁) 558703 A7 B7 10 五、發明說明（） 雖然在第2圖中未圖說，但驅動器IC 20伴隨有與Η 時脈信號之同步之邏輯操作。 (請先閱讀背面之注意事項再填寫本頁) 如第4(c)圖所示，類比資料信號是連續成串輸入至驅 動器I C 2 0。 ~起動脈衝如第4(a)圖所圖說者是輸入至第一移位暫 存器SRi中。第一移位暫存器SRi在收到第一 h時脈信 號時捕捉此起動脈衝，並傳送第〜移位脈衝SROi作為 其之輸出。 當第二迄第η個移位暫存器SR2迄SRn分別接收第二 迄第η個Η時脈信號時，其連鑛地傳送移位脈衝sr〇2 迄S R 0 n ，就如第一移位脈衝被移位〜樣，移位脈衝s R 〇 n 是傳送自第η個移位暫存器SRn ，作為指向至次皴驅動 器1C之一起動脈衝。 在第一組移位脈衝S R 0 i迄S R 0 n/2由自第一組移位暫 存器S R i迄S R n/2傳送時，開關控制電路2 2傳送控制信 號C0NTA至主開關SWd，此主開關選出第一分段資料線 21a。另一方面，在第二組移位脈衝SRO n/2+1迄s R 0 η是 自第二組移位暫存器SR η/2+ι至SRn時，開關控制電路22 傳送控制信號C0NTB至主開關SWd，此主開關選出第二分 段資料線2 1 b。 經濟部智慧財產局員工消費合作社印製 如上文提及者，第一組開關SW：l迄SWn/2電氣連接第 一分段線21a至，或隔離第一分段線21a與，第一組取樣 及保持電路S/H !迄S/H n/2。第二組開關SW n/2+i迄SWn 電氣連接第二分段線21b至或隔離第二分段線21b與，第 二組取樣及保持電路S/Hn/24a迄S/Hn。 -1 2 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 558703 A7 B7 _ 11 五、發明說明（） 在移位脈衝皆是在Η位準時，接收那些移位脈衝之開 關皆是繼續保持。其結果，聯合之取樣及保持電路作取 樣及保持類比資料信號，藉以將一類比電壓充電至取樣 及保持電路中之保持電容器中。 當移位暫存器SRi迄SRn根據Η 時脈信號；連續傳送 移位脈衝8£01迄811()11時，類比資料信號被連續的取樣， 並輸流充電至聯合之保持電容器中。在全部保持電容器 已被充電達取樣及保持之資料後，全部資料是通過輸出 放大器23傳送，並寫入液晶顯示板中。 在本實施例中，取樣及保持電路^/^丄迄S/Hn是設計 以包括一對保持電容器。在保持電容器之一被充電時， 其他之保持電容器傳送一輸出。保持電容器被轉換以一 線一線的使用。 下文將參考第4圖解釋主開關SWd及開關控制電路22 之操作。 如早先提及之第一及第二類比開關24 a及24 b是由第一 及第二控制信號CONTA及CONTB控制。現假設第一及第二 類比開關24a及2 4 b是當第一及第二控制信號CON T A及 CONTB分別是在Η及L位準時被導通及關斷，第一控制 信號C0NTA維持在Η位準之時是第一組移位脈衝SROi迄 SR〇n/2是在傳送中。而第二控制信號C0NTB維持在H位 準之時是第二組移位脈衝SR0 ^/2+1迄SROn是正在傳送中。 第3B圖及第3C圖中所示之開關控制電路傳送第一及第 二控制信號C0HTA及C0NTB藉以致使第一及第二類比開關 -1 3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---r -線丨#! 經濟部智慧財產局員工消費合作社印製 A7 558703 ___B7_ 五、發明說明（12 ) 24a及24b操作在上文提及之方式中。 以下將參考第5圖來解釋包括上文提及之驅動器1C之 一類比型全彩色LCD之一實施例。 第5圖中圖說之類比型全彩色LCD之組成包含：一連 接器基板31，一液晶顯示板32，多値驅動器ICs，IC1迄 IC in成串安置横跨連接器基板31及液晶顯示板32，用於 驅動在液晶顯示板32之資料線，一信號處理器33接收同 步信號及類比影像信號，處理類比影像信號，傳送如此 處理之類比影像信號至每一個驅動器ICs IC1迄ICro，及 又傳送一起動脈衝30至第一驅動器IC 1C 1，及一撓性印 刷電路38連接信號處理器33至連接器基板31。 連接器基板31之上包括有佈線39，每一佈線是電氣連 接至每一驅動器IC，IC1迄ICm。經過處理之類比影像信 號是通過佈線39傳送至每一驅動器ICs，IC1迄ICm。 驅動器1C 一般輸出384點。因此8値驅動器1C配置成 串接於XGA型式之LCD中（在水平方向有1024X 3點），而 10個驅動器1C配置成串接於SXGA型式之LCD中（在水平方 向有1 2 4 0 X 3點）。 類比型全彩色LCD—般接收水平和垂直之同步信號及 類比影像信號。那些信號皆接收在信號處理器3 3中。 信號處理器33之組成包含：一控制器；一 PLL(柑鎖迴 路）電路35，接收水平和垂直同步信號及傳送時脈信號 至控制器34; —類比信號處理器電路36,接收及處理一 類比資料信號；及一緩衝放大器3 7，傳送資料信號至每 -1 4 - 本紙張尺度適用^國國家標準（CNS)A4規格（210 X 297公爱1 ---：-------------K----tri:-------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 558703558703 A7 B7 V. Description of the invention (Chengling Mingfa shows that the liquid crystal display on the board is in use and installed • 1111 types Suppose it is like a piece of element display crystal liquid color full-guard type. It is slower than the previous type, the first type, the letter type, and the ratio type. The reason is as it is. The asset and equipment ratios are similar, and some of them have been passed through and processed. This is printed by Xianzhong, Jinglu No. Liquid Telecommunications, Color Material, Color Division, No. of the Ministry of Economic Affairs, Smart Finance, Employee Consumption Cooperative. The amplifier and a wiring bus are transmitted to a driver integrated circuit of an LCD (liquid crystal display). The LCD driver integrated circuit is a data line horizontally arranged in the liquid crystal display panel and driving the liquid crystal display panel. The LCD driver integrated body The circuit receives analog data signals, samples and holds the received analog data signals, and appropriately transmits a voltage signal to the liquid crystal display panel. Figure 1 is a block diagram of a conventional analog LCD driver integrated circuit The composition of the analog LCD driver integrated circuit 10 includes: n-channel shift register 3} {1 to 31? 11;-data line 11, receives an analog data signal; switch 3 ¥ 1 to 3 ¥ 11 are electrically connected to each data line 11; the sample and hold circuit 3 / Η1 · 3 / Ηιι are electrically connected to Sh-SWn respectively; and an output amplifier 12 is electrically connected to the sample and hold circuit S / fUgS / Hn To drive a data line of a liquid crystal display panel. When the shift registers SR i to SRn receive a moving pulse, the first shift register 8 ^ to 31111 transmits a moving pulse as the shift pulse SROi So far SROn is synchronized with the clock signal to switch 3 »1 to 3» 11. --- i ------- * — -------- * Order—1 ------— ^ wi (Please read the precautions on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 558703 A7 __ B7_ V. Description of the invention (2) Switch SW: 1 to date SWn is controlled by the shift pulses SRO i to SROn transmitted by the shift registers SR i to SRn, respectively. That is, when the shift pulses SROi to SROn are received, the switch SWi-SWn is pseudo-based on the shift pulses. From SROi to 31 ~ 11, since the first switch SWi to the n-th switch SWn, it is continuously closed and turned off. For example, when the first switch SW i is continuously closed, the analog data is Sample and hold in a hold capacitor, and the hold circuit S / Hi is electrically connected to the first switch SWi. After all the sample and hold circuits S / Hi-S / Hri have completed the sample and hold analog data in their holding capacitors, the liquid crystal panel is simultaneously driven through the output amplifier 12. An analog full-color LCD includes a conventional analog LCD driver integrated circuit 10 'with the following difficulties. The data transfer rate has been increased due to the increase in LCD resolution from XG A to SXGA and UXGA. However, the conventional analog gold color LCD cannot increase its processing speed. The reason is as follows, because the data line 11 and the switch are electrically connected to the buffer amplifier installed on a signal processing substrate, including --------- h 丨 ------ l ----- ' Order --------- line (please read the phonetic on the back? Matters before filling out this page) The Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs prints the liquid holding capacity of the liquid crystal in Jingtuyeying. In the discussion category, 70 is mentioned as one electricity. The pressure is the charge. The power increase is not against the M level, and it is blocked by tt3 points. By the way, the M27 is like the shadow of the wire fruit M22. The M6-wrong guarantee guarantees the wrong value and success. ^ 1, the appearance of the product is U. The small high take-up device 11 public often shows a piece of large sf1 non-significant base amplifier In DS trial, due to the addition of one piece to the LC, the element is displayed in the original shape. The size of the paper is better than that of the Japanese-style electrical display. The paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm). 558703 Employee Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs prints A7 _ _ B7 ___ V. Description of the invention (3) When image signals are used, sampling and holding operations are performed, and a step voltage is generated on each line during each horizontal scanning period. The analog image signal is transmitted through a first signal line to the sampling and holding circuit that performs the n-th sampling and holding operation, while the analog image signal is transmitted through a second signal line to the sampling and holding circuit that performs the m-th sampling and holding operation. Hold circuit where n is an odd number and m is an even number. Japanese Unexamined Patent Publication No. 7-161631 proposes an active matrix liquid crystal display element in which the first and second red analog video signals have a phase separation of half a period from each other and are the first to occur, and the first red analog video The signal is sampled and held in the n-th sample and hold circuit through a first signal line, and the second red analog video signal is sampled and held in the m-th sample and hold circuit through a second signal line, where η is an odd number and m is an even number. Japanese Unexamined Patent Publication No. 10-143118 proposes an active matrix display element. In the proposed active matrix display element, each gate line is divided into two sections at its center, and a vertical scanning circuit is associated with each section of the gate line. Each signal line is divided into two segments. A pre-charger applies a pre-charge signal to sections of the signal line at different timings. A horizontal scanning circuit samples this signal line from the left of the signal line to the dividing point in the left segment, samples this signal line, from the right to the dividing point of the right segment of the signal line, and writes the image to such a sampling signal line. Japanese Unexamined Patent Publication No. 10-198321 has proposed an active matrix display element. It includes: · Gate lines are arranged in rows, signal lines are arranged in columns, pixels are arranged at the intersection of gate lines and signal lines, and the paper size of a horizontal scan is applicable to China National Standard (CNS) A4 (210 X 297) Mm) --- y ------- r ---------- ^ order ------- line (please read the precautions on the back before filling this page) 558703 Economy Printed by the Consumers ’Cooperative of the Ministry of Intellectual Property and Finance Bureau A7 _B7_ V. Description of the Invention (4) During the scanning, a vertical scanning circuit scans the gate lines and selects a row of pixels; during a horizontal scanning, a horizontal scanning circuit samples the signal lines The image signal is written into one line of the selected pixel. And a pre-charging circuit applies a pre-charging signal to each signal line before the image signal is written into the pixel. Each polar line is divided into left and right segments at the center of the screen. The vertical scanning circuit is combined with the divided gate lines and is divided into left and right segments. The left and right segments select the pixels in the left and right columns respectively during a horizontal scanning period. The pre-charger applies a pre-charge signal to the left segment of the signal line before the image is written to the pixels in the left half of the signal line; and before the image is written to the pixels in the right half of the signal line, Apply a pre-charge signal to the right section of the signal line. The problems mentioned above remain unsolved even in the display elements proposed in the above-mentioned announcement. SUMMARY OF THE INVENTION An object of the present invention is to provide a device for driving a data line in a liquid crystal display element, which device can increase the operation speed in an analog full-color LCD. Another object of the present invention is to provide a method for driving a data line in a liquid crystal display element, which method can have the same effect. In one aspect of the present invention, a device for driving a data line in a liquid crystal display panel is provided, which includes: (a) a data line in which an analog data signal is input, and (b) at least one shift temporary storage Device, sending a shift pulse, and (c) at least one circuit for sampling and holding an analog data signal based on the shift pulse, and transmitting a voltage signal, the data cable of which is covered by the paper and the Chinese standard (CNS) A4 specification (210 X 297 mm) --1 ------- L ---------- • Order ------- line (Please read the precautions on the back before filling (This page) 558703 Printed by A7 ____B7___, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (5) The data line with the first and second segments, the analog data signal is input to the first and second segment data Line one. A device is further provided for driving a data line in a liquid crystal display panel, which includes (a) a data line in which an analog data signal is input, and (b) at least one shift register to send a shift The pulse, and (c) shows a circuit for sampling and holding the analog data signal according to the shift pulse, and transmitting a voltage signal, the data line of which includes the first to the N ′ 値 th segment data line, the analog data The signal is one of the N-th segmented data lines input to this, where N is an integer equal to or greater than 3. In another aspect of the present invention, a liquid crystal display element is provided, including (a) a liquid crystal display panel and (b) a plurality of driver integrated circuits, which are arranged in series on the liquid crystal display panel for driving the liquid crystal display. The data line in the board, and (c) a signal processor, receives a synchronization signal and an analog image signal, processes the analog image signal, and transmits the analog image signal thus processed to each driver integrated circuit, and transmits another The starting pulse is sent to one of the driver integrated circuits. The starting pulse is transmitted from one of the driver integrated circuits to an adjacent driver integrated circuit. Each driver integrated circuit is composed of It includes the device mentioned above for driving a data line in a liquid crystal display panel. In yet another aspect of the present invention, a method for driving a data line in a liquid crystal display panel is provided, which includes the steps of: (8) inputting an analog data signal into the first to Nth segment data lines One selected, where N is an integer equal to or greater than 2, (b) According to a shift pulse, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm): ------ -«----------- • Order i · ------- line (please read the precautions on the back before filling this page) 558703 A7 B7__ 5. Description of the invention (6) Sampling and The analog data signal is maintained to transmit a voltage signal, and (0) according to this voltage signal, a data file is driven. The benefits obtained by the present invention mentioned above will be explained below. According to the present invention, one of the data in the device The line is a segmented data line divided into two or more. As a result, the wiring resistance value and capacitance of the data line are reduced. In addition, the number of switches electrically connected between the data line and the sampling and holding circuit is reduced. Ensure that the parasitic capacitance caused by the switch is also reduced. The active segmented data line is only a part of the data line, so it may reduce the load applied to the buffer amplifier and ensure an increase in the operating rate of the analog full-color LCD. In addition, for the same reason, the load energy applied to the buffer amplifier It is reduced to ensure the reduction of power consumption in the analog full-color LCD. In addition, the segmentation of the data line is more enhanced for charging and holding a capacitor. This capacitor is positioned farthest from the input terminal, and the analog data signal That is, the terminal is input into the data line. By inputting an analog data signal to the center of the device, it is possible to reduce the difference between the charging characteristics in the device, which can ensure the increase of the quality of an analog full-color LCD image- -: ------——-------- tT · — · ^ ------- line (please read the notes on the back before filling this page) Bureau of the Consumer Cooperative Co., Ltd. printed the same phase of the installation knowledge, such as the number of materials, materials, and similar data. According to the original installation of the display device, it should be said that the liquid II is used instead of the simple input device. Enclose The material of the line is clearly issued based on the use of information, including only the package, the use of the present is to add energy. The board can be placed immediately centimeter 97 2 X 10 2 ___ 'grid 4 NS ) A (C) Standard printing paper printed by a moderate size paper printed on the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 558703 A7 _ B7 V. Description of the invention (7) The first picture is a conventional analog LCD driver integrated circuit Block diagram. Figure 2 is a block diagram of a device for driving a data line in a liquid crystal display panel according to an embodiment of the present invention. Figure 3A is a block diagram of an example of a switch control circuit. Figure 3B is a block diagram of another example of a switch control circuit. Figure 3C is a block diagram of an example of another switch control circuit. Fig. 4 is a timing chart of the device illustrated in Fig. 2. Fig. 5 is a block diagram of an analog full-color liquid crystal display device including one of the illustrated devices of Fig. 2. Fig. 6 is a partial block diagram of a device for driving a data line in a liquid crystal display panel according to another embodiment of the present invention. Description of the Example of Relocation and Management Figure 2 is a device for driving a data line in a liquid crystal display panel according to a preferred embodiment of the present invention (hereinafter referred to as " driver 1C, ·). The composition of the driver IC2 0 in the figure includes: · a first set of shift registers SRi to SRn / 2, a second set of shift registers SR n / 2 + 1 to SR η, a first segment Data line 21a, a second segmented data line 21b, a first set of sample and hold circuits S / 1U to 3/11? 1/2, a second set of sample and hold circuits S / H n / 2 + 1g S / Hn, —The first group of switches SW! So far SW n / 2 is positioned between the first segmented data line 21 a and the first group of sample and hold circuits S / Hi to S / Hn / 2, a second group of switches SWn / 2 + l to SWn are positioned between the second segmented data line 21b and the second set of sample and hold circuits S / H n / 2 + 1 · S / Hn. A main switch SWd is used to select the first With the second segmented data line, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- 7 ------ J -----------: Order · 1 · ------- line (please read the precautions on the back before filling this page) 558703 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description () One of 2 la and 2 lb A switch control circuit 22 transmits a control signal CON T to the main switch SWd, thereby controlling the operation of the main switch SWd, and an output Amplifier 23 is electrically connected to a first set of sample and hold circuit S / Ηχ until S / Hn / 2 and a second set of sample and hold both switches S / Η 11/2 + 1 until S / Hn. Here, M η ”傺 refers to the number of channels in a driver 1C. An analog data signal is input to the driver IC 20 through a terminal 25 at the center of the longitudinal side of the driver IC 20, and is passed to the main switch SWd. Input to one of the first and second segmented data lines 21 a and 21 b. The switch control circuit 22 transmits a control signal CONT to the main switch SWd according to the first and second sets of shift registers SRI to SRn. The bit register SRI gSRn continuously transmits the shift pulse SROi according to the clock signal when the first shift register SRI receives a moving pulse HSP, so far SROiu outputs one of the output signals from the n-th shift register SRn It is used as a start pulse and transmitted to one of the drivers 1C in the secondary. The first group of switches SWi to SWn / 2 electrically connects the first segment line 21a to the first group of sample and hold circuits S / Hi-S / Hn / s, Or isolate the first segment line 21 & from the first group of sample and hold circuits 3/111 to 3/1111/2. The second group of switches SW n / 2 + 1 to SWn are electrically connected from the second segment line 21b to the first Two sets of sample and hold circuits S / H n / 2 + 1 to S / Hn, or isolate the second segment line 21b from the second set of sample and hold circuits S / Hn / 2 + l to S / Hn. The first and second sets of sample and hold circuits S / Hi to S / Η η are to transmit their output through the output amplifier 23 to the outside of the driver IC 20. Figure 3A is An example of the main switch SWd. The composition of the main switch SWd is: a terminal, through which analog data signals are input; a first analogue switch -1 0-This paper size applies to China National Standard (CNS) A4 (210 X 297) Mm) --------- J -----------; Order-丨 · ------- line (Please read the precautions on the back before filling this page) 558703 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Off 24a, electrically connected to the first segment data line 21a; and a second analog switch 24b, electrically connected to the second segment data line 21b. The first and second analog switches 24a and 24b are respectively controlled by the control signals CON TA and CON TB transmitted from the switch control circuit 22. Figure 3B is an example of the switch control circuit 22. The switch control circuit 22 It consists of a first OR (or) circuit 26a, which receives the shift pulses SR 0 i to SR n / 2 from the first set of shift registers SR i to SR n / 2. SR 〇n / 2, and transmits the first control signal C0NTA indicating the sum of the shift pulses SR0 丄 to SRO n / 2; and a second OR circuit 26b, which receives the second set of shift registers SRn / 2 + The shift pulses SR0n / 2 + 1 to SROn transmitted from 1 to SRn and the second control signal C 0 NTB indicating the sum of the shift pulses SR 0 n / 2 + 1 gSROii are transmitted. FIG. 3C is another example of the switch control circuit 22. The switch control circuit 22 is composed of a first SR flip-flop 27a, which is set by the leading edge before the first shift pulse SROi, and reset by the trailing edge of the shift pulse SROn / 2. The result is that the first A control signal CONTA; and a second SR flip-flop 27b, set by the leading edge of the shift register SROn / 2 + 1, and reset by the trailing edge of the shift register SROii, and the result Yes, the second control signal C 0 NTB is transmitted. Although not shown in the figure, the switch control circuit 22 may include a counter that counts the number of clocks, and then transmits the first and second control signals CONTA * C0NTBo. The operation of the driver 1C shown in the second figure is explained below. Please refer to the diagram in Figure 4 to describe the timing diagram of each signal and pulse waveform. -1 1-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --- 1 * ------- M ----------. Order i: ------- Line (Please read the precautions on the back before filling this page) 558703 A7 B7 10 V. Description of the invention () Although not shown in the second figure, the driver IC 20 is accompanied by the clock Logic operation of signal synchronization. (Please read the precautions on the back before filling in this page.) As shown in Figure 4 (c), the analog data signal is continuously input to the drive I C 2 0. The start pulse is input to the first shift register SRI as illustrated in Fig. 4 (a). The first shift register SRI captures this start pulse when it receives the first h clock signal, and transmits the ~~ th shift pulse SROi as its output. When the second to n-th shift register SR2 to SRn respectively receive the second to n-th ， clock signals, its continuous mine transfers the shift pulses sr〇2 to SR 0 n, as in the first shift. The bit pulse is shifted ~, the shift pulse s R 0n is transmitted from the n-th shift register SRn, and serves as one of the start pulses directed to the second driver 1C. When the first group of shift pulses SR 0 i to SR 0 n / 2 are transmitted from the first group of shift registers SR i to SR n / 2, the switch control circuit 22 transmits a control signal C0NTA to the main switch SWd, This main switch selects the first segmented data line 21a. On the other hand, when the second set of shift pulses SRO n / 2 + 1 to s R 0 η are from the second set of shift registers SR η / 2 + to SRn, the switch control circuit 22 transmits a control signal C0NTB To the main switch SWd, this main switch selects the second segmented data line 2 1 b. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as mentioned above. The first group of switches SW: 1 to SWn / 2 electrically connects the first segment line 21a to, or isolates the first segment line 21a from the first group. Sample and hold circuits S / H! So far S / H n / 2. The second group of switches SW n / 2 + i to SWn electrically connects the second segment line 21b to or isolates the second segment line 21b from the second group of sample and hold circuits S / Hn / 24a to S / Hn. -1 2-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 558703 A7 B7 _ 11 V. Description of the invention () When the shift pulses are all at the level, receive those shift pulses The switches are all kept on. As a result, the combined sample and hold circuit is used to sample and hold the analog data signal, thereby charging an analog voltage to the holding capacitor in the sample and hold circuit. When the shift registers SRi to SRn are continuously transmitted according to the Η clock signal; when the shift pulses are continuously transmitted from 8 £ 01 to 811 () 11, the analog data signal is continuously sampled and charged to the joint holding capacitor. After all the holding capacitors have been charged and sampled and held, all the data is transmitted through the output amplifier 23 and written into the liquid crystal display panel. In this embodiment, the sample and hold circuit S / Hn is designed so as to include a pair of hold capacitors. When one of the holding capacitors is charged, the other holding capacitor transmits an output. Holding capacitors are switched for one-by-one use. The operation of the main switch SWd and the switch control circuit 22 will be explained below with reference to FIG. 4. As mentioned earlier, the first and second analog switches 24a and 24b are controlled by the first and second control signals CONTA and CONTB. Now assume that the first and second analog switches 24a and 2 4 b are turned on and off when the first and second control signals CON TA and CONTB are at the Η and L levels, respectively, and the first control signal C0NTA is maintained at the Η position. On time is that the first set of shift pulses SROi to SROn / 2 is being transmitted. When the second control signal CONTB is maintained at the H level, the second set of shift pulses SR0 ^ / 2 + 1 and SROn are being transmitted. The switch control circuit shown in Figures 3B and 3C sends the first and second control signals C0HTA and C0NTB to make the first and second analog switches-1 3- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Order --- r-line 丨 #! Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 558703 ___B7_ V. Description of the invention (12) 24a and 24b operate in the manner mentioned above. An embodiment of an analog full-color LCD including the driver 1C mentioned above will be explained below with reference to FIG. The composition of the analog full-color LCD illustrated in FIG. 5 includes: a connector substrate 31, a liquid crystal display panel 32, multiple driver ICs, and IC1 to IC in a series arrangement across the connector substrate 31 and the liquid crystal display panel 32. For driving the data line on the liquid crystal display panel 32, a signal processor 33 receives the synchronization signal and the analog image signal, processes the analog image signal, and transmits the analog image signal thus processed to each driver ICs IC1 to ICro, and then transmits A start pulse 30 to the first driver IC 1C 1 and a flexible printed circuit 38 connect the signal processor 33 to the connector substrate 31. The connector substrate 31 includes wirings 39, and each wiring is electrically connected to each driver IC, IC1 to ICm. The processed analog image signals are transmitted to each driver ICs through IC 39, IC1 to ICm. Driver 1C generally outputs 384 points. Therefore, the 8 値 driver 1C is configured to be serially connected to the XGA type LCD (1024X 3 dots in the horizontal direction), and the 10 driver 1C is configured to be serially connected to the SXGA type LCD (1 2 4 0 X in the horizontal direction) 3 points). Analog full-color LCD-generally receives horizontal and vertical synchronization signals and analog video signals. Those signals are all received in the signal processor 33. The composition of the signal processor 33 includes: a controller; a PLL (Orange Locked Loop) circuit 35, which receives horizontal and vertical synchronization signals and sends clock signals to the controller 34;-an analog signal processor circuit 36, which receives and processes one Analog data signal; and a buffer amplifier 3 7, transmitting data signal to every -1 4-This paper size applies to the national standard (CNS) A4 specification (210 X 297 public love 1 ---: ------ ------- K ---- tri: ------- line (Please read the precautions on the back before filling out this page) Printed by the Employee Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 558703
經濟部智慧財產局員工消費合作社印製 五、發明說明（13) ~驅動器ICS，IC1迄ICm。 控制器34接收水平與垂直同步信號及自PLL電路35傳 送之時脈信號；並傳送控制信號至類比信號處理電路3 6 及緩衝放大器37，藉以控制它們。控制器34亦傳送起動 信號至第一驅動器IC1。 類比信號處理器電路3 6執行時間轉換，y轉換，及類 比影像信號之資料反轉。類比影像信號是在類比信號處 理電路36中處理，其後即通過緩衝放大器37及佈線39傳 送至每一個驅動器ICs, IC1迄ICm。Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (13) ~ Driver ICS, IC1 to ICm. The controller 34 receives the horizontal and vertical synchronization signals and the clock signals transmitted from the PLL circuit 35; and transmits control signals to the analog signal processing circuit 36 and the buffer amplifier 37 to control them. The controller 34 also sends a start signal to the first driver IC1. The analog signal processor circuit 36 performs time conversion, y conversion, and data inversion of the analog video signal. The analog video signal is processed in the analog signal processing circuit 36, and is then transmitted to each driver ICs, IC1 to ICm through the buffer amplifier 37 and the wiring 39.
控制器34産生起動脈衝30，並通過撓性印刷電路3 8傳 送此起動脈衝30至第一驅動器1C 1。在起動脈衝被收到 時，第一驅動器IC1則傳送一起動脈衝至第二驅動器IC2 。同樣方式，在起動脈衝自前一個驅動器1C ^^收到時， 驅動器ICn則傳送一起動脈衝至其次之驅動器1C 如早先提及者，在起動脈衝之收到時，移位暫存器傳 送在每一個驅動器1C中之移位脈衝。當第一組移位脈衝 3^1迄31?(^/2産生時，第一分段資料線21&造成活性； 而當第二組移位脈衝SRO η/2+1迄SROn産生時，第二分段 資料線21b造成活性。當包括那些分段資料線21a及21b 之驅動器1C傳送起動脈衝至其次之驅動器1C時，第一及 第二分段資料線21a及2 lb皆造成不活性。如此在第5 圖中圖示之類比型全彩色LCD中多個驅動器1C是配置成 串接之情況下，僅有一個驅動器1C中之第一及第二分段 資料線21a及21b之一個被造成活性。 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —：-------—----^----tris-------線 (請先閱讀背面之注意事項再填寫本頁) 558703 A7 B7 f v 14 五、發明說明（） 雖然資料線是分割成二個段部分，即是在上面提出之 實施例中之第一及第二分段資料線21 a及21b，但應注意 ，資料線被分割成之段部分數目並不限於兩個。資料線 可以分割成三個或更多之段部分。 第6圖中圖示一資料線被分割為三個段部分之實例， 卽是有第一迄第三個分段資料線42a，42b及42c。 一類比資料信號通過一位在驅動器1C 40之中央之端 子4 3輸入至驅動器1C 40中。此類比資料信號通過一根 據來自開關控制電路41傳送之控制信號CON T所控制之主 開關SWd，傳送至第一迄第三分段資料線42a，42b及42c 。此類比資料信號是輸入至第一，第二，或第三之分段 資料線42a，42b或42c在其中心處，確保提高持持電容 器之充電特性，及由是之影像品質。 開關控制電路41傳送控制信號C0NT至主開關SWd由此 根據來自移位暫存器之移位脈衝，選出第一迄第三分段 資料線42a迄42c之一線。當驅動器1C傳送一起動脈衝時 ，主開關SWd被造成斷開，即是主開關SWd不再電氣連接 端子43至驅動器1C中之第一迄第三分段資料線42a迄42c 中之任一線。 其他操作是與上文提出之實施例之操作相同。 參考符號説明 1〇.....LCD驅動器積體電路 11,42a,42b,42c.....資料線 12.....輸出放大器 -1 6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---·------------- (請先閱讀背面之注意事項再填寫本頁) 訂--- 經濟部智慧財產局員工消費合作社印製The controller 34 generates a start pulse 30 and transmits the start pulse 30 to the first driver 1C 1 through the flexible printed circuit 38. When the start pulse is received, the first driver IC1 sends a moving pulse to the second driver IC2. In the same way, when the start pulse is received from the previous driver 1C ^^, the driver ICn sends a moving pulse to the next driver 1C. As mentioned earlier, when the start pulse is received, the shift register is transmitted at every A shift pulse in a driver 1C. When the first group of shift pulses 3 ^ 1 to 31? (^ / 2 is generated, the first segmented data line 21 & causes activity; and when the second group of shift pulses SRO η / 2 + 1 to SROn is generated, The second segmented data line 21b is activated. When the driver 1C including those segmented data lines 21a and 21b transmits a start pulse to the next driver 1C, both the first and second segmented data lines 21a and 2 lb are rendered inactive. In this case, when multiple drivers 1C are configured in series in the analog full-color LCD illustrated in FIG. 5, only one of the first and second segmented data lines 21a and 21b in one driver 1C is configured. Caused to be active. -15- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) —: --------------- ^ ---- tris ---- --- Line (please read the precautions on the back before filling this page) 558703 A7 B7 fv 14 V. Description of the invention () Although the data line is divided into two sections, it is the first in the embodiment proposed above. The first and second segmented data lines 21 a and 21 b, but it should be noted that the number of segments into which the data line is divided is not limited to two. The data line can be divided into Three or more segments. Figure 6 shows an example where a data line is divided into three segment parts. There are first to third segmented data lines 42a, 42b, and 42c. An analog data The signal is input to the driver 1C 40 through a bit 4 3 in the center of the driver 1C 40. The analog data signal is transmitted to the first through a main switch SWd controlled by a control signal CON T transmitted from the switch control circuit 41. So far the third segmented data line 42a, 42b and 42c. The analog data signal is input to the first, second, or third segmented data line 42a, 42b, or 42c at its center to ensure that the holding capacitor is increased. Charging characteristics and image quality. The switch control circuit 41 transmits a control signal CONT to the main switch SWd, thereby selecting the first to third segment data lines 42a to 42c based on the shift pulse from the shift register. One line. When the driver 1C transmits a moving pulse, the main switch SWd is turned off, that is, the main switch SWd is no longer electrically connected to the terminal 43 to any of the first to third segmented data lines 42a to 42c in the driver 1C. First line. Other operations are The operation is the same as that of the embodiment proposed above. Reference symbol description 10. LCD driver integrated circuit 11, 42a, 42b, 42c ... Data line 12. Output amplifier-1 6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --- · ------------- (Please read the precautions on the back before filling this page ) Order --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
線---------——I 558703 A7 B7 五、發明說明（） 經濟部智慧財產局員工消費合作社印製 2 0,4 0 .....驅動琴1C 2 1a... ..第一分段資料線 2 1b... ..第二分段資料線 2 2,41. ——開關控制電路 25,43. ——端子 23 ·… .輸出放大器 24a… ..第一類比開關 24b… ..第^類比開關 2 6a... ..第一 0 R電路 26b… ..第一 0R電路 27a… ..第一 SR正反器 27b… •.第一 SR正反器 30 ·… .起動脈衝 31.... .連接器基板 32 .... .液晶顯示板 33.... .信號處理器 34 .... .控制器 35 .... .P L L電路 36 .... .類比信號處理電路 37.... .緩衝放大器 38 .... .撓性印刷電路 39 .... .佈線 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Φ 訂 i ;--- -----線 ---------.---------------Line ---------—— I 558703 A7 B7 V. Description of the invention () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 0, 4 0 ..... Drive 1C 2 1a ... .. first segmented data line 2 1b ... .. second segmented data line 2 2,41. ——Switch control circuit 25,43. ——Terminal 23 · ... .output amplifier 24a ..... first Analog switch 24b ... .. ^ analog switch 2 6a ... .. first 0 R circuit 26b ... .. first 0R circuit 27a ... .. first SR flip-flop 27b ... •. First SR flip-flop 30 · ... .Starting pulse 31 .... .Connector substrate 32 ..... LCD display board 33 ..... Signal processor 34 .... Controller 35 ..... PLL circuit 36 ..... analog signal processing circuit 37 ... Buffer amplifier 38 ... .. flexible printed circuit 39 ... .. wiring -17- This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) (Please read the notes on the back before filling this page) Φ Order i; --- ----- line ---------.-------- -------