CN109003587A - GOA circuit and HG2D dot structure with the GOA circuit - Google Patents
GOA circuit and HG2D dot structure with the GOA circuit Download PDFInfo
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- CN109003587A CN109003587A CN201810878457.0A CN201810878457A CN109003587A CN 109003587 A CN109003587 A CN 109003587A CN 201810878457 A CN201810878457 A CN 201810878457A CN 109003587 A CN109003587 A CN 109003587A
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- 239000010409 thin film Substances 0.000 claims description 172
- 239000003990 capacitor Substances 0.000 claims description 12
- 101100134058 Caenorhabditis elegans nth-1 gene Proteins 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of HG2D dot structures with the GOA circuit, the GOA circuit includes the GOA driving unit of bus unit and multiple grades, odd number CK clock cable is arranged in the bus unit, each GOA driving unit connects a CK clock cable；The CK signal dutyfactor of each CK clock cable is set as Duty (100/N)/(100/N).The present invention can be effectively reduced the item number of CK clock cable, it is being applied in HG2D dot structure, use the CK clock cable of odd number item number, the number of some intermediate CK clock cables, such as 6CK, 10CK can be used, the number of CK clock cable is doubled with 2 multiple, space can be preferably utilized, wiring can be reasonably arranged, save wiring space.
Description
Technical Field
The invention relates to the technical field of liquid crystal display and the like, in particular to a GOA circuit and an HG2D pixel structure with the GOA circuit.
Background
With the improvement of the performance of the TFT, the GOA technology is currently and widely applied to the panel, and has many advantages, so that Gate ICs can be saved, the yield of customers can be improved, and a frameless design can be realized.
The GOA Circuit includes two parts, which generally include a GOA driving unit (Circuit) and a bus unit (busline), wherein the bus unit (busline) includes a CK signal line, an XCK signal line, an STV signal line, a VSS signal line, an LC control signal line, and the like. In general, the GOA circuit always transmits both the CK signal and the XCK signal, one as a continuous signal and one as a pull-down signal. In the advanced multiple CK signal GOA circuit, the configuration of 2CK, 4CK, 6CK, 8CK,10CK,12 CK, etc. occurring in pairs is also adopted, as shown in fig. 1 and fig. 2, fig. 1 shows the GOA circuit arrangement of 2CK signals, and fig. 2 shows the GOA circuit arrangement of 4CK signals. The multi-CK GOA circuit has many advantages, such as reducing single CK RC loading, increasing charging time, etc., but also has some disadvantages, such as the more the number of CK signal lines, the wider the total width of the CK signal lines, the larger the required circuit wiring (Layout) space, the increased system complexity, etc.
Disclosure of Invention
The purpose of the invention is: a GOA circuit is provided to solve the problems that the total width of a CK signal line is wide, the space of required circuit wiring (Layout) is large, and the circuit wiring is complex in the prior art.
The technical scheme for realizing the purpose is as follows: a GOA circuit comprises a bus unit and a plurality of cascaded GOA driving units, wherein odd CK clock signal lines are arranged in the bus unit, and each GOA driving unit is connected with one CK clock signal line; the CK signal Duty ratio of each of the CK clock signal lines is set to Duty (100/N)/(100/N).
In a preferred embodiment of the present invention, the odd number is an integer greater than 2.
In a preferred embodiment of the present invention, the GOA unit includes a pull-up control module, a pull-up module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor; the pull-up control module is respectively connected with the pull-down module and the pull-down maintaining module; the pull-up module is respectively connected with the CK clock signal line and the scanning line of the current stage; the down-pulling module is connected with the CK clock signal line and the down-pulling module respectively; the pull-down maintaining module and the pull-down module are respectively connected with a pull-down signal line; the pull-down module is respectively connected with the scanning line of the current stage; one end of the bootstrap capacitor is connected with the pull-up control module and the download module respectively, and the other end of the bootstrap capacitor is connected with the scanning line of the stage.
In a preferred embodiment of the present invention, the pull-up control module includes a first thin film transistor T11, a gate of the first thin film transistor T11 is configured to receive a trigger signal of a GOA cell of the nth-1 stage, and a drain of the first thin film transistor T11 is respectively connected to the pull-down module and the pull-down sustain module.
In a preferred embodiment of the present invention, the down module includes a second thin film transistor T22, the gate of the second thin film transistor T22 is connected to the drain of the first thin film transistor T11, the source of the second thin film transistor T22 is connected to the CK clock signal line, and the drain of the second thin film transistor T22 is used for outputting the trigger signal of the GOA unit of the current stage.
In a preferred embodiment of the present invention, the pull-up module includes a third tft T21, a gate of the third tft T21 is connected to a drain of the first tft T11, a source of the third tft T21 is connected to the CK clock signal line, and a drain of the third tft T21 is connected to the scan line of the present stage.
In a preferred embodiment of the present invention, the pull-down module includes a fourth thin film transistor T41 and a fifth thin film transistor T31, a gate of the fourth thin film transistor T41 is connected to the N +1 th scan line, a source of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to the pull-down signal line; the gate of the fifth thin film transistor T31 is connected to the (N + 1) th scan line, the source of the fifth thin film transistor T31 is connected to the scan line of the current stage, and the drain of the fifth thin film transistor T31 is connected to the pull-down signal line.
In a preferred embodiment of the present invention, the pull-down maintaining module includes a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, and a ninth thin film transistor T32; the gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, the source thereof is connected to the drain of the seventh thin film transistor T51, and the gate thereof is connected to a pull-down signal line; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving a control signal; a gate electrode of the eighth thin film transistor T42 is connected to a source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to a drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line.
In a preferred embodiment of the present invention, the GOA circuit further includes a plurality of stages of pre-charge units correspondingly connected to each stage of the GOA driving units; the gate of the first thin film transistor T11 is used for receiving a trigger signal of the GOA unit of the nth-2 level; a gate of the fourth thin film transistor T41 is connected to the N +2 th scan line, a source of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to a pull-down signal line; the gate of the fifth thin film transistor T31 is connected to the (N + 2) th stage scan line.
The invention also provides an HG2D pixel structure, which comprises a GOA circuit.
The invention has the advantages that: the GOA circuit can effectively reduce the number of CK clock signal lines, for example, when the number of the required CK clock signal lines is more than 2 but not more than 4, 3 CK clock signal lines can be used to reduce the number of the CK clock signal lines, and when the GOA circuit is applied to an HG2D pixel structure, the number of intermediate CK clock signal lines can be used by using odd number of CK clock signal lines, for example, the number of 6CK clock signal lines, 10CK clock signal lines and the number of CK clock signal lines are multiplied by 2, so that the space can be better utilized, the circuit wiring can be reasonably arranged, and the circuit wiring space is saved.
Drawings
The invention is further explained below with reference to the figures and examples.
FIG. 1 shows a GOA circuit arrangement for 2CK signals in the prior art;
FIG. 2 shows a GOA circuit arrangement for 4CK signals in the prior art;
FIG. 3 is a schematic diagram of a GOA driving unit of embodiment 1;
FIG. 4 is a waveform diagram of CK clock signals of embodiment 1;
FIG. 5 is a schematic diagram of a GOA driving unit of embodiment 2;
FIG. 6 is a diagram of a portion of a GOA circuit structure of the HG2D pixel structure;
wherein,
1 GOA driving unit; 2, a bus unit;
100 a pull-up control module; 200, a pull-up module;
300 a download module; 400 pull down maintenance module;
500 pull down the module; 600 bootstrap capacitance;
700 pull down the signal line; 800CK clock signal lines;
900 scan lines of this stage.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc., refer to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
Example 1: referring to fig. 1 and 2, a GOA circuit includes a bus unit 2 and a plurality of cascaded GOA driving units 1, wherein odd CK clock signal lines 800 and STV signal lines are arranged in the bus unit 2, and each GOA driving unit 1 is connected to a CK clock signal line 800. The CK signal Duty ratio of each of the CK clock signal lines 800 is set to Duty (100/N)/(100/N). The odd number is an integer greater than 2, and the present embodiment takes 3 CK clock signal lines 800 as an example to further explain the present invention. When 3 CK clock signal lines 800 are arranged in the bus bar unit 2, the CK signal Duty ratio of each CK clock signal line 800 is set to Duty 33/33. CK clock signal lines 800 are labeled CK1, CK2, CK3, respectively. The clock signal of its output is shown in fig. 3. The odd CK clock signal lines 800 may be applied to the Layout of the Layout space between odd and even numbers, for example, when the CK clock signal lines 800 are arranged, more than 2 and less than 4 are needed, and when 3 lines can be actually arranged, 3 CK clock signal lines 800 are used. Compared with 2CK clock signal lines, the RC loading of a single CK can be reduced, and the charging time can be reduced.
As shown in fig. 4, the GOA unit includes a pull-up control module 100, a pull-up module 200, a pull-down module 300, a pull-down sustain module 400, a pull-down module, and a bootstrap capacitor 600; the pull-up control module 100 is respectively connected with the pull-down module 300 and the pull-down maintaining module 400; the pull-up module 200 is connected to the CK clock signal line 800 and the scan line 900 of the current stage, respectively; the pull-down module 300 is connected to the CK clock signal line 800 and the pull-down module 500, respectively; the pull-down maintaining module 400 and the pull-down module 500 are respectively connected to the pull-down signal line 700; the pull-down modules 500 are respectively connected with the scan lines 900 of the current stage; one end of the bootstrap capacitor 600 is connected to the pull-up control module 100 and the pull-down module 300, respectively, and the other end is connected to the scan line 900 of the current stage.
The pull-up control module 100 includes a first thin film transistor T11, a gate of the first thin film transistor T11 is configured to receive a trigger signal of a GOA cell of the nth-1 stage, and a drain of the first thin film transistor T11 is connected to the pull-down module 300 and the pull-down sustain module 400, respectively.
The down-link module 300 includes a second thin film transistor T22, a gate of the second thin film transistor T22 is connected to a drain of the first thin film transistor T11, a source of the second thin film transistor T22 is connected to the CK clock signal line 800, and a drain of the second thin film transistor T22 is used for outputting a trigger signal of the GOA unit of the current stage.
The pull-up module 200 includes a third thin film transistor T21, a gate of the third thin film transistor T21 is connected to a drain of the first thin film transistor T11, a source of the third thin film transistor T21 is connected to the CK clock signal line 800, and a drain of the third thin film transistor T21 is connected to the scan line 900 of the present stage.
The pull-down module 500 includes a fourth thin film transistor T41 and a fifth thin film transistor T31, a gate of the fourth thin film transistor T41 is connected to the N +1 th scan line, a source of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to the pull-down signal line 700; the gate of the fifth thin film transistor T31 is connected to the (N + 1) th scan line, the source of the fifth thin film transistor T31 is connected to the scan line 900 of the current stage, and the drain of the fifth thin film transistor T31 is connected to the pull-down signal line 700. The pull-down sustain module 400 includes a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, and a ninth thin film transistor T32; the gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, the source thereof is connected to the drain of the seventh thin film transistor T51, and the gate thereof is connected to the pull-down signal line 700; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving a control signal; a gate electrode of the eighth thin film transistor T42 is connected to the source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to the drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line 700; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line 900 of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line 700. One end of the bootstrap capacitor 600 is a first node Q (N), and is connected to the drain of the first thin film transistor T11 through the first node Q (N). The source of the fourth thin film transistor T41 and the gate of the second thin film transistor T22 are connected to the drain of the first thin film transistor T11 through a first node Q (N). The gate electrode of the eighth thin film transistor T42, the source electrode of the sixth thin film transistor T52, and the drain electrode of the seventh thin film transistor T51 are connected through a second node P (N).
Embodiment 2, as shown in fig. 5, in this embodiment, the GOA circuit further includes a multi-stage pre-charging unit correspondingly connected to each stage of the GOA driving unit 1. The connection structure of the precharge unit and the GOA driving unit 1 is the technical knowledge grasped by those skilled in the art, and is not described in detail herein.
In this embodiment, the GOA unit includes a pull-up control module 100, a pull-up module 200, a pull-down module 300, a pull-down maintaining module 400, a pull-down module 500, and a bootstrap capacitor 600; the pull-up control module 100 is respectively connected with the pull-down module 300 and the pull-down maintaining module 400; the pull-up module 200 is connected to the CK clock signal line 800 and the scan line 900 of the current stage, respectively; the pull-down module 300 is connected to the CK clock signal line 800 and the pull-down module 500, respectively; the pull-down maintaining module 400 and the pull-down module 500 are respectively connected to the pull-down signal line 700; the pull-down modules 500 are respectively connected with the scan lines 900 of the current stage; one end of the bootstrap capacitor 600 is connected to the pull-up control module 100 and the pull-down module 300, respectively, and the other end is connected to the scan line 900 of the current stage.
The pull-up control module 100 includes a first thin film transistor T11, a gate of the first thin film transistor T11 is configured to receive a trigger signal of a GOA cell of the nth-2 stage, and a drain of the first thin film transistor T11 is connected to the pull-down module 300 and the pull-down sustain module 400, respectively.
The down-link module 300 includes a second thin film transistor T22, a gate of the second thin film transistor T22 is connected to a drain of the first thin film transistor T11, a source of the second thin film transistor T22 is connected to the CK clock signal line 800, and a drain of the second thin film transistor T22 is used for outputting a trigger signal of the GOA unit of the current stage.
The pull-up module 200 includes a third thin film transistor T21, a gate of the third thin film transistor T21 is connected to a drain of the first thin film transistor T11, a source of the third thin film transistor T21 is connected to the CK clock signal line 800, and a drain of the third thin film transistor T21 is connected to the scan line 900 of the present stage.
The pull-down module 500 includes a fourth thin film transistor T41 and a fifth thin film transistor T31, a gate of the fourth thin film transistor T41 is connected to the N +2 th scan line, a source of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to the pull-down signal line 700; the gate of the fifth thin film transistor T31 is connected to the (N + 2) th scan line, the source of the fifth thin film transistor T31 is connected to the scan line 900 of the current stage, and the drain of the fifth thin film transistor T31 is connected to the pull-down signal line 700. The pull-down sustain module 400 includes a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, and a ninth thin film transistor T32; the gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, the source thereof is connected to the drain of the seventh thin film transistor T51, and the gate thereof is connected to the pull-down signal line 700; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving a control signal; a gate electrode of the eighth thin film transistor T42 is connected to the source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to the drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line 700; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line 900 of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line 700. One end of the bootstrap capacitor 600 is a first node Q (N), and is connected to the drain of the first thin film transistor T11 through the first node Q (N). The source of the fourth thin film transistor T41 and the gate of the second thin film transistor T22 are connected to the drain of the first thin film transistor T11 through a first node Q (N). The gate electrode of the eighth thin film transistor T42, the source electrode of the sixth thin film transistor T52, and the drain electrode of the seventh thin film transistor T51 are connected through a second node P (N).
As shown in fig. 6, fig. 6 is a partial GOA circuit structure diagram of HG2D pixel structure, where in the GOA circuit structure of HG2D pixel structure: since two gates are turned on simultaneously, the CK clock lines must be paired to provide the same clock signal for both gates simultaneously, and if the conventional design in the prior art is adopted, the number of CK clock lines required becomes 4CK,8CK,12CK, etc., sequentially increasing by multiples of 4. When the number of the required CK clock signal lines is more than 2 and not more than 4, etc., odd number of CK signal lines of the present invention can be used, and the number of the CK clock signal lines can be set to 6CK,10CK, etc., and thus, the space can be better utilized.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A GOA circuit is characterized by comprising a bus unit and a plurality of cascaded GOA driving units, wherein odd CK clock signal lines are arranged in the bus unit, and each GOA driving unit is connected with one CK clock signal line; the CK signal Duty ratio of each of the CK clock signal lines is set to Duty (100/N)/(100/N).
2. The GOA circuit of claim 1, wherein the odd number is an integer greater than 2.
3. The GOA circuit according to claim 2, wherein the GOA unit comprises a pull-up control module, a pull-up module, a pull-down maintaining module, a pull-down module and a bootstrap capacitor;
the pull-up control module is respectively connected with the pull-down module and the pull-down maintaining module;
the pull-up module is respectively connected with the CK clock signal line and the scanning line of the current stage;
the down-pulling module is connected with the CK clock signal line and the down-pulling module respectively;
the pull-down maintaining module and the pull-down module are respectively connected with a pull-down signal line;
the pull-down module is respectively connected with the scanning line of the current stage;
one end of the bootstrap capacitor is connected with the pull-up control module and the download module respectively, and the other end of the bootstrap capacitor is connected with the scanning line of the stage.
4. The GOA circuit of claim 3, wherein the pull-up control module comprises a first thin film transistor T11, when the CK clock signal lines have a number of 3, a gate of the first thin film transistor T11 is configured to receive a trigger signal of a GOA unit of the Nth-1 stage, and a drain of the first thin film transistor T11 is respectively connected to the pull-down module and the pull-down maintaining module.
5. The GOA circuit of claim 4, wherein the downstream module comprises a second thin film transistor T22, a gate of the second thin film transistor T22 is connected to a drain of the first thin film transistor T11, a source of the second thin film transistor T22 is connected to the CK clock signal line, and a drain of the second thin film transistor T22 is used for outputting a trigger signal of the GOA unit of the current stage.
6. The GOA circuit of claim 5, wherein the pull-up module comprises a third TFT T21, the gate of the third TFT T21 is connected to the drain of the first TFT T11, the source of the third TFT T21 is connected to the CK clock signal line, and the drain of the third TFT T21 is connected to the scan line of the current stage.
7. The GOA circuit according to claim 6, wherein the pull-down module comprises a fourth thin film transistor T41 and a fifth thin film transistor T31, wherein a gate of the fourth thin film transistor T41 is connected to the N +1 th scan line, a source of the fourth thin film transistor T41 is connected to a gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to a pull-down signal line; the gate of the fifth thin film transistor T31 is connected to the (N + 1) th scan line, the source of the fifth thin film transistor T31 is connected to the scan line of the current stage, and the drain of the fifth thin film transistor T31 is connected to the pull-down signal line.
8. The GOA circuit of claim 7, wherein the pull-down maintaining module comprises a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, a ninth thin film transistor T32; the gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, the source thereof is connected to the drain of the seventh thin film transistor T51, and the gate thereof is connected to a pull-down signal line; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving a control signal; a gate electrode of the eighth thin film transistor T42 is connected to a source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to a drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line.
9. The GOA circuit according to claim 4, further comprising a multi-stage pre-charging unit correspondingly connected to each stage of the GOA driving unit; the gate of the first thin film transistor T11 is used for receiving a trigger signal of the GOA unit of the nth-2 level; a gate of the fourth thin film transistor T41 is connected to the N +2 th scan line, a source of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to a pull-down signal line; the gate of the fifth thin film transistor T31 is connected to the (N + 2) th stage scan line.
10. A HG2D pixel structure, comprising a GOA circuit of claim 1 or 2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810878457.0A CN109003587A (en) | 2018-08-03 | 2018-08-03 | GOA circuit and HG2D dot structure with the GOA circuit |
| PCT/CN2018/110009 WO2020024429A1 (en) | 2018-08-03 | 2018-10-12 | Goa circuit and hg-2d pixel structure having same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810878457.0A CN109003587A (en) | 2018-08-03 | 2018-08-03 | GOA circuit and HG2D dot structure with the GOA circuit |
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| CN109003587A true CN109003587A (en) | 2018-12-14 |
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| CN201810878457.0A Pending CN109003587A (en) | 2018-08-03 | 2018-08-03 | GOA circuit and HG2D dot structure with the GOA circuit |
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| CN (1) | CN109003587A (en) |
| WO (1) | WO2020024429A1 (en) |
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| CN110910846A (en) * | 2019-11-21 | 2020-03-24 | Tcl华星光电技术有限公司 | Display driving method and liquid crystal display device |
| CN111162114A (en) * | 2020-03-05 | 2020-05-15 | 深圳市华星光电半导体显示技术有限公司 | Display array substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110910846A (en) * | 2019-11-21 | 2020-03-24 | Tcl华星光电技术有限公司 | Display driving method and liquid crystal display device |
| CN111162114A (en) * | 2020-03-05 | 2020-05-15 | 深圳市华星光电半导体显示技术有限公司 | Display array substrate, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020024429A1 (en) | 2020-02-06 |
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