KR20000071401A - Liquid crystal display device and appratus for driving data line of liquid crystal display panel and method of doing the same - Google Patents

Abstract

(a) a data line to which analog data is input, (b) one or more shift registers SR ₁ to SR _n for transmitting shift pulses SRO ₁ to SRO _n , and (c) the shift pulses SRO ₁ to At least one circuit (S / H ₁ to S / H _n ) for sampling and maintaining the analog data signal according to SRO _n ) and transmitting a voltage signal, wherein the data line is first to Nth divided data. Lines 21a, 21b; 42a, 42b, 42c, wherein the analog data signal is input to one of the first to Nth data lines 21a, 21b; 42a, 42b, 42c, and N is 2 The apparatus 20 and 40 which drive a data line in a liquid crystal display panel which are the above integers are provided. According to this apparatus, data lines in the liquid crystal display panel are provided with first and second divided data lines. Therefore, it is possible to reduce the wiring resistance and the capacity of the data line as a whole.

Description

A liquid crystal display and a data line driving device of a liquid crystal display panel and a method thereof

The present invention relates to an apparatus and a method for driving a data line of a liquid crystal display panel.

In general, analog type full color liquid crystal displays are designed to receive analog data signals and process the analog data signals. In such an analog type full color liquid crystal display, the analog data signal is processed in the analog-signal processing circuit and input to the LCD driver integrated circuit through a wiring bus formed on the connection substrate via a buffer amplifier. The LCD driver IC is arranged perpendicular to the liquid crystal display panel and drives the data line of the liquid crystal display panel. The LCD driver IC receives an analog data signal, samples and holds the received analog data signal, and transmits a voltage signal to the liquid crystal display device.

1 is a block diagram of a conventional analog-type LCD driver IC.

The analog-type LCD driver IC 10 shown is a switch electrically connected to _n -channel shift registers SR ₁ to SR _n , a data line 11 receiving an analog data signal, and a data line 11, respectively. (SW ₁ to SW _n ), sampling and holding circuits (S / H ₁ to S / H _n ) electrically connected to SW ₁ to SW _n , respectively, and a sampling and holding circuit for driving data lines of the liquid crystal display panel. And an output amplifier 12 electrically connected to (S / H ₁ to S / H _n ).

When the shift registers SR ₁ to SR _n receive the start pulses, the first shift registers SR ₁ to SR _n are the shift pulses SRO ₁ to SRO _n , which switch switches SW to synchronize the start pulses with the clock signal. ₁ to SW _n ).

It is controlled in its operation by the shift pulses SRO ₁ to SRO _n respectively transmitted from the switches SW ₁ to SW _n shift registers SR ₁ to SR _n . That is, upon receiving a shift pulse (SRO ₁ to SRO _n), switch (SW ₁ to SW _n) comprises a first switch (SW ₁₎ to the shift pulse (SRO ₁ to SRO _n) from the N-th switches (SW _n) It can be turned on or off continuously.

For example, while the first switch SW ₁ is in the on state, it is sampled and held in the holding capacitor in the first sampling and holding circuit S / H ₁ electrically connected to the first switch SW ₁ . do. After all the sampling and holding circuits S / H ₁ to S / H _n have finished sampling and holding the analog data at their holding capacitors, the liquid crystal panel is driven simultaneously through the output amplifier 12.

The analog-type full color LCD including the conventional analog-type LCD driver IC involves the following problems.

As the resolution of the LCD is increased from XGA to SXGA and UXGA, the data transfer rate is increased. However, conventional analog-type full color LCDs cannot improve its processing rate.

The reason for this is as follows. Since the data line 11 and the switches SW ₁ to SW _n are electrically connected to the buffer amplifier mounted on the signal processing substrate, a fairly large load including the impedance of the wiring formed on the connection substrate is applied across the buffer amplifier. . As a result, the characteristic of charging the holding capacitor in the analog-type LCD driver IC 10 deteriorates.

It is an object of the present invention to provide a device capable of improving the rate at which an analog-type full color LCD operates, driving a data line in a liquid crystal display.

Another object of the present invention is to provide a method and a method of driving a data line in a liquid crystal display.

In one embodiment of the present invention, the analog data signal is sampled and held in accordance with (a) a data line to which an analog data signal is input, (b) one or more shift registers for transmitting a shift pulse, and (c) a shift pulse. At least one circuit for transmitting a voltage signal, the data line having a first to Nth divided data line, wherein an analog data signal is input to one of the first to Nth divided data lines, where N is 2 An apparatus for driving a data line in a liquid crystal display panel characterized by the above integer is provided.

In another embodiment of the present invention, an analog data signal is input to a selected one of the first to Nth divided data lines where N is an integer of 2 or more, (b) sampling and maintaining the analog data signal according to a shift pulse. A method of driving a data line in a liquid crystal display panel comprising transmitting a voltage signal, and (c) driving the data line in accordance with the voltage signal.

1 is a block diagram of a conventional analog-type LCD driver IC.

2 is a block diagram of an apparatus for driving data lines in a liquid crystal display panel according to an exemplary embodiment of the present invention.

3A is a block diagram of an embodiment of a switch control circuit, FIG. 3B is a block diagram of an embodiment of a switch control circuit, and FIG. 3C is a block diagram of another embodiment of a switch control circuit.

4 is a timing diagram of the apparatus shown in FIG. 2;

5 is a block diagram of an analog-type full color liquid crystal display device including the device shown in FIG.

6 is a partial block diagram of an apparatus for driving data lines in a liquid crystal display panel according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

20 drive IC

21a and 21b first and second split data lines

22 switch control circuit

23 output amplifier

25 terminals

SW ₁ to SW _n switch

SR ₁ to SR _n shift register

SRO ₁ to SRO _n Shift Pulse

FIG. 2 is a block diagram of an apparatus for driving data lines in a liquid crystal display panel (analog LCD driver IC, hereinafter referred to as "driver IC") according to a preferred embodiment of the present invention.

The illustrated driving device IC 20 includes a first group SR ₁ to SR _{n / 2} of a shift register, a second group SR _{n / 2 + 1} to SR _n of a shift register, and a first divided data line 21a. ), The second divided data line 21b, the first group of sampling and holding circuits S / H ₁ to S / H _{n / 2} , and the second group of sampling and holding circuits S / H _{n / 2 + 1} To S / H _n , a first group of switches SW ₁ to 1 located between the first divided data line 21a and the first group of sampling and holding circuits S / H ₁ to S / H _{n / 2} . SW _{n / 2),} the second split data lines (second group of switches located between 21b), a second group of the sample and hold circuit _{(S / H n / 2 +} 1 to S / H _n) (SW _{n / 2 + 1} to SW _n ), a main switch SWd for selecting one of the first and second divided data lines 21a and 21b, and a control signal CONT sent to the main switch SWd to send the main switch. A switch control circuit 22 for controlling the operation of (SWd), and a first of a sampling and holding circuit Groups (S / H ₁ to S _/ H _n / _2), the sample and hold circuit of the second group _{(S / H n / 2 +} 1 to S / H _n), the output amplifier 23 is electrically connected to both of the It is provided with. Here, "n" indicates the number of channels in one driver IC.

The analog data signal is input to the driving device IC 20 through the terminal 25 located in the longitudinal center of the driving device IC 20, and the first and second divided data lines (through the main switch SWd) 21a and 21b).

The switch control circuit 22 transmits a control signal CONT to the main switch SWd in accordance with the first and second groups SR ₁ to SR _n of the shift register.

When the first shift register SR1 receives the start pulse HSP, the shift registers SR ₁ to SR _n continuously transmit the shift pulses SRO ₁ to SRO _n in accordance with a clock signal.

The first group of switches SW ₁ to SW _{n / 2} electrically connects or samples the first split line 21a to the first group of sampling and holding circuits (S / H ₁ to S / H _{n / 2} ). And the first dividing line 21a from (S / H ₁ to S / H _{n / 2} ) to the first group of the holding circuit. The second group SW _{n / 2 + 1} to SW _n of the switch has a second dividing line 21b at (S / H _{n / 2 + 1} to S / H _n ) to the second group of sampling and holding circuits. The second dividing line 21b is electrically connected or separated from the second group S / H _{n / 2 + 1} to S / H _n of the sampling and holding circuit. The first and second groups S / H ₁ to S / H _n of the sampling and holding circuit transmit their outputs from the drive device IC 20 via the output amplifier 23.

3A shows an embodiment of the main switch SWd. The main switch SWd is a terminal to which an analog data signal is input, a first analog switch 24a electrically connected to the first split data line 21a, and a second electrically connected to the second split data line 21b. It is provided with an analog switch 24b. The first and second analog switches 24a and 24b are controlled by control signals CONTA and CONTB transmitted from the switch control circuit 22, respectively.

3B shows an embodiment of the switch control circuit 22. The switch control circuit 22 receives the shift pulses SRO ₁ to SRO _{n / 2} transmitted from the first group SR ₁ to SR _{n / 2} of the shift register and shifts the shift pulses SRO ₁ to SRO _{n / 2} . Shift pulse SRO _{n / 2} transmitted from the first OR circuit 26a for transmitting the first control signal CONTA indicating the sum of and the second group SR _{n / 2 + 1} to SR _n of the shift register. _And a second OR circuit 26b which receives ₊₁ to SRO _n and transmits a second control signal CONTB indicating the sum of the shift pulses SRO _{n / 2 + 1} to SRO _n .

3C shows another embodiment of the switch control circuit 22. The switch control circuit 22 is set on the rising edge of the first shift pulse SRO ₁ and reset on the falling edge of the shift pulse SRO _{n / 2} , and as a result, transmits the first control signal CONTA. 1 SR flip-flop 27a and set on the rising edge of shift pulse SRO _{n / 2 + 1} and reset on the falling edge of shift pulse SRO _n , resulting in the transmission of the second control signal CONTB Is provided with a second SR flip-flop 27b.

Although not shown, the switch control circuit 22 may be provided as a counter for counting the number of H clocks and transmitting the first and second control signals CONTA and CONTB.

In the following, the operation of the driving device IC 20 is described in FIG. 2 with reference to FIG. 4, which is a timing diagram showing waveforms of signals and pulses respectively.

Although not shown in Fig. 2, the driving device IC 20 performs a logical operation in synchronization with the H clock signal.

As shown in Fig. 4C, the analog data signal is continuously input to the driver IC 20 in series.

The start pulse as shown in FIG. 4A is input to the first shift register SR ₁ . The first shift register SR ₁ takes a start pulse in the case of the reception of the first H clock signal and transmits the first shift registers SR ₂ to SR _n as its output.

When the second to Nth shift registers SR ₂ to SR _n respectively receive the second to NH clock signals, the shift pulses SRO ₂ to SRO _n even when the first shift pulse SRO ₁ is shifted. Send continuously. The shift pulse SRO _n is transmitted from the Nth shift register SR _n as a start pulse to be directed to the next drive IC.

The first group of shift pulses SRO ₁ to SRO _{n / 2} is transmitted from the first group SR ₁ to SR _{n / 2} of the shift register, while the switch control circuit 22 controls the main switch SWd. The signal CONTA is transmitted to select the first divided data line 21a. On the other hand, the second group of shift pulses SRO _{n / 2 + 1} to SRO _n is transmitted from the second group SR _{n / 2 + 1} to SR _n of the shift register, while the switch control circuit 22 The control signal CONTB is sent to the main switch SWd to select the second divided data line 21b.

As described above, the first group of switches SW ₁ to SW _{n / 2} electrically connect the first divided data line 21a to the sampling and holding circuits S / H ₁ to S / H _{n / 2} . Or separate the first divided data line 21a from the sampling and holding circuits S / H ₁ to S / H _{n / 2} . The second group of switches SW _{n / 2 + 1} to SW _{n electrically} connects the second divided data line 21b to the sampling and holding circuits S / H _{n / 2 + 1} to S / H _n . The second divided data line 21b is separated from the sampling and holding circuits S / H _{n / 2 + 1} to S / H _n .

While the shift pulse is at the H level, the switch that receives such a shift pulse remains on. As a result, the associated sampling and holding circuit samples and holds the analog data signal, charging the analog capacitor in the sampling and holding circuit.

As the shift registers SR ₁ to SR _n continuously transmit the shift pulses SRO ₁ to SRO _n in accordance with the H clock signal, the analog data signal is continuously sampled and charged in sequence with the associated sustain capacitor. After all the holding capacitors have been sampled and charged with the held data, all the data are transmitted through the output amplifier 23 and written to the liquid crystal display panel.

In an embodiment, the sampling and holding circuits S / H ₁ to S / H _n are designed to include a pair of holding capacitors. One of the holding capacitors is charged while the other holding capacitor transmits the output. The holding capacitor is switched to use every line.

In the following, the operation of the main switch SWd and the switch control circuit 22 will be described with reference to FIG.

As described above, the first and second analog switches 24a and 24b are controlled by the first and second control signals CONTA and CONTB. When the first and second control signals CONTA and CONTB are at the H and L levels, respectively, the first and second analog switches 24a and 24b are turned on and off, and the first group of shift pulses SRO ₁ through. SRO _{n / 2)} a first control signal (CONTA) is held at H level, the second group of shift pulses (SRO _{n / 2 + 1} to SRO _n) a second control signal (CONTB during transmission during transmission Is assumed to remain at the H level.

The switch control circuit as shown in Figs. 3B and 3C transmits the first and second control signals CONTA and CONTB so that the first and second analog switches 24a and 24b operate in the manner described above.

An embodiment of an analog-type full color LCD including the above-mentioned driving device IC is described with reference to FIG.

The analog-type full color LCD shown in FIG. 5 is connected in series across a connection substrate 31, a liquid crystal display panel 32, a liquid crystal display panel 32 for driving data lines in the liquid crystal display panel 32, and a connection substrate. Receives a number of driving device ICs (IC ₁ to IC _m ), a synchronization signal and an analog video signal, and processes analog video signals, and processes the processed analog video signals to each of the driving device ICs (IC ₁ to IC _m ). A signal processor 33 for transmitting and transmitting the start pulse 30 to the first driving device IC ₁ , and a flexible printed circuit board 38 for connecting the signal processor 33 to the connection board 31. do.

The connection board 31 includes wirings 39 each electrically connected to each of the driving device ICs IC ₁ to IC _m . The processed analog video signal is transmitted to each of the respective driving device ICs IC ₁ to IC _m through the wiring 39.

The driver IC typically outputs 384 dots. Thus, eight driver ICs are arranged in series on an XGA type LCD (1024x3 dots in the horizontal direction), and ten driver ICs are arranged in series on an SXGA type LCD (1024x3 dots in the horizontal direction).

Analog-type full color LCDs typically receive horizontal and vertical sync signals and analog video signals. Such a signal is received at the signal processor 33.

The signal processor 33 includes a controller 34, a PLL circuit 35 that receives horizontal and vertical synchronization signals and transmits a clock signal to the controller 34, and an analog signal processing circuit 36 that receives and processes analog data signals. And a buffer amplifier 37 for transmitting a data signal to each of the driving device ICs IC ₁ to IC _m .

The controller 34 receives the horizontal and vertical synchronizing signals and the clock signals transmitted from the PLL circuit 35 and transmits control signals to the analog signal processing circuit 36 and the buffer amplifier to control them. The controller 34 also transmits a start pulse to the first drive device IC1.

Analog signal processing circuit 36 is a time conversion of the analog video signal, Perform the conversion and data inversion. The analog video signal is processed by the analog signal processing circuit 36 and transmitted to the respective driving device ICs IC ₁ to IC _m through the buffer amplifier 37 and the wiring 39.

The controller 34 generates the start pulse 30 and transmits the start pulse 30 to the first drive device IC ₁ through the flexible printed circuit 38. Upon receiving the start pulse, the first drive unit IC ₁ transmits a start pulse to the second drive unit IC ₂ . In the same way, upon receiving a start pulse from the previous driver IC _n-1 , the driver IC transmits a start pulse to the next driver IC _{n + 1} .

As described above, upon receiving the start pulse, the shift register transmits a shift pulse at each driver IC. When the first group of shift pulses SRO ₁ to SRO _{n / 2} is generated, the first divided data line 21a is activated, while the second group of shift pulses SRO _{n / 2 + 1} to SRO _{When n} ) is generated, the second divided data line 21b is activated. When transmitting a start pulse to the next driver IC including such data lines 21a and 21b, the first and second divided data lines 21a to 21b are deactivated. Therefore, in the analog-type full color LCD shown in FIG. 5, characterized in that a plurality of drive unit ICs are arranged in series, of the first and second divided data lines 21a and 21b in one drive unit IC. Only one is active.

Although the data line is divided into two parts, that is, the first and second divided data lines 21a and 21b in the above-described embodiment, it should be known that the number of parts in which the data line is divided is not limited to two. . The data line may be divided into three or more parts.

FIG. 6 shows an embodiment in which a data line is divided into three parts, namely, first to third divided data lines 42a, 42b, and 42c.

The analog data signal is input to the drive device IC 40 through the terminal 43 located at the center of the drive device IC 40. The analog data signal is transmitted to one of the first to third divided data lines 42a, 42b and 42c via the main switch SWd controlled according to the control signal CONT transmitted from the switch control circuit 41. The analog data signal is input at its center into the first, second or third divided data lines 42a, 42b, or 42c to improve the charging characteristics of the holding capacitor and the image quality.

The switch control circuit 41 transmits a control signal CONT to the main switch SWd, and selects one of the first to third divided data lines 42a to 42c in accordance with the shift pulse transmitted from the shift register. . When the drive IC transmits a start pulse, the main switch SWd is open, i.e., the main switch SWd is open to any one of the first to third divided data lines 42a to 42c in the drive IC. The terminal 43 is not electrically connected.

The other operation is the same as that of the above-described embodiment.

Advantages obtained by the present invention described above are as follows.

According to the present invention, the data lines are divided into two or more numbers of divided data lines in the apparatus. Therefore, the wiring resistance and the capacity of the data line are reduced, and the number of switches electrically connected between the data line and the sampling and holding circuit can be reduced, so that the parasitic capacitor caused by the switch can be reduced. .

In addition, since the active split data line is part of the data line, it is possible to reduce the load on the buffer amplifier, ensuring an improvement in the rate at which the analog-type full color LCD operates. In addition, for the same reason, the load on the buffer amplifier can be reduced and the power consumption in the analog-type full color LCD can be reduced.

In addition, the division of the data line improves the characteristic of charging the holding capacitor farthest from the input terminal into which the analog data signal is input to the data line. By inputting an analog data signal into the device at the center thereof, the difference between the charging characteristics of the device can be eliminated, and the image quality of the analog-type full color LCD can be improved.

Further, according to the present invention, the analog data signal is input to the device in the same manner as in the conventional device. Therefore, the present liquid crystal display panel including the device for driving the data line can be used by simply replacing the conventional device as the device according to the present invention.

Claims (15)

In the data line drive devices 20 and 40 in the liquid crystal display panel, (a) a data line to which analog data is input; (b) one or more shift registers SR ₁ to SR _n for transmitting shift pulses SRO ₁ to SRO _n ; And (c) one or more circuits (S / H ₁ to S / H _n ) for sampling and holding the analog data signal in accordance with the shift pulses SRO ₁ to SRO _n and transmitting a voltage signal, The data line consists of first to Nth divided data lines 21a, 21b; 42a, 42b, 42c, and the analog data signal is comprised of the first to Nth data lines 21a, 21b; 42a, 42b, 42c), and N is an integer of 2 or more. The method of claim 1, And said analog data signal is input at one of said first to Nth data lines (21a, 21b; 42a, 42b, 42c) at the center thereof. The method of claim 1, When the shift registers SR ₁ to SR _n transmit shift pulses SRO ₁ to SRO _n , the analog data signal is selected from the first to Nth data lines 21a, 21b; 42a, 42b, and 42c. The data line driving apparatus, which is not input to any one. The method of claim 1, And N is 2, and the first and second divided data lines (21a and 21b) are equal in length to each other. The method according to any one of claims 1 to 4, And a signal input terminal (25 and 43) for inputting the analog data signal to the device (20), wherein the signal input terminal is located at the center side of the device (20). The method according to any one of claims 1 to 4, (d) a switch (SWd) through which the analog data signal is transmitted to one of the first to Nth divided data lines (21a, 21b; 42a, 42b, 42c); (e) further comprising switch control circuits (22 and 41) for transmitting a control signal (CONT) to said switch (SWd) for controlling the operation of said switch (SWd). The method according to any one of claims 1 to 4, And the switch control circuit (22 and 41) transmits the control signal (CONT) in accordance with the operation of the shift registers (SR ₁ to SR _n ). The method of claim 6, The switch SWd is a first to Nth analog switch 24a and 24b whose operation is controlled by first to Nth control signals CONTA and CONTB transmitted from the switch control circuits 22 and 41, respectively. Data line, characterized in that it comprises first to Nth analog switches 24a and 24b electrically connected to the first to Nth divided data lines 21a, 21b; 42a, 42b, 42c, respectively. drive. The method of claim 8, The switch control circuits 22 and 41 respectively receive _first to Nth shift pulses SRO ₁ to SRO _n transmitted from the first to Nth groups of the shift registers SR ₁ to SR _n , and First to Nth OR circuits 26a and 26b which respectively transmit the first to Nth control signals CONTA and CONTB indicating the sum of the first to Nth shift pulses SRO ₁ to SRO _n . A data line driving device comprising a. The method of claim 8, The switch control circuits 22 and 41 are set at the rising edge of the initial shift pulse in each of the first to Nth groups of shift pulses and the falling edge of the last shift pulse in each of the first to Nth groups of shift pulses. And a first to N-th SR flip-flop (27a and 27b) to be reset in Tx, and transmitting the first to Nth control signals. Liquid crystal display device, (a) liquid crystal display panel 32; (b) A driving device (IC ₁ to IC _m ) mounted in a cascade on the liquid crystal display panel 32 for driving a data line in the liquid crystal display panel 32, wherein the liquid crystal display panel 32 includes: A plurality of driving devices IC ₁ to IC _m each defined in any one of the preceding claims; And (c) receive a synchronization signal and an analog video signal, process the analog video signal, and thus transmit the processed analog video signal to each of the devices IC ₁ to IC _m , and also to the device IC ₁ to IC _m) liquid crystal, characterized in that it comprises a signal processor 33 for transmitting the start pulse (30) to be transmitted to an adjacent device from the device - the first device (IC ₁₎ of the device (IC ₁ to IC _m) Display device. The method of claim 11, The transmitted to each of the devices (IC ₁ to IC _m), the device (IC ₁ to IC _m) through the connecting board 31, the wiring 39 having a wiring 39 electrically connected to each And a processed analog video signal, the respective devices (IC ₁ to IC _m ) mounted over the liquid crystal display panel (32), and the connection substrate (31). The method of claim 12, And a flexible printed circuit (38) for connecting the signal processor (33) to the connection board (31). In the method for driving a data line in a liquid crystal display panel, (a) inputting an analog data signal into a selected one of the first through Nth divided data lines 21a, 21b; 42a, 42b, 42c, where N is an integer of 2 or more; (b) sampling and maintaining the analog data signal in accordance with a shift pulse to transmit a voltage signal; And and (c) driving a data line in accordance with the voltage signal. The method of claim 14, And when the shift pulse is not transmitted, the analog data signal is not input to any one of the first to Nth divided data lines.