KR100560998B1 - Circuit for driving electrodes of a thin film transistor-liquid crystal display devices - Google Patents

Abstract

Disclosed is an electrode driving circuit for a thin film transistor liquid crystal display device capable of minimizing data damage by preventing overlapping data of two adjacent horizontal lines in the thin film transistor liquid crystal display device. The data register sequentially samples and outputs a plurality of video data signals provided from the data controller in response to the sequential sampling clock signals. The delay circuit delays the video data signal at the position where sampling starts at the data register designated by the sequential sampling clock signal among the plurality of video data signals output from the data register in response to the main clock signal for a predetermined time. Output The data latch unit receives and latches and outputs a video data signal from the delay circuit and a plurality of video data signals from the data register. Therefore, by continuously outputting data, video data signals corresponding to horizontal lines of two adjacent blocks can be prevented from overlapping each other and being written to the data latch unit, and damage of the video data signal can be minimized.

Description

Electrode driving circuit for thin film transistor liquid crystal display device {CIRCUIT FOR DRIVING ELECTRODES OF A THIN FILM TRANSISTOR-LIQUID CRYSTAL DISPLAY DEVICES}

1 is a block diagram schematically showing the configuration of an electrode driving circuit for a conventional thin film transistor liquid crystal display element;

2 is a block diagram showing a configuration of an electrode driving circuit for a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention;

3 and 4 are block diagrams showing the configuration of an electrode driving circuit for a thin film transistor liquid crystal display device according to another preferred embodiment of the present invention; And

FIG. 5 is a circuit diagram showing an example of a configuration of a delay circuit of an electrode driving circuit for a thin film transistor liquid crystal display device according to the present invention shown in FIGS. 2 to 4; And

Fig. 6 is a circuit diagram showing another example of the configuration of a delay circuit of an electrode driving circuit for a thin film transistor liquid crystal display device according to the present invention shown in Figs.

<Explanation of symbols for the main parts of the drawings>

100, 110, 120: data control unit 200, 210, 220: shift register

300, 310, 320: data register 400a, 400b, 410, 420: delay circuit

500a, 500b: Multiplexer 600, 510, 520: Data latch portion

700, 610, 620: Digital / Analog Converter 800, 710, 720: Output Buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode driving circuit for a thin film transistor liquid crystal display device, and more specifically, to a horizontal line in two adjacent blocks in a polysilicon thin film transistor liquid crystal display device driving by dividing one horizontal line into a plurality of blocks. The present invention relates to an electrode driving circuit for a thin film transistor liquid crystal display device capable of minimizing data damage by preventing data overlap between lines.

In general, a thin film transistor liquid crystal display (TFT-LCD) is an amorphous silicon TFT-LCD (hereinafter referred to as an 'amorphous silicon TFT-LCD'). And a polysilicon thin film transistor liquid crystal display device (Polysilicon TFT-LCD, hereinafter referred to as 'polysilicon TFT-LCD').

1 is a block diagram schematically showing a configuration of an electrode driving circuit for a conventional amorphous silicon thin film transistor liquid crystal display device.

As shown in FIG. 1, an electrode driving circuit for an amorphous silicon TFT-LCD receives a plurality of video data signals continuously from a timing controller (not shown) and stores them in a data register 30 designed inside the electrode driving circuit. do.

The video data signal stored as described above is output by the sequential sampling clock signal SS_CLK output from the shift register 20, and the video data signals are analogized by the digital / analog converter 50 through the data latch 40. Is converted into a signal.

Next, the output signal from the digital / analog converter 50 selects and outputs an analog voltage indicating gray scale through the output buffer 60.

Many researches have been conducted in relation to the electrode driving voltage of the liquid crystal display device, which is called "APPARATUS AND METHOD FOR DRIVING SIGNAL ELECTRODES FOR LIQUID CRYSTAL DISPLAY DEVICES." US Pat. No. 4,859,9998, issued to Masao Kawamura et al., Discloses a loss of current by the latch circuit latching the video data signal one time during one horizontal scan interval until the next latch pulse is generated. Disclosed are an apparatus and a method that can be saved.

In general, a timing controller (not shown) provides a main clock signal M_CLK and video data signals D1, D2, D3, ..., Dm required for driving the TFT-LCD panel. A blanking time in which video data signals are continuously output until all the video data signals for driving one horizontal line are written, and then the transmission of the video data signals is paused until the video data signals of the next horizontal line are written. (blanking time).

As described above, the electrode driving circuit for the TFT-LCD corresponds to one horizontal line because a blanking time exists between the video data signal for driving one horizontal line and the video data signal for driving the next horizontal line. After storing all the video data signals D1, D2, D3, ..., Dm in the internal data register 30, a control signal may be generated to simultaneously output the stored data.

On the other hand, the electrode driving circuit for the polysilicon TFT-LCD also receives a video data signal continuously output from the graphics controller and outputs the same, so as to drive one horizontal line like the electrode driving circuit for the amorphous silicon TFT-LCD. It has a blanking time after transmitting all the video data signals.

The polysilicon TFT-LCD panel continuously outputs the driving voltage of the column line using only one or two electrode driving circuits. At this time, the TFT switches formed inside the TFT-LCD panel control the output data of the electrode driving circuit on a block-by-block basis so that the column electrodes of the TFT-LCD panel are sequentially driven one block at a time.

However, according to such a conventional TFT-LCD electrode driving circuit, the video data signal corresponding to one horizontal line is continuously input to the electrode driving circuit. Therefore, when the TFT switches are turned on to output the video data signal stored in the data register 30 of the electrode driving circuit, the voltage corresponding to the horizontal line of the next block at some outputs located at the beginning or the end of the output of the electrode driving circuit. This sample has an output characteristic that is sampled and overwritten with an analog voltage for driving the horizontal line of the current block.

That is, when the video data signal corresponding to one horizontal line is sequentially sampled and stored in the data latch 40 from the data register 30, the video corresponding to the horizontal line of the next block input to the data register 30. Data signals are also simultaneously stored in the data latch 40 while the TFT switches are turned on. Accordingly, data corresponding to the horizontal lines of two adjacent blocks are overwritten in the data latch 40, thereby damaging the video data signal.

The present invention proposed to solve the above-described problem, in the thin film transistor liquid crystal display device driving by dividing one horizontal line into a plurality of blocks prevents data corruption by overlapping data between horizontal lines of two adjacent blocks. An object of the present invention is to provide an electrode driving circuit for a thin film transistor liquid crystal display device that can be minimized.

According to an embodiment of the present invention, an electrode driving circuit for a thin film transistor liquid crystal display device receives a plurality of video data signals and outputs the plurality of video data signals in synchronization with a main clock signal. And a shift register for generating a sequential sampling clock signal in response to an L / R control signal for controlling a start position of sampling of the main clock signal and the plurality of video data signals, and the sequential sampling clock signal. A data register for sequentially sampling and outputting a plurality of video data signals from the data control means in response to the signal; and the sequential sampling clock among the plurality of video data signals output from the data register in response to the main clock signal. Determined by the signal At least two delay means for receiving a video data signal corresponding to a position at which sampling is started in the data register, and outputting the delayed signal for a predetermined time; and corresponding to each of the at least two delay means. Receiving a delayed video data signal, receiving a video data signal corresponding to a position at which sampling is started in the data register, and receiving a delayed video data signal by the delay means in response to the L / R control signal. And at least two selection means for selecting and outputting any one of the video data signals corresponding to the position at which sampling is directly input from the data register.

According to another aspect of the present invention, an electrode driving circuit for a thin film transistor liquid crystal display device receives a plurality of video data signals and outputs the plurality of video data signals in synchronization with a main clock signal. And a shift register for generating a sequential sampling clock signal in response to an L / R control signal for controlling a start position of sampling of the main clock signal and the plurality of video data signals, and the sequential sampling clock signal. A data register for sequentially sampling and outputting a plurality of video data signals from the data control means in response to the signal; and the sequential sampling clock among the plurality of video data signals output from the data register in response to the main clock signal. Texture by signal Delay means for delaying and outputting a video data signal corresponding to a position at which sampling is started in the data register for a predetermined time; and a plurality of directly provided from the video data signal and the data register delayed by the delay means. And latch means for receiving and latching a video data signal.

The delay means includes a plurality of D-type flip-flops, and the plurality of D-type flip-flops have a form in which an output from the D-type flip-flop at the front end is input to an input terminal of the D-type flip-flop at the rear end.

According to such an electrode driving circuit for a thin film transistor liquid crystal display device, a video data signal corresponding to a position at which sampling is started is selected from among a plurality of video data signals corresponding to one horizontal line provided from a data register to a data latch unit. Delay is provided to the data latch unit.

Therefore, before the video data signal corresponding to the position where the sampling of the plurality of video data signals corresponding to the next horizontal line starts is input to the data latching unit, the video data signal corresponding to the current horizontal line is transmitted to the data latching unit. Is complete.

Hereinafter, an electrode driving circuit for a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 2 to 6.

2 is a block diagram illustrating a configuration of an electrode driving circuit for a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the TFT-LCD electrode driving circuit according to an exemplary embodiment of the present invention transmits a plurality of input video data signals D1, D2, D3,..., And Dm to the main clock signal M_CLK. A data control unit 100 for synchronously outputting, a shift register 200 for generating a sequential sampling clock signal SS_CLK, and a plurality of video data signals D1, D2, D3, ..., a data register 300 for sequentially sampling and outputting Dm), a first data for delaying and outputting a video data signal at a position at which sampling is started in the data register 300 for a predetermined time; For selecting and outputting any one of the second delay circuits 400a and 400b, the video data signals from the first and second delay circuits 400a and 400b, and the video data signals from the data register 300. First and second multiplexers 5 00a and 500b, a data latch unit 600 for receiving and latching video data signals from the first and second multiplexers 500a and 500b and a plurality of video data signals from the data register 300; , A digital-to-analog converter 700, and an output buffer 800.

Hereinafter, the operation of the electrode driving circuit for the thin film transistor liquid crystal display device according to the exemplary embodiment of the present invention described above with reference to FIG. 1 will be described in more detail.

The electrode driving circuit for the thin film transistor liquid crystal display device receives a main clock signal M_CLK and video data signals D1, D2, D3, ..., Dm from a timing controller (not shown).

The data controller 100 receives a plurality of video data signals D1, D2, D3,..., Dm provided from the timing controller (not shown), and similarly receives the plurality of video data signals from the timing controller. The data is output to the data register 300 in synchronization with the main clock signal M_CLK generated from (not shown).

The shift register 200 is an L / R control signal LR_CS for controlling a start position of sampling of the main clock signal M_CLK and the plurality of video data signals D1, D2, D3, ..., Dm. And a sequential sampling clock signal SS_CLK used to sample the plurality of video data signals D1, D2, D3, ..., Dm, which are continuously output from the data controller 100 by using the shift data signal. ) Is provided to the data register 300.

The data register 300 includes a plurality of video data signals D1, D2, which are sequentially input from the data controller 100 in response to the sequential sampling clock signal SS_CLK from the shift register 200. D3, ..., Dm) are sampled sequentially and stored.

Here, the shift register 200 transmits the plurality of video data signals D1, D2, D3, ..., Dm from the data register located at the end of the output based on the L / R control signal LR_CS. You can decide to sample, or sample from the data register located at the beginning of the output.

Next, the plurality of video data signals D1, D2, D3,..., Dm stored in the data register 300 are output to the data latch unit 600.

At this time, sampling determined by the sequential sampling clock signal SS_CLK from the shift register 200 among the plurality of video data signals D1, D2, D3,..., Dm output from the data register 300. The video data signal at the position where the sampling starts in the sequence is input to the first delay circuit 400a and the first multiplexer 500a or the second delay circuit 400 and the second multiplexer 500b. Then, the remaining video data signal except for the video data signal at the position where sampling is first started is immediately provided to the data latch unit 600 and stored.

In more detail, sampling of the plurality of video data signals D1, D2, D3,..., Dm stored in the data register 300 starts with the video data signal 'D1' and goes to 'Dm'. Assuming that it is over, the video data signal 'D1' of the plurality of video data signals D1, D2, D3, ..., Dm output from the data register 300 is the first delay circuit 400a and the It is input to the first multiplexer 500a.

The video data signal 'Dm' at the position where sampling of the plurality of video data signals D1, D2, D3, ..., Dm ends is transferred to the second delay circuit 400b and the second multiplexer 500b. Is entered. The remaining video data signals except for the video data signals 'D1' and 'Dm' are directly provided to the data latch unit 600.

The first and second delay circuits 400a and 400b respectively delay the video data signals D1 and Dm input from the data register 300 for a predetermined time in synchronization with the main clock signal M_CLK. These delayed video data signals 'D1' and 'Dm' are provided to the first and second multiplexers 500a and 500b, respectively.

Next, the first multiplexer 500a receives the video data signal 'D1' delayed by a predetermined time from the first delay circuit 400a and passes through the first delay circuit 400a from the data register 300. Video data signal 'D1' is provided.

The first multiplexer 500a is configured based on the L / R control signal LR_CS indicating a start position of sampling of the plurality of video data signals D1, D2, D3, ..., Dm. It can be seen that sampling of the plurality of video data signals D1, D2, D3,..., Dm from 300 starts from the video data signal 'D1'.

Accordingly, the first multiplexer 500a may be configured to the first delay circuit 400a from among delayed video data signals and non-delayed video data signals provided from the first delay circuit 400a and the data register 300, respectively. The video data signal 'D1' is delayed by the data latch unit 600.

Next, the second multiplexer 500b receives the video data signal 'Dm' delayed by a predetermined time from the second delay circuit 400b and passes through the second delay circuit 400b from the data register 300. Video data signal 'Dm' is provided.

Similarly, the second multiplexer 500b receives the plurality of video data signals D1, D2, D3,..., Dm from the data register 300 based on the L / R control signal LR_CS. It can be seen that the sampling of is started from the video data signal 'D1'.

Accordingly, the second multiplexer 500b is directly connected from the data register 300 among delayed video data signals and non-delayed video data signals provided from the second delay circuit 400b and the data register 300, respectively. The provided non-delayed video data signal 'Dm' is output to the data latch unit 600.

On the other hand, it is assumed that sampling of the plurality of video data signals D1, D2, D3,..., Dm stored in the data register 300 starts with the video data signal 'Dm' and ends with 'D1'. In this case, the operations of the first and second multiplexers 500a and 500b are reversely performed to change output characteristics thereof.

That is, the first multiplexer 500a is provided directly from the data register 300 among delayed video data signals and non-delayed video data signals provided from the first delay circuit 400a and the data register 300, respectively. The non-delayed video data signal 'D1' is provided to the data latch unit 600.

In addition, the second multiplexer 500b may be connected to the second delay circuit 400b among delayed video data signals and non-delayed video data signals provided from the second delay circuit 400b and the data register 300, respectively. The video data signal 'Dm' delayed is provided to the data latch unit 600.

Accordingly, a plurality of video data signals continuously input and output to the data register 300 are delayed for a predetermined time by the video data signals (D1 or Dm), which are initially sampled, regardless of the sampling order. And provided to the data latch unit 600.

Therefore, the data latch unit for the video data signal corresponding to the current horizontal line before the video data signal corresponding to the position where the sampling of the video data signal corresponding to the next horizontal line starts is input to the data latch unit 600. Transmission to 600 may be completed.

Subsequently, the plurality of video data signals D1, D2, D3,..., Dm latched in the data latch unit 600 are converted into analog signals by the digital / analog converter 700. It is output as signals Y1, Y2, Y3, ..., Yn for driving the electrodes through the output buffer 800.

5 and 6, configurations of the first and second delay circuits 400a and 400b are as follows. 5 and 6 are circuit diagrams showing the configuration of a delay circuit of an electrode driving circuit for a thin film transistor liquid crystal display device according to the present invention.

Referring to FIG. 5, the first and second delay circuits 400a and 400b include a plurality of D-type flip-flops DF1, DF2,..., DFm as shown in FIG. 5. The plurality of D-type flip-flops DF1, DF2, ..., DFm have a form in which an output from the D-type flip-flop at the front end is input to an input terminal of the D-type flip-flop at the rear end. The main clock signal M_CLK is input to each clock terminal CK of the plurality of D flip-flops DF1, DF2,..., DFm.

Meanwhile, as shown in FIG. 6, the first and second delay circuits 400a and 400b include a plurality of JK flip-flops JKF1, JKF2, ..., JKFm. Many JK-type flip-flops (JKF1, JKF2, ..., JKFm) may have a form in which the output from the JK-type flip-flop at the front end is input to the input terminal of the JK-type flip-flop at the rear end, or RS latch It can also be configured.

Here, the number of D-type flip-flops or JK-type flip-flops used in the first and second delay circuits 400a and 400b depends on the time to delay the video data signal from at least two stages. In consideration of the turn-on time and the chip area of the switch, the number of flip-flops is preferably 10 steps or less.

Hereinafter, an electrode driving circuit for a thin film transistor liquid crystal display device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4. 3 and 4 are block diagrams showing the configuration of an electrode driving circuit for a thin film transistor liquid crystal display device according to another exemplary embodiment of the present invention.

3 and 4, a TFT-LCD electrode driving circuit according to another embodiment of the present invention may include a plurality of input video data signals D1, D2, D3,..., And Dm as a main clock signal. A data control unit 110 or 120 for outputting in synchronization with (M_CLK), a shift register 210 or 220 for generating a sequential sampling clock signal SS_CLK, and a plurality of data control units 110 or 120 from the data control unit 110 or 120; A data register 310 or 320 for sequentially sampling and outputting the video data signals D1, D2, D3, ..., Dm, and a video at a position at which sampling is started in the data register 310 or 320; A delay circuit 410 or 420 for delaying and outputting a data signal for a predetermined time, a video data signal from the delay circuit 410 or 420, and a plurality of video data signals from the data register 310 or 320; Receive input And a data latch section for latching (510 or 520) and a digital / analog converter (610 or 620), the hitting has an output buffer (710 or 720).

3 and 4, the electrode driving circuit shown in FIG. 3 and FIG. 4 is the first of a plurality of video data signals corresponding to one horizontal line at a position at which sampling of the plurality of video data signals DF1, DF2,..., DFm starts. Is fixed to the video data signal (eg, 'D1') or the last video data signal (eg, 'Dm').

Accordingly, in the electrode driving circuit for the thin film transistor liquid crystal display device illustrated in FIGS. 3 and 4, a delay circuit 410 for delaying a video data signal between the data register 310 and the data latch unit 510 is provided. Only one is designed.

That is, in the electrode driving circuit shown in FIG. 3, sampling of the plurality of video data signals DF1, DF2,..., DFm always proceeds from the first video data signal 'D1' to the last video data signal 'Dm'. The sampling operation of the plurality of video data signals DF1, DF2, ..., DFm in the electrode driving circuit shown in FIG. 4 is always the first video data signal 'D1' from the last video data signal 'Dm'. It is going to be.

Therefore, the electrode driving circuit for the thin film transistor liquid crystal display element shown in FIGS. 3 and 4 does not require the first and second multiplexers 500a and 500b as shown in FIG. Because the position at which the sampling operation of the plurality of video data signals is started is the same for all horizontal lines, the data latch (D1 or Dm), which is always input to the same position, is delayed for a predetermined time to latch the data. This is because it is sufficient to provide the parts 510 and 520.

3, the data control unit 110, the shift register 210, the data register 310, the delay circuit 410, the data latch unit 510, the digital / analog converter 610, and the output buffer 710. Each operation of C) is the same as those shown in FIG.

The plurality of video data signals D1, D2, D3, ..., Dm sequentially sample from the first video data signal 'D1' to the last video data signal 'Dm' by the sequential sampling clock signal SS_CLK. The first video data signal 'D1' is always input to the delay circuit 410 when it is outputted from the data register 310 to the data latch unit 510.

The delay circuit 410 delays the first video data signal 'D1', which is a video data signal at the position where sampling is started, for a predetermined time in synchronization with the main clock signal M_CLK, to the data latch unit 510. to provide.

The operations of the data register 310, the delay circuit 410, and the data latch unit 510 are similarly performed for the plurality of video data signals corresponding to the next horizontal line. This is because the TFT-LCD electrode driving circuit shown in Fig. 3 always generates the last video data signal (in this case, 'D1') from the first video data signal (in this case, 'D1') by the L / R control signal LR_CS. This is because sampling proceeds with Dm ').

Therefore, the data latch unit for the video data signal corresponding to the current horizontal line before the video data signal corresponding to the position where the sampling of the video data signal corresponding to the next horizontal line starts is input to the data latch unit 510. Transmission to 510 may be completed.

Meanwhile, in FIG. 4, the data controller 120, the shift register 220, the data register 320, the delay circuit 420, the data latch unit 520, the digital / analog converter 620, and the output buffer. Each operation of 720 is the same as those shown in FIG. 2 above.

The plurality of video data signals D1, D2, D3, ..., Dm are sequentially sampled from the last video data signal 'Dm' to the first video data signal 'D1' by the sequential sampling clock signal SS_CLK. When the data register 320 is output from the data register 320 to the data latch unit 520, the last video data signal 'Dm' is always input to the delay circuit 420.

The delay circuit 420 delays the last video data signal 'Dm', which is a video data signal at the position where sampling is started, for a predetermined time in synchronization with the main clock signal M_CLK and provides it to the data latch unit 520. do.

The operation of the data register 320, the delay circuit 420, and the data latch unit 520 is similarly performed for the plurality of video data signals corresponding to the next horizontal line. The electrode driving circuit for the TFT-LCD shown in Fig. 4 always starts with the first video data signal (in this case, 'Dm') from the last L data signal (LR_CS). This is because sampling proceeds to D1 ').

Therefore, the data latch unit for the video data signal corresponding to the current horizontal line before the video data signal corresponding to the position where the sampling of the video data signal corresponding to the next horizontal line starts is input to the data latch unit 520. Transmission to 520 may be completed.

Here, the configurations of the delay circuits 410 and 420 of the electrode driving circuit for the TFT-LCD shown in Figs. 3 and 4 are the first and second in the electrode driving circuit for the TFT-LCD shown in Fig. 2 described above. It has the same configuration as the delay circuits 400a and 400b.

According to the electrode driving circuit for a thin film transistor liquid crystal display element as described above, among the plurality of video data signals corresponding to one horizontal line provided from the data register to the data latch portion, the video data signal corresponding to the position where the sampling starts is Delayed for a predetermined time is provided to the data latch unit.

Accordingly, the data for the video data signal corresponding to the horizontal line of the current block before the video data signal corresponding to the position where the sampling of the plurality of video data signals corresponding to the horizontal line of the next block starts is input to the data latch unit. Transfer to the latch section is completed.

Therefore, it is possible to prevent the video data signals corresponding to the horizontal lines of two adjacent blocks from overlapping each other and to be written to the data latch unit, and to minimize the damage of the video data signals.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (3)

Data control means for receiving a plurality of video data signals and outputting the plurality of video data signals in synchronization with a main clock signal; A shift register for generating a sequential sampling clock signal in response to an L / R control signal for controlling a start position of sampling of the main clock signal and the plurality of video data signals; A data register for sequentially sampling and outputting a plurality of video data signals from said data control means in response to said sequential sampling clock signal; Predetermined time by receiving a video data signal corresponding to a position where sampling starts in the data register determined by the sequential sampling clock signal among the plurality of video data signals output from the data register in response to the main clock signal At least two delay means for delayed outputting; And Corresponding to each of the at least two delay means, a video data signal delayed by the delay means is input, a video data signal corresponding to a position at which sampling is started in the data register is directly input, and the L / R control is performed. And at least two selection means for selecting and outputting any one of a video data signal delayed by the delay means and a video data signal corresponding to a position at which sampling is directly input from the data register in response to the signal. An electrode drive circuit for thin film transistor liquid crystal display elements. Data control means for receiving a plurality of video data signals and outputting the plurality of video data signals in synchronization with a main clock signal; A shift register for generating a sequential sampling clock signal in response to an L / R control signal for controlling a start position of sampling of the main clock signal and the plurality of video data signals; A data register for sequentially sampling and outputting a plurality of video data signals from said data control means in response to said sequential sampling clock signal; Delaying a video data signal corresponding to a position at which sampling is started in the data register determined by the sequential sampling clock signal among the plurality of video data signals output from the data register in response to the main clock signal for a predetermined time; Delay means for outputting; And And latch means for receiving and latching a video data signal delayed by said delay means and a plurality of video data signals provided directly from said data register. The input terminal of claim 1 or 2, wherein the delay unit comprises a plurality of D flip-flops, and the plurality of D flip-flops have an output from a front-end D flip-flop and an input terminal of a rear D-type flip-flop. An electrode drive circuit for a thin film transistor liquid crystal display device, characterized in that it has a form to be input to.

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