TW557560B - Method of preparing copper metallization die for wirebonding - Google Patents

Method of preparing copper metallization die for wirebonding Download PDF

Info

Publication number
TW557560B
TW557560B TW091104380A TW91104380A TW557560B TW 557560 B TW557560 B TW 557560B TW 091104380 A TW091104380 A TW 091104380A TW 91104380 A TW91104380 A TW 91104380A TW 557560 B TW557560 B TW 557560B
Authority
TW
Taiwan
Prior art keywords
wafer
copper
patent application
cleaning
gasket
Prior art date
Application number
TW091104380A
Other languages
English (en)
Inventor
Kok Wai Mui
Fuaida Bte Harun
Lan Chu Tan
Nor Mohd Faizairi Bin Mohd
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW557560B publication Critical patent/TW557560B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48747—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/905—Cleaning of reaction chamber

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Description

557560 A7 B7 五、發明説明（ 發明背景 1·發明領域 本發明關於積體電路，更特別地，關於一種用以製備一 具有含鋼墊片之晶片以供更穩定的打線之半導體晶圓之方 法。 2·相關技術背景 積體電路（IC)晶片係一切割自一例如一碎晶圓之半 導體晶圓之小裝置，其上多晶片被形成。這類晶片典型地 經由使用一焊錫或環氧樹脂黏接它們至引線框以封裝保護 它們免於腐蚀。一晶片係電性連接至該引線框之引線，並 接著該晶片及該引線框被密封於一塑膠封裝中β該引線框 之引線自該封裝中伸出並終止於允許該晶片電性連接例如 一印刷電路板上之其它電路之接腳中。 參考圖4 ’ 一用以包裝一晶片之傳統方法被顯示。第一 ’在步驟40 ’ 一晶片係切自或鋸自它形成於其上之晶圓中 。在該晶片切割自該晶圓中後，在一晶片焊接或晶片黏附 步驟42中該晶片後面牢牢地被黏接至一載體或引線框。典 型地’在該晶片焊接步驟42中，該晶片係使用一例如一環 氧樹脂之有機黏劑黏接至該引線框並接著經烘烤處理。一 但該環氧樹脂被處理，在步驟44中該晶片係接線至該引線 框。 圖5係一封裝積體電路50之放大剖面圖。該封裝電路5〇 包含一焊接至一晶片黏接墊片52之晶片51。該晶片51係利 用接線54連接至一引線框53。又，該晶片51、晶片黏接塾 -5- 本紙蒗瓦度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 557560 A7 __B7 五、發明説明（2 )- 片52、接線54及部分該引線框53係密封或塑模於一封裝55 中。該封裝55可以是塑膠、金屬、陶瓷或另一已知封裝材 料。 該接線54連接該晶片51之焊接墊片至該引線框53之焊 接塾片。最常用的晶片連接技術係打線。打線係一固態焊 接處理，其中二金屬材料、一非常薄接線及一墊片表面係 產生接觸。一旦該表面係產生接觸，一熱、壓力及/或紫外 線能f之結合被用來產生電子分享或原子内擴散，導致一 接線之形成。 打線典型地係使用三種工業標準技術其中之一來製造 :使用一壓力與上升溫度結合之熱壓縮（T/C)焊接；使用一 壓力、上升溫度及超音波振動突波結合之熱聲波（T/s)烊接 :及使用一壓力及超音波振動突波結合之超音波（u/s)焊接 這些打線技術係熟知的。雖然也使用例如銀、铭/碎、銘 /鎂、鈀及銅，該較佳之接線材料係為金。 再參考至圖4，在該打線步驟44後，該晶片背面被清潔 ，典型地使用紫外線-臭氧（UV0)清潔法。在uvo清潔法中， 一發射大量鵪射之UV-臭氧清潔劑被用來自該晶片中移除 有機污染物。最後，步驟48,該晶片及引線框組件被塑模 ，形成圖5所示之封裝電路5〇。 在最近幾年，相對於鋁而言，因期待更高時脈速率與改 善之熱官理及執行精密間隔及超精密間隔銅打線能力故重 燃於1C中使用銅線之興趣。為了防止過渡金屬現象，最好 焊接銅線至銅墊片。 -6 - 本紙張尺度適用中國國家揉準(CMS) A4規格_i210x297公釐)
裝 訂
線 557560 A7 B7 五、發明説明（3 不幸地，銅具快速氧化及腐蝕之傾向。腐蝕可能完全打 開該接線兩端，而允許該接線移動至該封裝内，藉此引起 電性短路。該腐蝕發生於出現溼氣及污染物中β例如在 打線£域出線氯或溪可能引起氯化物或漠化物的形成而 引發焊接腐蚀。焊接腐蝕也增加該接線内連線之電阻。因 此，形成一穩定銅對銅焊接可能是困難的。據此，具有一 接線可更穩定焊接至其上之塾片表面係有好處的。 發明概述 為了提供更穩定接線，本發明提供一用以製備一具有許 多積體電路形成於其上之半導體晶圓之方法，該積體電路 具有由銅組成之墊片。在本方法中，該氧化物係自該銅墊 片中移除且接著該晶圓係真空包裝於一防震容器中β該氧 化物可以數種方法自該銅墊片中移除。一第一種方法包含 於一鹼性液中清潔該晶圓，對該已清潔晶圓執行酸中和， 及接著弄乾該晶圓。一第二方法包含以一酸溶液清潔該晶 圓，例如將該晶圓浸入一盆Ηβ〇4或ΗΝ〇3中，以水清洗該酸 清潔晶圆’施用一抗氧化劑活化劑至該銅蟄片表面，在應 用該抗氧化劑活化劑後以水清洗該晶圓，及接著弄乾該已 水洗晶圓。又一第三方法包含在一約為5_2〇毫托耳之超低 真空壓力中使用一約5-10%氫及約90-95%氬混合劑以電漿 清潔該銅墊片及接著濺鍍一例如鋁之非常薄氧化物鈍化層 至該銅整片之表面上。該氧化物鈍化層具有一約1至約i 〇 毫微米之厚度。 本發明又提供一以一銅線電性連接一積體電路之一銅 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
k 557560 A7 ___ B7 五、發明説明（4 ) 墊片與一引線框之一墊片之方法，包含下列步驟為使用約 5-10%氫及約90-95%氬電漿清潔該銅及接著將接線打線至 該已清潔鋼墊片及該引線框墊片。 圖式之簡單說明 本發明較佳具體實施例之前述概述及下列詳細說明在 配合所附圖式讀取時將會有較好的了解，顯示於該圖式具 體實施例係表現較佳的。然而，應注意，本發明不限於所 示之精心安排及手段。在該圖式中·· 圖1係一根據本發明之一第一具體實施例說明涉及製備 一具有一或更多積體電路形成於其上之半導體晶圓之步驟 之方塊圖； 圖2係一根據本發明之一第二具體實施例說明涉及製備 一具有一或更多積體電路形成於其上之半導體晶圓之步驟 之方塊圖； 圖3係一根據本發明之一第三具體實施例說明涉及製備 一具有一或更多積體電路形成於其上之半導體晶圓之步驟 之方塊圖； 圖4係一說b月涉及製備一積體電路裝置之傳統步驟之方 塊圖， 圖5係一封裝積體電路晶片之放大剖面圖；及 圖6係一根據本發明之一第四具體實施例說明 J，步及製備 一積體電路裝置之步驟之方塊圖。 發明之詳細說明 結合所附圖式說明於下之詳細說明係想要當成— 田 < —本發 -8 - 本紙張又度通用中a國家標準(CNS) A4規格(210 X 297公釐） 557560 A7 ___ B7 五、發明説明（5 ) 明所示之較佳具體實施例說明，而不要代表本發明實行之 唯一形式。該說明結合圖示具體實施例以執行程序步驟之 順序描述。然而，應了解，相同或等效功能及順序可由要 包括於本發明之精神及範圍内之不同具體實施例來達成。 在該圖式中，類似編號係用以指示全部類似元件。 如前述，因電性效率及成本優點故使用銅内連線金屬化 技術來製造積體電路變得普遍。為了防止過渡金屬現象， 提供給IC銅墊片❶典型地，雖然銅及銀也可使用，但打線 具有晶片載體或引線框之1C係使用金及鋁線材料來執行。 烊接這些線至不同墊片材料產生不同冶金系統。如此，基 於提供1C銅墊片之相同理由，最妤使用銅線來連接該1(：之 銅墊片至該引線框。 不幸地’銅氧化非常快，使它更難以達到一穩定接線。 因此’為了確保該接線之焊接度及穩定度，該關鍵條件其 中之係該烊接表面須沒有任何污染物。典型地，電路係 在某一地方形成於晶圓上且接著該晶圓被傳送至自該晶圓 中切割及封裝該電路所在之另一地方。因相當多時間花在 該晶圓製造及;·該封裝處理之間，該銅墊片氧化可能發生於 這類時期。據此，本發明在製造該電路於一晶圓後並在該 晶圓被包裝載至該封裝場所前提供來清潔一積體電路之鋼 塾片。 現在參考至圖1，顯示一製備一具有許多積體電路形成 於其上之半導體晶圓之弟一方法，該積體電路具有由銅組 成足墊片。在一矽晶圓上形成具有銅墊片之電路之方法係 -9- 本紙尺度通用中a a家標準(CNS) :\4規格(21() x 297公董) 557560 A7 B7 五、發明説明（6 ) 已知且一其詳細說明用於了解本發明是不需要的。應了解 ’本發明方法係在一積體電路已形成於該晶圓上後才執行 。大致上，此係在所有層已施加至該晶圓且該晶圓已於解 離子水中清洗而該晶圓背面已被磨平以移除不要的材料後 ’又，最妤，在各晶片或裸晶之測試已執行後。典型地， 在執行測試後，該晶圓再使用例如解離子水、異丙基乙醇 、丙酮及甲醇之溶劑來清潔。本發明係指向在該晶圓已經 測試後所執行之清潔並提供用以自該銅塾片中移除氧化物 及接著真空包裝該晶圓。 更特別地’始於步驟10 ’該晶圓及特別是各晶片之銅勢 片係以驗液來清潔。最好，該晶圓係在室溫下利用一鹼性 溶液將該晶圓浸入或埋入一鹼性浴盆中約1至約20秒間。用 以移除氧化物之鹼性溶液通常被用來製造引線框且係為那 些熟知此項技術之人士所熟知。 自該鹼性浴盆移除該晶圓後，一酸中和步驟12被執行。Λ 該酸中和步驟12最好係執行於室溫下在一酸性浴盆中浸入 或埋入該晶圓約1至約20秒以確保所有氧化物已自該銅墊 片中被移除。所使用之酸最好係為h2so4或ηνο3，然而，其 它酸也可使用，例如磷酸、過氧化氩、氫.氟酸及鹽酸，這 些係商用且常用於半導體製造處理中。然而，將了解，據 那些熟知此項技術之人士所了解之例如檸檬酸之其它酸也 可被使用。 在該酸中和步驟12後，該晶圓在步驟14被弄乾。該晶圓 可使用環繞或暖空氣及/或一商用吹風機任一者來弄乾❹另 -10- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐）
装 訂
k- 557560
外’該日日圓可使用壓縮空氣或_例如氮氣之氣禮來弄乾。 該乾燥時間可從數秒變化至數分鐘。然而，最好，該晶圓 不要曝露於％繞2氣中持太長時間，因那個將會使該銅 片氧化。 一旦該晶圓不夠乾燥來進行封裝，該晶圓係在步驟16真 $包裝i真空包裝可使用_般已知之商用真空包裝設備 來執行。最好，該晶圓係包裝於一由一不起作用材料構成 之防震容器中。 當該晶圓係備好用於封裝時，該晶圓從該容器中拆裝且 可開始該封裝處理。在該封裝處理中，不是球形焊接就是 楔形焊接被執行。進一步，如那些熟知此項技術之人士所 了解的，若聚合材料被用於晶片黏接，該聚合物應於一鈍 氣中作處理以防止氧化。 現在參考至囷2,顯示一用以製備一具有許多積體電路 形成於其上之半導體晶圓之第二方法，該積禮電路具有由· 銅組成之墊片。類似該第一具體實施例，該第二具體實施 例最好在該晶圓上之晶片已測試後執行。 更特別地，在測試後，該晶圓係在步驟2〇以一酸溶液清 潔並接著在步驟22以水清洗。在步驟20中清潔該晶圓最好 係在室溫或上升溫度將該晶圓浸入或埋入一酸性浴盆中。 該晶圓最好係浸入該酸性浴盆約2至20秒，且，約10秒更好 。最好，該酸溶液不是h2s〇4就是ηνο3，然而，例如磷酸、 過氧化氫、氩氟酸及鹽酸之其它酸也可使用，這些係商用 且常用於半導體製造處理中《該水洗步驟22最好係使用解 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
k 557560 A7 _ ___B7 五、發明説明（8 ) 離子水在約21°C執行約2分鐘。 在該晶圓於步驟22清洗後，一抗氧化劑活化劑在步騾24 施用至該銅表面。可使用任何用於該半導體及引線框製造 之商用抗氧化劑。取好玄晶圓被浸入或埋入一盆抗氧化 劑活化劑中。然而，該活化劑可以例如噴霧之其它已知方 式來施用。 從該抗氧化劑浴盆移除該晶圓後，該晶圓係以水清洗並 弄乾。最好，該晶圓係使用解離子水清洗並接著弄乾。該 晶圓可利用環繞或暖空氣任一者來弄乾。又，該晶圓可使 用一商用吹風機來弄乾。 最後，步驟16被執行，其中該已弄乾晶圓係真空包裝於 一最好是防震且由不起作用材料構成之容器中。 現在參考至圖3中，顯示一用以製備一具有許多積體電 路形成於其上之半導體晶圓之第三方法，該積體電路具有 由銅組成之塾片。類似該第一及第二具體實施例，該第三 具體實施例最好在該晶圓上之晶片已測試後執行。 更特別地，在測試後，該氧化物係在步驟3〇自該晶圓中 移除。該氧化物可利用執行圖1所示之鹼性浴（步驟1 〇)、酸 中和（步驟12)及弄乾（步驟14)或執行圖2所示之酸性浴（步 驟20)、水洗（步驟22)、抗氧化劑活化劑施用（步驟24)及水 洗並弄乾（步驟26)。然而，該氧化物移除步驟3〇可包括分 子或電漿清潔。 電漿清潔使用一高功率射頻（RF)源、微波或直流電以轉 換氣體成為電漿。該高速氣體離子轟擊該焊接表面（也就是 -12- « ' — - .............. " .....__— ' 丨 一 本紙張又度適用中國國家搮準(CNS) A4規格(21〇x 297公*)
装 訂
557560 A7 _____B7 _ 五、發明説明（9 ) ，該銅塾片）及以物性或化性裂開該污染物分子來清除該焊 接表面之污染物。電漿清潔半導體及引線框係那些熟知此 項技術之人士所了解且用以執行這類電漿清潔之機器係商 用的。然而，本電漿清潔技術不足以自銅中移除氧化物。 在傳統電漿清潔中，該離子化氣體係氧、氬、氮，8〇% Ar + 20% 〇2或80% 〇2 + 20% Ar。另外，〇2/n2電漿也被使用。該 發明人已決定這些氣體及氣體之結合不夠清潔該銅塾片。 如此’根據本發明，該電漿清潔步驟係使用一約5-1〇%氫及 約90-95%氬之結合來執行。從經驗中得知，使用氫氣須在 一超低真空壓力下執行以提供該清潔離子一較長平均自由 路徑來到達被清潔表面是已決定的。也就是，該電漿清潔 最好係在一介於約5至20毫托耳間之超低壓力下利用約 800-1000毫瓦之微波功率來執行。 一旦該氧化物已自該晶圓中移除，步驟32，一例如鋁或 其它有機/無機塗佈之薄層氧化物純性材料被施用，最好賤, 鍍於該銅整片上。又稱為部分真空蒸鍍之濺鍍/PECvj)(電漿 促進化學氣相沉積）係一發生於一包含一例如一本例中最 好為銘之硬厚片之薄膜材料之目標物之真空室及該晶圓之 物性處理。氬氣被引進該室内並離子化為一正電荷。該帶 正電荷氬原子加速擊向該鋁，擊出該鋁原子。該擊出之銘 原子係沉積至包含該銅墊片表面之晶圓表面上。濺鍍在該 銅塾片上形成一均勻厚度之鋁。根據本發明，該濺鍍係只 被執行約2-3秒》 如習知中已知的以鋁覆蓋銅墊片以防止氧化，這類傳統 -13- 本紙張尺度適用中國國家樣準(CNS) Α4規格(210 X 297公釐) 557560 A7 _____B7__ 五、發明説明（10 ) 銘外套典型地係在10-20仟埃厚左右。反之，本發明使用濺 鍍/PECVD來提供一鋁皮或最好具有一約1-5毫微米厚度之 其它無機/有機氧化鈍性/PECVD材料。 最後，如前二具體實施例所述，步驟16被執行。也就是 ’該已弄乾晶圓係真空包裝於一最好由不起作用材料構成 之防震容器中。 前述圖1 -3所示方法係指向清潔一形成於一矽晶圓上之 積體電路之銅墊片及真空包裝該晶圓致使該銅墊片在打線 前不會氧化。據此，更穩定接線係使用執行上述方法之晶 圓來形成。 現在參考至圖6，一類似上述圖4所示之傳統方法以組合 半導體之方法被顯示。然而，如前述，銅墊片非常容易氧 化’因此為了提供更穩定接線，在組合期間應更小心。又 ’該發明人決定在該晶片自該晶圓（步驟40)被切割及焊接 至該晶片黏附墊片（步驟42)後並在打線（步驟44)前執行電> 漿清潔（步驟60)將會擁有更穩定的接線。 如參考囷3之上述，該電漿清潔步驟係使用一約5-1〇%氫 及約90-95%氬結合來執行。進一步，該電漿清潔最好係在 一介於約5至20毫托耳間之超低真空壓力以一約8〇〇_1〇〇〇 毫瓦之微波功率來執行。 在該晶片被清潔後，該接線步驟44被執行，接著步驟46 為該傳統步驟之UVO清潔及步驟48密封或塑模。 如同顯而易見的，本發明提供用以製備具有含銅墊片之 晶片之晶圓之方法致使當在該晶圓上之晶片備好封裝時， -14- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐） 557560 A7 B7 五、 發明説明（11 ) 該銅墊片具有較少氧化並因此該墊片之打線產生更穩定的 焊接。本發明又提供一用以在該晶片封裝處理期間製備一 具有含銅墊片之晶片之晶圓以減少該銅墊片上之氧化致使 該墊片之打線產生更穩定焊接之方法。如所了解的，本發 明係指向製備打線用之銅墊片。本發明不限於使用銅線來 打線，例如金或鋁之其它接線也可使用。進一步，雖然本 發明已使用球焊接來執行，它係不限於球狀焊接，也可以 楔狀焊接來實施。 本發明之較佳具體實施例說明已基於顯示及說明目的 來呈現，而不是要耗盡或限制本發明為所揭示之形式。那 些熟知此項技術之人士所了解其改變可產生於上述具體實 施例而不偏離其廣義發明觀點。因此，了解到本發明不限 於所揭示之特定具體實施例，並涵蓋如附上申請專利範圍 所定義之本發明精神及範圍内之修改。
裝 訂
k -15· 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公爱)

Claims (1)

  1. ABCD 55756%〇911〇438〇號專利申請案浪7· 中文申請專利範圍替換本(92年7月） 申請專利範圍 裡用以製備一具有許多積體電路形成於其上之半導 體晶圓之方法，該積體電路具有由銅組成之墊片，該方 法包括下列步驟： =由-酸性溶液清潔該晶圓及以水清洗該酸性溶液 m潔過<晶圓，以自該銅墊片中移除氧化物；及 真空包裝該晶圓。 2. =請專利範圍第!項之方法，其中該真空包裝步驟包 括真芝包裝該晶圓於一防震容器中。 3·:申請專利範圍第”員之方法，其中清潔步驟包括將該 日印圓浸至一h2so4溶液中。 其中清潔步驟包括將; 進一步包括該步驟為; 4·如申請專利範圍第1項之方法 晶圓浸至一hno3溶液中。 5·如申請專利範圍第丨項之方法 用一抗氧化劑活化劑至該銅墊片表面。 6. 如申請專利範圍第5項之方法，進—步包括該步驟為在 用孩抗氧化劑活化劑後以水清洗該晶圓及弄乾該水 洗過之晶圓。 7. 如申請專利範圍第!項之方法，進—步包括該步驟為形 一非常薄鈍化層於該銅墊片表面上。 8. 如申請專利範”7項之方法，其中該形成—純化層之 驟包括濺鍍一鈍化材料於該銅墊片表面上。 9·如申請專利範圍第8項之方法，其中該濺鍍鈍化層係約 U亳微米厚。 10·如申請專利範圍第9項之方法，其中該純化材料包括链 本紙張尺度適樣準(CNS) M規格ϋ297公釐) 557560 A8 B8 C8 D8 申請專利範圍 踢種用以製備一具有許多積體電路形成於其上之半導 且曰口圓之方法，該積體電路具有由銅組成之墊片，該方 法包括下列步驟： 、藉由電漿清潔該銅墊片以自該銅墊片移除氧化物;形 成一非常薄鈍化層於該銅墊片表面上；以及真空包裝該 晶圓。 12·如申請專利範圍第η項之方法，其中該電漿清潔係使用 約5-10%氫及約9(μ95〇/()氬來執行。 13. 如申請專利範圍第㈣之方法，其中該電漿清潔係在一 介於約5至20毫托耳間之超低壓力下執行。 14. 如申請專利範圍第13項之方法，其中該電漿清潔係使用 一功率約為800-1 000毫瓦來執行。 15. —種用以製備一具有許多積體電路形成於其上之半導 體晶圓之方法，該積體電路具有由銅組成之墊片，該方 法包括下列步驟： 經由電漿清潔該銅整片以自該銅#片移除氧化物；以 及真空包裝該晶圓。 々申叫專利範圍第15項《方法，其中該電衆清潔係使用 約5-10%氫及約9〇·95。/。氬來執行。 17.-種用以製備一具有許多積體電路形成於其上之半導 體晶圓之方法’該積體電路具有由銅組成之墊片，該方 法包括下列步驟： 以一酸性溶液清潔該晶圓； 以水清洗該酸清潔過之晶圓； -2 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 裝 訂 557560
    施用一柷氧化劑活化劑至該銅塾片表面； 在應用該抗氧化劑活化劑後以水清洗該晶圓； 弄乾該水清洗過之晶圓；及 真空包裝該晶圓於一防震容器中。 如申請專利範圍第17項之方法，其中清潔步驟包括將晶 圓浸至一 h2so4溶液中。 19.如申請專利範圍第17項之方法’其中清潔步驟包括將該 晶圓浸至一 HN 0 3溶液中。 20·—種用以製備一具有許多積體電路形成於其上之半導 體晶圓之方法，該積體電路具有由鋼組成之墊片，該方 法包括下列步驟： 使用約5-10%氫及約90-95%氬來電漿清潔該銅墊片； 在該銅墊片之一表面上濺鍍一非常薄層之鈍化材料 ，該鈍化層具有一約1-5毫微米厚度；及 真空包裝該晶圓於一防震容器中。 21·—種以一銅線電性連接一積體電路之一銅墊片與一引 線框之一墊片之方法，包括下列步驟： 使用約5-10%氫及約90-95%氬來電漿清潔該銅墊片； 及 打線該銅線至該清潔過之銅墊片及該引線框墊片。 22.如申請專利範圍第21項之方法，其中該電漿清潔係在_ 約為5至2 0毫托耳之超低壓力下執行。 23·如申請專利範圍第2 1項之方法，其中該電漿清潔係使用 一約為800-1000毫瓦之功率來執行。 -3- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
TW091104380A 2001-03-12 2002-03-08 Method of preparing copper metallization die for wirebonding TW557560B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/803,749 US6693020B2 (en) 2001-03-12 2001-03-12 Method of preparing copper metallization die for wirebonding

Publications (1)

Publication Number Publication Date
TW557560B true TW557560B (en) 2003-10-11

Family

ID=25187336

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091104380A TW557560B (en) 2001-03-12 2002-03-08 Method of preparing copper metallization die for wirebonding

Country Status (7)

Country Link
US (1) US6693020B2 (zh)
EP (1) EP1388167B1 (zh)
JP (1) JP4056394B2 (zh)
AU (1) AU2002242136A1 (zh)
DE (1) DE60214159T2 (zh)
TW (1) TW557560B (zh)
WO (1) WO2002073687A2 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720204B2 (en) * 2002-04-11 2004-04-13 Chartered Semiconductor Manufacturing Ltd. Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding
WO2004059708A2 (en) * 2002-12-20 2004-07-15 Agere Systems Inc. Structure and method for bonding to copper interconnect structures
MY134318A (en) * 2003-04-02 2007-12-31 Freescale Semiconductor Inc Integrated circuit die having a copper contact and method therefor
DE10320472A1 (de) * 2003-05-08 2004-12-02 Kolektor D.O.O. Plasmabehandlung zur Reinigung von Kupfer oder Nickel
JP4036834B2 (ja) * 2004-01-21 2008-01-23 松下電器産業株式会社 マイクロポンプ用逆止弁の製造方法
US7186652B2 (en) * 2004-05-05 2007-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for preventing Cu contamination and oxidation in semiconductor device manufacturing
JP4035733B2 (ja) * 2005-01-19 2008-01-23 セイコーエプソン株式会社 半導体装置の製造方法及び電気的接続部の処理方法
DE102005019160B4 (de) * 2005-04-25 2007-04-05 Emag Holding Gmbh Verfahren zur Herstellung von Kugelnaben für Gleichlaufgelenke
DE102006044691B4 (de) * 2006-09-22 2012-06-21 Infineon Technologies Ag Verfahren zum Herstellen einer Anschlussleitstruktur eines Bauelements
TWI370515B (en) 2006-09-29 2012-08-11 Megica Corp Circuit component
US8414534B2 (en) * 2006-11-09 2013-04-09 Abbott Medical Optics Inc. Holding tank devices, systems, and methods for surgical fluidics cassette
TWI368286B (en) 2007-08-27 2012-07-11 Megica Corp Chip assembly
US20100052174A1 (en) * 2008-08-27 2010-03-04 Agere Systems Inc. Copper pad for copper wire bonding
SG194523A1 (en) * 2011-04-25 2013-12-30 Air Prod & Chem Cleaning lead-frames to improve wirebonding process
CN107845568A (zh) * 2017-10-31 2018-03-27 浙江华越芯装电子股份有限公司 一种集成电路封装键合前等离子清洗方法及装置
CN113488399B (zh) 2021-06-15 2021-12-21 广东工业大学 一种超细节距半导体互连结构及其成型方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764244A (en) * 1985-06-11 1988-08-16 The Foxboro Company Resonant sensor and method of making same
JPH02101156A (ja) 1988-10-05 1990-04-12 Fujikura Ltd 真空蒸着用銅基材の製造方法
US5246782A (en) * 1990-12-10 1993-09-21 The Dow Chemical Company Laminates of polymers having perfluorocyclobutane rings and polymers containing perfluorocyclobutane rings
JP3247211B2 (ja) 1993-08-02 2002-01-15 富士通株式会社 配線用銅膜表面の酸化銅除去方法
KR100295429B1 (ko) 1997-12-29 2001-10-24 윤종용 웨이퍼의포장방법
US6355571B1 (en) * 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US6358847B1 (en) 1999-03-31 2002-03-19 Lam Research Corporation Method for enabling conventional wire bonding to copper-based bond pad features
US6440854B1 (en) * 2001-02-02 2002-08-27 Novellus Systems, Inc. Anti-agglomeration of copper seed layers in integrated circuit metalization

Also Published As

Publication number Publication date
EP1388167A2 (en) 2004-02-11
JP2004527114A (ja) 2004-09-02
WO2002073687A2 (en) 2002-09-19
US6693020B2 (en) 2004-02-17
DE60214159D1 (de) 2006-10-05
AU2002242136A1 (en) 2002-09-24
EP1388167B1 (en) 2006-08-23
US20020127825A1 (en) 2002-09-12
DE60214159T2 (de) 2006-12-14
WO2002073687A3 (en) 2003-11-13
JP4056394B2 (ja) 2008-03-05

Similar Documents

Publication Publication Date Title
TW557560B (en) Method of preparing copper metallization die for wirebonding
CN100524725C (zh) 半导体装置及其制造方法
US8956919B2 (en) Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof
US20040195696A1 (en) Integrated circuit die having a copper contact and method therefor
TW200403820A (en) A packaged semiconductor with coated leads and method therefore
JPH01100930A (ja) 半導体プラスチックパッケイジのための銅メッキリードフレーム取り扱い方法
US20220246557A1 (en) Package chip and method of manufacturing the same, rewiring package chip and method of manufacturing the same
TW561538B (en) Method of preventing tungsten plugs from corrosion
JPS59154054A (ja) ワイヤおよびそれを用いた半導体装置
CN1211838C (zh) 制作焊垫的方法
JP3543573B2 (ja) 電子部品の実装方法およびチップの実装方法
JPS62224048A (ja) ダイヤモンド膜製半導体基板の製造方法
CN102136451A (zh) 形成金属互连的方法
KR100545216B1 (ko) 반도체 소자의 패드 제조 방법
CN102239556A (zh) 自组装单层膜作为氧化物抑制剂的应用
KR930007519B1 (ko) 전기장치의 패키지(package) 방법
CN115966456A (zh) 晶圆焊垫结构的清洗方法
JP2003318346A (ja) 樹脂封止型半導体装置およびその製造方法
KR100588892B1 (ko) 반도체 소자의 패드 산화 방지방법
Koh et al. A Study on the Effect of Post Metal Etching Polymer Strip Process on Via Resistance
JP3957536B2 (ja) エッチング方法
TW442865B (en) Metal etching process of integrated circuit
JP2674144B2 (ja) 半導体装置の製造方法
JP2003197594A (ja) ウェーハ及びウェーハを製造する方法
TW546774B (en) Method of forming a self-aligning pad

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees