TW557387B - Thin film transistor array panels for liquid crystal displays and methods of manufacturing the same - Google Patents

Abstract

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the boundary area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

Description

557387 Ⅴ. Description of the invention (1) I Background of the invention (a) Field of the invention The present invention relates to a thin film electric crystal (TFT) panel for a liquid crystal display (LCD) and a method for manufacturing the same. (b) Description of related techniques-LCD (Liquid Crystal Display) is one of the most popular FPDs (Flat Panel Displays). The LCD has two panels and the panel has two electrodes for generating an electric field! And a liquid crystal layer interposed therebetween, The transmission rate of incident light is controlled by the electric field intensity applied to the liquid crystal layer.

In an extremely widely used LCD, an electrode for generating an electric field is provided on a two-sided panel, and one of the panels has a switch such as a thin film transistor. In general, a thin film transistor panel array is made by photolithography using a plurality of photomasks, and uses five or six light lithographic printing steps. Due to the high cost of the light lithographic printing process, it is necessary to reduce the number of light lithographic printing steps. Even if it is recommended to use only four light lithographic printing steps, the methods are not easy to achieve. A conventional method for manufacturing a thin film transistor array panel using four lithographic printing steps will now be described.

First, an aluminum or aluminum alloy gate circuit is formed on a substrate by using a first photomask, and a gate insulation layer, an amorphous stone layer, an η + amorphous stone layer, and a metal layer Sequentially stacked, the metal layer, η + amorphous silicon layer, and amorphous silicon layer are patterned using a second photomask. At this time, the gate pads of the gate line are covered only by the gate insulating layer.

cover. An I TO (indium tin oxide) layer is stacked and patterned using a third mask I

I, remove the I τ 〇 layer part on the brake pad at this time, when the metal layer and the lower | I

Page 6 | 557387 V. Description of the Invention (2) After the amorphous stone layer is patterned using the patterned IT 0 layer as a touch mask, a passivation layer is deposited on the completed thin film transistor array. The panel is obtained by patterning the passivation layer and the gate insulation layer below through the fourth photomask, and removing a portion of the passivation layer and the gate insulation layer on the gate pad. As a result, brake pads made of aluminum or aluminum alloy are presented in the conventional manufacturing method using four photomasks, but aluminum and aluminum alloys cannot withstand physical and chemical stimuli and are easily damaged, although they have low resistance Advantages. To compensate for this, the brake wire is made of a multilayer structure or made of a material resistant to physical and chemical stimuli, but the former complicates the process and the latter has a problem of extremely high material resistance. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel manufacturing method of a thin film transistor array panel for LCDs to reduce the number of photomasks. Another object of the present invention is to protect the gate blocks of LCDs. Another object of the present invention is to prevent current leakage of LCDs. According to the present invention, the above and other objectives are achieved by patterning the gate insulating layer, the semiconductor layer, the ohmic contact layer, and the data conductor layer at a time. According to the present invention, a first light lithography process is used to form a gate circuit on an insulating substrate; a second light lithography process is used to form a gate insulation layer, a semiconductor layer, and an ohm. The four layers of the contact layer and a data conductor layer are on the substrate and the gate circuit; a third light lithography process is used to form a conductive pattern on the data conductor layer; the data conductor layer not covered by the conductive pattern is partially etched Divide by to form a data line; divide the data

Page 7 557387 V. Description of the invention (3)-'------------------ The ohmic contact layer not covered by the line is removed; The layer pattern is printed on the conductive pattern using the younger brother's four-light lithograph. At this time, the gate line includes a number of gates extending after a first ancient A + universal joint, gates of the Aozha line branch, and a gate connected to each # θ,, U are κ. Thin and light gate block for external thunder policy to pick up the scanning signal; the quadruple layer has 笫 1, ^ ^ μ are contact holes to expose each block; and the passivation layer has The two contact holes to expose the first line include a plurality of n contact holes extending in the -S-direction. The gate electrode, and a gate pad connected to one end of each gate line and designated as a branch line branch line from the outside; the quadruple layer has a first contact hole to receive the scanning signal block; and the purification layer has a second contact hole to The first exposure, Zenglu, includes a plurality of gate lines extending in a first direction, & Weiji, and gate pads connected to one end of each gate line and serving as a branch line branch line from an external power source; the data lines include Extending in the second direction 'Slightly receiving scanning signals include the first conductive pattern, which is through the first contact], α, brake pad; conductive pattern. U ^ ^ ^ m): 2 nm ™. Holes are connected by ^ In the brake pad electric pattern. Multiple data lines of the gate line to the gate line, data pads connected to one end of each data line with intersecting image signals, connected to the data line and adjacent to each other 1 ° 卩 The circuit receives a shadow related to the gate and is located on the opposite side of the source Zhiqu ·, the source electrode and the first conductive pattern are formed on the data line and the child selection pattern. The pattern includes the second conductive pattern and is formed on the drain electrode and the pixel mallet: and the lean material block. Above, on the second conductive pattern and formed on the pixel electrode connected by the gate line and the data electrode, '' HI -ip-> Γ- and the purification layer have an opening to expose the pixel electrode and the first region; A first conductive pattern on the pad. The passivation layer has a Γ opening to expose the semiconductor layer portion between the current two neighboring data lines, and a hole that is opened to expose the current phase and the exposed portion to facilitate separation of the 7th line below the second data line. "Semiconductor"-the step of the body layer. image

Page 8 557387 V. Description of the invention (4) Plain electrode overlapped Conductor layer part is formed on the gate pad, and the fourth opening is exposed on the substrate, the road and the pixel electrode part. The passivation space and the adjacent image pass through the groove. On the two main lines, there is a recessed conductive pattern quadruple layer. The data conductor degree depends on the position. The thinnest points of the gate pad and the data erosion layer are formed. The second part is the first part of the gate line which is more than the second part, and is interposed between the pixel electrode and the gate line, which is isolated from other parts of the semiconductor layer. The first part is between the half of the gate and the data pad. The first part of the insulating layer of the gate is exposed, and the part of the semiconductor layer located at the gate 2 is removed to facilitate the separation of the second semiconductor layer of the gate pad. The passivation layer covers the edge of the pixel electrode and the edge of the data pixel. A quadruple layer is formed on the storage circuit L overlapping the pixel electrode, and a semiconductor layer partially interposed between the two layers is isolated from the semiconductor layer: The layer has a groove to expose the first conductive layer. Band: "Near other levels, and further steps include the removal of surnames. The open line includes two main lines and a part of the connecting line ii and 象 pixel poles overlapping the gate line. One end of the source 41 handle is located in the concave portion. The formation steps include the following two? Tin oxide. Overlayer · Temperature + Sensitive · Coated with a photoresist layer ^ 4 5 * "and development will make the photoresist layer a thick, cross-linked pattern · 伞 儿 Umbrella > wp Riyishan's, π > t first anti-surname layer pattern etched quadruple layer to 20% of the material line and between the source and drain lines p ^ ^ ^ part, < 、 · 彖 层 # / Knife. The first part is the photoresistance to j: ^ ^ formed on the brake pad, the second part is the thickest part of the household, ^ and the data line connected to the pole, and the g, divided and thin In the second part, it is formed in. Especially the exposure of the resist layer is performed by using a photomask.

557387 V. Description of the invention (5) The hood includes at least three parts and its transmission ratio is removed using the second light lithography process: @。 One part of the interlayer insulation layer: conductive = including contact between the intermediary ends: the end of the current line is formed in the passivation layer. The present invention provides a thin film transistor array surface with a light lithography process. The panel includes: a gate line formed in a-insulation, the thin film transistor array =-a plurality of gate lines in the-direction, connected to the gate: the material; and Including a gate pad block extending one end of the closed wire;-gate insulation layer, and some gate electrodes, and connected to the block and formed in an array shape on the gate line and the United States, there are contact holes to expose the gate pad on the open insulation layer ; A data line, upper J = semiconductor layer, including extending in a second direction to intersect on the I semiconductor layer, and the source of the envelope, separated from the data line, and] ::, data line, adjacent The drain S on the opposite side of the pole, and * are connected to the source, and are thick. They are located in the source conductive pattern, including the source and the data. They are formed on the drain and the pads; The second pattern, the first pattern of ν and W, the first pattern, the pattern, and the third pattern of the image 2 connected to the data block on the data block, the semiconductor pattern, and the base: pole; And a passivation layer, opened) formed in the pixel electrode, the second opening to expose the second, the first opening The gate insulation type is the exposed layer, the third opening is located on the gate pad, and the material line is formed between the gate and the material line. At this time, the data line is only formed and the fourth opening is used to expose the conductor layer of the third figure to form the entire gate insulation. Between the electric pattern on the layer and the semiconductor layer, except for half, and the portion below the two adjacent data lines but below the second opening. At this time, the thin film transistor array panel: the conductor layer portions are separated from each other. A violation step includes the formation of a contact layer in 557387 V. Description of the invention (6) Between the semiconductor layer and the data line, and the reduction of the semiconductor layer and data The fourth pattern:,: Λ I: contact circuit. Conductive pattern The third opening reveals the fourth pattern: Contact: Connected to the gate pad, and the gate pixel electrodes sandwiched between the pixel electrode and the gate line are superimposed on the adjacent gate line and divided. The gate insulation layer includes a semiconductor layer that is isolated between other blocks, and the purification layer has :: formed in two pads and two data pads, and Fengwu openings to expose the insulating layer The first knife and burdock body layer was not formed on the flint stone. Ding + | Prime pole edge. The first opening is under the warm ancestor and younger brother. The passivation layer cover image = step including a storage line formed on the substrate 12 = surface layer? Cover, which is lost between the storage circuit and the pixel electrode 2 :: The layer part is isolated from the other parts. The conductive pattern is a method for manufacturing a thin-film transistor array panel containing fj 2 and oxidized by indium tin oxide. It is known that: a first-lithographic printing process is used to form a gate circuit including a gate block; A first insulating layer, a semiconducting layer, a ohmic contact layer, and a metal layer are stacked on the gate line; a second lithography is used to form a metal layer pattern and an ohmic contact layer. A pattern of a semiconductor layer and a pattern of a first insulation layer. The layers have an array shape and overlap the gate line, except for the gate pad; a transparent layer is used, and a third light lithography is used. Process to form a transparent conductor pattern, including a pixel pole, a plurality of redundant data lines, a redundant source electrode, and a redundancy; and a pole, several data pads, and a redundant gate block; Part of the metal layer covered by the pattern and the ohmic contact layer below it is removed; 557387 is deposited V. Description of the invention (7) A second insulating layer; forming a passivation layer pattern, which has a hole opening pad and a data pad Blocks, pixel poles, and adjacent to each other * The body layer portion; the semiconductor layer portion exposed through the opening is etched away. At this time, the manufacturing method may further include the semiconductor layer. After the step, the first step below the semiconductor exposed portion is: [Etching step] According to the present invention, a method for manufacturing a thin film transistor: a first light lithography process is used to form a gate circuit including the following step pads; A first insulating layer, half of the gate line and the contact layer, and a metal layer on the gate line; the metal layer, the second, the first, the semiconductor layer, and the first insulating layer are patterned into a shape: in contact Pattern, one ohm contact layer pattern and one semiconductor layer pattern, separated into two pieces on the master layer pattern line, and a first insulation layer pattern overlay = on the gate except the gate pad; a transparent one is deposited The conductor layer; using the second gate line, with: Γ transparent conductor layer pattern; except for the metal layer part and the ohmic contact layer that are not covered by the transparent second light guide stone / Figure 1, the plural data blocks , Source and drain, and oboe underneath—including line ; Accumulation-the second insulation layer; and the use of-the fourth 3 = type of data formation-passivation layer pattern, which has at least contact = Cheng Yi pad blocks. The second light lithographic printing process includes the following sub-steps. Applying an anti-neodymium layer on the metal layer; using exposure and development in a 22-layer pattern, which has at least three parts and whose thicknesses are different from each other; 1 = erosion layer is removed Metal layer, ohmic contact layer, semiconductor layer and first insulation

O: \ 58 \ 58736.ptd 557387 5. Description of the invention (8) Layer to remove the first part, gp 4 = · n along the thinnest part of the third ablation layer pattern thicker than the first part, and layers, semiconductors Layer and the second insect-removing metal layer, the ohmic contact contact layer and the semiconductor layer below; said = to = except for the J-type layer and the two layers of ohmic protection, 'second part ;: The exposure is performed using a photomask, which is the second. The photoresist layers are different from each other. The right side of the mask is at least two, and the transmission rate is at least two. The transmission rates are different from each other. Material = long slits of device resolution, or use the pass to form the spacer and a formation. The photomask is divided into a first photomask. The transfer rate is different from the first: hi mask to form other places, and the first photomask is located on the brake pad. The first part of the photoresist layer pattern is the photoresist layer pattern. This step includes the following sub-steps: it is for the layer, the ohmic connection, and the photoresist is removed by the stopper # —— 邰 / 刀As the third part of the etching layer, the semiconductor layer and the metal layer under the first type, and the second part of the ohmic contact layer using the ashing process to remove the photo-induced anti-money as the third part of the metal layer; The photoresistance layer and the underlying semiconductor layer are exposed to metal, the ohmic contact layer 4: the bulk layer is made of amorphous debris. The second insulating layer is made of a light-defining material according to the present invention. A rhombic γ + · includes the following steps: forming a gate circuit, and a manufacturing method of a transistor array panel. Including a plurality of gate lines and connected to the gate, the open line is generally located in the base area of the display area and the gate pads are generally located in the peripheral area; 557387 V. Description of the invention (9) A gate insulation layer, a semiconductor are sequentially deposited Layer, an ohmic contact layer, and a conductor layer on the gate line; coating a photoresist layer on the metal layer; using exposure and development to form a photoresist layer pattern, the thickness of which varies depending on the location ; Using a light lithographic printing process to make a pattern of the metal layer, the ohmic contact layer, the semiconductor layer, and the gate insulation layer at a time to form a metal layer pattern, a first ohmic contact layer pattern, and a semiconductor layer pattern, And expose a lumped block; accumulate a conductor layer; use a light lithographic printing process to form a Muna Moonton layer pattern, which includes a plurality of pixel electrodes to cover a part of the metal layer, and a plurality of conductor layer patterns To cover other parts of gold It belongs to the gate and is located on the opposite side of the prime electrode in relation to the gate electrode; the layer layer and the ohmic contact layer below the pixel electrode and the separated conductor layer pattern are removed to form a -data line, spoon < I- number data line , The data pad, the source and the drain, and one of the following: a pattern of the complex contact layer; and a passivation layer is formed. — Di Erohm, at this time, once the metal layer of the other parts of the light is exposed, the anti-fogging method is applied to the anti-fogging method. On the money layer and gold, the pattern is now partly layered, and the thin ohmic photo-metal layer is exposed to remove the ohmic contact ohmic contact pads, and the delamination pattern is on the belonging layer. The step includes exposing the European contact layer anti-name layer Part of the contact layer, layer, and half of the bottom are only metal layers. The ohmic contact includes the following contact and semiconductor to expose the ohmic contact of the semiconductor conductor layer. The thickness is thicker than the display area. ] Layer, semiconductor layer and gate turn-off steps: remove the surrounding area by using an etching method that can remove the king 3 at one time, remove the metal layer under the a; remove the contact layer; and use a layer and Etching of gate insulation layer and gate insulation layer to expose exposure of Zhouma contact layer and semiconductor layer |

557387 V. Description of invention (ίο) Points. The substrate has openings to expose the pixel electrodes. The conductor layer pattern includes a plurality of redundant, shell material lines to cover data lines, redundant data pads to cover data pads, and brake pads to cover brake pads. The passivation layer has openings to expose redundant gates ^ ί redundant data pads. It further includes the steps of forming a common circuit. ^ 2. The circuit includes a plurality of common electrodes, which can generate electricity on the substrate with the pixel electrode as follows: a thin film transistor array panel manufacturing method is an odd circuit: Λ includes a plurality of gates, wires, and gates connected to the intermediate line. A common circuit including a plurality of common electrodes is formed on an insulating substrate to form a gate. The insulating layer pattern is simplified by frost, green, and semiconductor patterns. Gate π renews the μ common line; forms ~ bulk layer pattern bu · τ #bar, said above, forms an ohmic contact layer pattern on the semi-conductive complex data green table; data lines on the ohmic contact layer pattern, including forming 1 ; ΐϊ sound in: the source of the material line, separated from the source of the pole; outside; and the formation of the complex 彳 tϋ, a part of the drain electrode in addition to the electric field; its Hi: connected to the pole and the common electrode type Light; the separation between μ and the drain is made by using a photoresist ® with the master < lithography first-especially the soft resist layer part is located; privately, and the photoresist pattern includes a first The second brother's score is thicker than the first sword's first brother ~ This , Shen depending μ formed. Closed circuit: The contact layer and semiconductor layer use a single layer of a light circuit, a semiconductor pattern, and an ohmic connection. The steps for forming a mask include the following + cattle contact layer pattern and data. Green layer, ohm Contact @ step product gate insulation layer, semi-training-Ma contact layer and metal layer; coated with a light Niu Ling body resist layer on the metal layer. 557387 V. Description of the invention (11) ~-through a photomask to expose Photoresist layer; the photoresist layer is led to the pattern of the anti-silver layer, the second part of which is located on the light part of the data line: the square metal layer, the ohmic contact layer and the semiconductive insect, The second layer of the metal layer and the lower ohmic contact layer, and the second === some thicknesses to form a data line, an ohmic contact layer pattern, and a semiconductor pattern; and removing a photoresist layer pattern. The steps of forming the data line, the Olympus 61, and the semiconductor pattern include the following sub-steps:

/ σ One part dry-etches the semiconductor layer under the ohmic contact layer under the third part to expose the gate insulating layer in the third part I and the metal layer under the first part along the completed semiconductor pattern; and the etching; The pattern of the data line and the ohmic contact layer is completed by excluding the metal layer portion below the first portion and the ohmic contact layer below. Fig. 1 is a plan view of a substrate of a substrate which has been segmented to make an example of the present invention for an LCD. FIG. 2 is a configuration diagram of a TFT panel for an LCD according to an example of the present invention.

FIG. 3 is a layout diagram of a TFT panel for an LCD according to the first example of the present invention, and is an enlarged view of a part mainly including the pixels and the pads shown in FIG. 2. 4 and 5 are cross-sectional views taken along lines iIV_IV and v_v in FIG. 3, respectively. FIG. 6A is a configuration diagram of an iTFT panel in the first manufacturing step of the first example of the present invention. 6B and 6C are cross-sectional views taken along lines VIB-VIB and VIC-VIC 'of FIG. 6A, respectively.

Page 16 557387 V. Description of the invention (12) FIG. 7A is a TFT panel configuration diagram in the subsequent manufacturing steps of FIGS. 6A to 6C. Figs. 7B and 7C are sectional views taken along line VI IB-VI IB 'and VI IC-VI 1C' of Fig. 7A, respectively. FIG. 8A is a TFT panel configuration diagram in the subsequent manufacturing steps of FIGS. 7A to 7C. 8B and 8C are cross-sectional views taken along lines VI I IB-VI I IB ′ and VII IC-VI I 1C, in FIG. 8A, respectively. FIG. 9 is a layout diagram of a TFT panel for an LCD according to the second example of the present invention, and is an enlarged view of a part mainly including the pixels and the pads shown in FIG. 2. Figs. 10 and 11 are sectional views taken along lines X-X 'and XI-XI in Fig. 9, respectively. FIG. 1 A is a layout diagram of an iTF τ panel in the first manufacturing step of the second example of the present invention. FIG. 128 is a cross-sectional view taken along line 118-1118 of FIG. 12. FIG. 13A is a configuration diagram of the rFT panel in the subsequent manufacturing steps of FIGS. 12A and 12B. 13B is a cross-sectional view taken along the line XIiiB-XIIIB in FIG. 13A. FIG. 14 is a layout diagram of a TFT panel for an LCD according to a third example of the present invention, and is an enlarged view of a part mainly including the pixels and pads shown in FIG. 2. Fig. 15 is a sectional view taken along the line XV-XV 'in Fig. 14. FIG. 16 is a layout diagram of a TFt panel for a fourth example of the present invention for an LCD, and is an enlarged view of a portion mainly including the pixels and pads shown in FIG. 2. Figures 17 and 1.8 are cross-sectional views taken along the lines} 6 iXVI J — χν j j, and χν j j j — χν j π, respectively. FIG. 19 is a layout diagram of a TFT panel for an LCD according to a fifth example of the present invention, and is an enlarged view of a part mainly including the pixels and pads shown in FIG. 2.

Page 17 557387 V. Description of the invention (13) Figure 20 is a cross-sectional view taken along the line XX-XX of Figure 19. FIG. 21 is a configuration diagram of a TFT panel used in the sixth example of the present invention—LCI), and is an enlarged view of a part mainly including the pixels and the pads shown in FIG. 2. FIG. 22 is a cross-sectional view taken along the line XXI I-χχπ of FIG. 21. FIG. 2 A is a layout diagram of the first panel in the sixth manufacturing step of the sixth example of the present invention. * Fig. 23B is a cross-sectional view taken along the line XXI I IB-XXI ΠB 'in Fig. 23A. FIG. 24A is a TFT panel configuration diagram in the subsequent manufacturing steps of FIGS. 23A to 23B. Fig. 24B is a cross-sectional view taken along the line XXIVB-XXIVB 'in Fig. 24A. Figs. 25A, 25B, · 2 6A, 26B, and 27 are sectional views of the photomask used in the manufacturing steps shown in Figs. 2A to 24A, respectively. Fig. 28 is a cross-sectional view taken along the line XXIVB-XXIVB in Fig. 24A and in the subsequent manufacturing step of Fig. 24B. FIG. 29A is a TFT panel configuration diagram in a subsequent manufacturing step of FIG. 28. The figure is a cross-sectional view taken along the line XXIXB-XXIXB of FIG. 2ΘΑ. FIG. 30 is a configuration diagram of a TFT panel for an LCD according to a seventh example of the present invention. Figures 31 and 32 are sectional views taken along lines XXXI-XX χΓ and XXXI I-XXXI Γ in Figure 30, respectively. Fig. 3 A is a spring view of the configuration of the TF T panel in the first manufacturing step of the seventh example of the present invention. Figs. 33B and 33C are sectional views taken along lines XXXIIIB-XXXIIIB 'and XXXI I IC-XXX I I 1C' in Fig. 33A, respectively. FIG. 34A is a TFT panel configuration diagram in the subsequent manufacturing steps of FIGS. 33A to 33C. Figures 34B and 34C are taken along XXXIVB-XXXIVB 'and Figure 34A, respectively.

Page 18 557387 V. Description of the invention (14) Sectional drawing taken from the XXXIVC-XXXI VC ’line. FIG. 35A is a TFT panel configuration diagram in the subsequent manufacturing steps of FIGS. 34A to 34C. 35B and 35C are cross-sectional views taken along lines XXXVB-XXXVB 'and XXXVC-XXXVC' in FIG. 35A, respectively. FIG. 36 is a configuration diagram of a TFT panel for an LCD according to an eighth example of the present invention. 37 and 38 are cross-sectional views taken along lines XXXVI I-XXXVI I 'and XXXVI I I-XXXVII Γ in FIG. 36, respectively. Figure 3 9A is a TF T panel configuration diagram in the first manufacturing step of the ninth example of the present invention. Fig. 3 9B and 39C are sectional views taken along lines XXXIXB-XXXIXB 'and XXXIXC-XXXIXC' in Fig. 39A, respectively. 40A and 39A to 39C are TFT panel configuration diagrams in subsequent manufacturing steps. 40B and 40C are cross-sectional views taken along lines XLB-XLB 'and XLC-XLC' in FIG. 40A, respectively. FIG. 41A is a layout diagram of the TFT panel in the subsequent manufacturing steps of FIGS. 40A to 40C. 41B and 41C are cross-sectional views taken along lines XLIB-XLIB ′ and XLIC-XLIC, respectively, of FIG. 41A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to related drawings. The preferred embodiments of the present invention are disclosed in the drawings. However, the present invention can be implemented in many different ways and is not limited to the examples described in the text. Rather, it can be used to fully and completely explain the invention and: for the purpose of this technology to understand its scope. In the drawings, the thicknesses of the regions and regions have been enlarged for clarity. The same numbers in the figures refer to the same elements. It can be understood that when an element such as a layer, region or substrate is called

Page 19 557387 V. Description of the invention (is) When it is on another element, then this can be directly on another element or also on / intermediate the 7G element; otherwise, when an element is called direct On another element, there is no intervening element in between. A structure of a TFT array panel according to an embodiment of the present invention will now be described with reference to FIGS. As shown in FIG. 1, a plurality of panel regions are formed on an insulating plate. As shown in FIG. 1, four panel regions 110, 120, 130, and 14 are formed on a broken plate 10. When the panel is a TF T array panel The panel area 丨 丨 〇, 丨 2 〇, 1 3 〇, 140 includes display areas 111, 121, 131, 丨 41, and has a plurality of pixels and peripheral areas 11 2, 122, 1 32, 142, TFTs, The lines and pixel electrodes are repeatedly arranged in a matrix manner in the display areas m, 丨 2 11 3 丨, 141, and the pads to be connected to the external circuit and the electrostatic discharge protection circuit are provided in the peripheral areas 112, 122, 132, 142 in. In general, the panel area 110 ,! The components in 20, 13 and 14 are printed by light lithography using a double-feeder, which is an exposure equipment. The display area 111, 121, 131, 141 and the surrounding areas 112, 122, 132, and 142 are divided into sections using a step of% ', and one pR layer coated on the film passes through one or more photomasks and one section Exposure for a while. Subsequently, the $ pR layer is displayed, and the film under the PR layer is removed to form a thin film pattern. Once the LCD panel is completed, it is obtained by repeating the above drawing steps. FIG. 2 is a layout diagram of a τ ρ T array panel area, which is an example of the present invention shown in FIG. 1. FIG. As shown in FIG. 2, a plurality of TFTs, a plurality of pixel electrodes connected thereto, and a plurality of lines including the gate line 22 and the data line 62 are all formed in the display area, and

557387 Five 'Explanation of the invention (16) around a short-circuited bus 4 with a false phase. Connected to the gate line 22 and the data line 62, and one gate 64 is formed at the periphery and side. The gate block 24 and the data block row 5 of the short circuit bus 5 are connected to the ring eight I domain respectively, and the gate is short-circuited. The bus bar 4 and the data short-circuit bus head 6 are connected to each other, 4 idle lines 2 2 and all data lines 62, and static electricity is generated through a connecting component to make them all at the same potential, so as to avoid the device line 2 cutting the panel And electrical failure. The short-circuit busbars 4 and 5 will be divided by the contact holes shown in the cut. A number 7 indicates that it is formed in the insulating layer (not shown in the figure, the connector 6 is the face: 0 ', which is placed between the connector 6 and the short circuit. The # 4 & fT contact holes 7 of the busbars 4 and 5 are connected to the short-circuit busbars. Figure J is a TFT panel layout diagram of the present invention shown in Figure 2 ~ silly f-D, and is IV- IV, ^ VV, and the enlarged view of the block, and Figures 4 and 5 are cross-sectional views taken along the line V of Figure 3 bis. L! Gate wire made of electrical materials, such as Ming (ai) and aluminum , Turn (M, indium, thorium. W) alloy, chromium (Cr) and group (Ta), agricultural, Ming t 1 line on the insulating substrate 10 includes several; line 22 scans the signal by a plurality of brake pads " , And the road, the gate to the plural TFTs gate 26. The gate lines 22, 24, and 26 which are closed branch lines can be a -multi-layer structure and-* When the inter-lines 22, 24, 26 form a multi-layer structure, its '' :: Resistive material, and the other layer is made of the same material: (for example, or alloy) ... a silicon nitride (SiNx) gate insulation layer 30 is formed on the gate line 22, 24. Above 557387 V. Description of the invention (17) ~~ _ —-- and cover it. The interlayer insulating layer 30 has a net-like pattern. -Semiconductor patterns 42 and 47 made of semiconductor are formed on the gate insulating layer 30, the semiconductor pattern core, 47 and = 乂, that is, the plural first part 42 extends in the vertical direction and 祯 "f a knife, and the second part 47 and the second part 47 are separated and located between the two first parts 42 and adjacent to a branch block M. It extends on and is formed on the brake pad 24. 'An ohmic contact layer made of, for example, a large amount of doped 彳 # g, -55. Rr L heterotype non-Japanese silicon. 55, 56, 57 and 58 are formed on the semiconductor patterns 42, 47. . '::: Two materials such as molybdenum or molybdenum tungsten, chromium, aluminum or aluminum alloy and buttons 5: 56:?, 66, 67, 68 are formed on the ohmic contact layer pattern gas subpoles 6, 8 The material line 62, 64, 66, 67, 68 has a multi-layer shell material line 62, which includes a plurality of thin films, two sleeves, one thousand and ten, how many, and the source level 65 of film-seeking private crystals (TFTs), and Yandu: direction, the data pad 64 is connected to one end of the data line 62 and the image signal from # 6 ^^^ to # 料 线 62. The f material line also has a plurality of D's, which are located on the opposite side of the source 65 in relation to the gate electrode 22, and the first type 55, _7 is formed on the second portion 47 of the semiconductor layer. The ohmic contact layer patterns 62 5 7, 58 are formed between the semiconductor layer patterns 42, 47 and the data lines 64, 6, 66, 67, 68, and have the same characteristics as those of the data lines 62, M, 66, and 68. Configuration. 42. In another Europe, the gate insulation layer 30 on the gate pad 24, the semiconductor layer contact hole pattern 58 and the first isolated data conductor 68 all have plural numbers: Zancong exposes the gate pad 24. Complex Derivatives Made of Transparent Material $ ¥% Sexual Materials such as ITO (Indium Tin Oxide)

Page 22 557387 V. Description of the invention (18) The road of the pixel area from the electric pattern type 71, 72, 73, 7fi, the data line 62 ;; on the substrate 10. The conductive patterns 71,? Vm, 64, 66, 67, 68 and the first to fourth rounds 72, 73, 74, 75, 76, 77 include complex-patterns 72, 75. They are divided into :: :: 62 and the first on the data pad 64-72. The second pattern 71 = the part 75 on the source 65 and the other pixel 71 on the pixel. The middle part 76 is on the drain 66 and is formed on the second isolation. It is an extended and 22 storage capacitor. Secondly, to form a superimposed gate line to assist the data pad 6: and one; Qiu: 7 is formed on the data pad 64, and the pattern 73 is formed between the gate pads 1 and 24: 1. The ohmic contact and the fourth contact with the external circuit i are now: to assist the brake pad 75 to connect to the third pattern ?: contact. At this time, the brother-patterns 72, 74 and 74 and the one-fourth patterns 71, 73, and 76 are separated. In this example, the guide ::; pattern 73 can be omitted. -In a reflective LCD, V: No: the day is made of a transparent material ', but it is made of an opaque material. The third and fourth patterns of transparent conductors 73 and 8: To expose the pixel electrode η and to avoid one of the gate lines 22, f々tai = layer knife into a mouth ^ knife 42, 47 can be used as one # 极 H # 主 " The muscle body's private sun body becomes a gate electrode, and the data line 6 2 = type element pole 71 is formed-drain electrode, as shown in FIG. 5. Because: The prime 71 is superimposed on the front-to-line, as in this example, a transistor will cause a big problem, but the semiconductor layer can be

Page 23 557387 V. Description of the invention (19) A power channel is formed at a voltage. If two adjacent data lines are connected through the semiconductor layer, the signals of the two data lines will interfere with each other. Therefore, in other types and previous gates In the model, the separation of the semiconductor layers is necessary. A conventional example of a non-precedent uranium gate type will be described in a fourth example of the present invention. A method of manufacturing a thin film transistor array panel according to a first example of the present invention will now be described with reference to FIGS. 6A to 8C and FIGS. 3 to 5 described above. Figures 6A, 7A, and 8A are configuration diagrams of a TFT panel, and are arranged in order according to the manufacturing steps of the first example of the present invention. Figures 6B, 6C, 7B, 7C, 8B, and 8C are ¥ 18 along Figure 6 -¥ 18 'and ¥ 1〇 ¥ 1 (:, cross-sections taken from line VIIB-VIIB of Fig. 7 and VIIC-VIIC, line and VIIIB-VIIIB' and VIIIC-VIIIC 'of Fig. 8A. First, as shown in FIGS. 6A to 6C, a metal conductor layer is deposited on a substrate 10 by sputtering, and has a thickness of 1,000 to 3,000 angstroms, and one includes a gate line 2 2, a The gate circuit of the gate pad 24 and one gate electrode 26 is formed by using the first photomask in a dry or wet mode. As described above, the gate circuit 2 2, 2 4, 2 β can be made of Selenium and molybdenum tungsten. Double-layer construction, and dry etching is preferred at this time, while wet etching is preferred when the intermediate circuit is made of double-layer chromium and aluminum. Second, as shown in Figures 7A and 7B, a gate The insulating layer 30, a semiconductor acoustic 40, an ohmic contact layer 50, and a data conductor layer 60 of chromium or aluminum 'alloy are sequentially deposited and patterned by dry etching. At this time, as shown in FIG. A, four The patterns of 30, 40, 50, and 60 form a mesh pattern to cover the entire lines 22, 24, and 26. An opening 22 of the substrate 10 is exposed and formed in the pixel area. A contact hole 21o that exposes the brake pad 24 is formed on the brake pad 24.

Page 24 557387 V. Description of the invention (20) Secondly, as shown in FIGS. 8A to 8C, a ΤΤ layer is stacked and patterned using a third mask and dry money engraving to form a conductive pattern 71 , 72, 73, 74, 75, 76, 77, and subsequently, the portions not covered with the lean conductor layer, the transparent conductor layer, and the ohmic contact layer 50 are removed by dry etching. Secondly, as shown in FIGS. 3 to 5, a passivation layer of one is deposited and patterned using a fourth photomask to form openings 81, 82, 83, 84, 85, and is exposed through the openings 81, 82. The semiconductor layer 40 is etched and divided into two pieces 42, 47. At this time, the etching process of the passivation layer 80 and the semiconductor layer 40 is sequentially performed by a dry etching process. When the etching rate of Si Nx with respect to the amorphous silicon is about 丨 0: 丨, the rat (C 12) and oxygen ( 〇 2) mixed gas can be used as a silver engraved gas. This special film transistor panel can be manufactured in many other ways and made into many other variations. ° A TFT array panel and a manufacturing method thereof, which are one of the second examples of the present invention, will be described below. FIG. 9 is a layout diagram of a TFT panel for an LCD according to a second example of the present invention, and mainly includes a pixel and a pad of FIG. 2, and FIG. 10 and i] are along x — x and XI-XI of FIG. 9, respectively. 'Cross section taken from the line.

^ As shown in Figures 9 to 11, the structure of the TFT array panel of the second example is almost the same as that of the first example, except that the perimeter of the pads, that is, the gate insulation layer 30 between the pads is in the first example. , But not in the second example. In addition, the passivation layer 80 in the second example has an opening 86, which is like a crease and exposes the gate insulating layer 30 between the pads. Therefore, ^ is not interconnected via the semiconductor layer. Asia will now be described with reference to FIGS. 12A to 13B and FIGS. 9 to 11 to illustrate a second embodiment of the present invention.

Page 557387

Example of a method for manufacturing a thin film transistor array panel. FIGS. 12A and 13A are configuration diagrams of a TFT panel and are sequentially arranged according to the second manufacturing step of the second example of the present invention. FIGS. 12B and 13β are X along a XIIB-XI I ′ B and FIG. 13A iXIIIB — Sectional view taken along the χπ Γ β line. First, as in the first example, a gate line 22, 24, 26 is formed. Then, four layers of a gate insulation layer 30, a semiconductor figure 40, an ohmic contact layer 50, and a data conductor layer 60 are sequentially stacked and patterned. At this time, as shown in FIG. 12 /, 12B It is shown that the four layers are removed at the periphery of the cushion. Secondly, as shown in FIGS. 13A and 13B, an ITO layer is stacked and patterned using a third mask and a dry pattern to form a conductive pattern 71, 7 3 74 7 5 7 6, 7 7 Then, the parts that are not covered with the transparent conductor layer 60 and the ohmic contact layer of the data conductor layer 60 are removed by dry etching. Secondly, as shown in FIGS. 9 to 12, a passivation layer 80 is stacked and patterned by using a fourth photomask to form openings δ1, 82, 83, 84, and 85, and then etched by the opening 81. , 82, 86 exposed semiconductor layer 40, and half of the data line below, the body layer 40 is separated from each other, and the part between the pads is removed. In the first and second examples, the edge of the pixel electrode 71 is covered by the passivation layer 80, but it may not be covered by the passivation layer 80. In this case, reference will be made to the second example with reference to FIGS. 4, 4 and 5. 15 is a face-to-face drawing taken along the line ―χν, in FIG. 14. As shown in FIGS. 14 and 15, one of the openings 85 of the passivation layer 80 exposes the edge of a pixel electrode 71, so the substrate 10 between the passivation layer 8 () and the pixel electrode 71 can be exposed. The other structures are almost the same as those of the first example.

Page 26 557387 V. Description of the invention (22) This structure needs to prevent the pixel electrode 7 1 from being short-circuited to the conductive pattern 72 on the material 62 or the lean material line 62 via the semiconductor layer 42. That is, although the pixel electrode n furnace: lineman The conductor layer 42 is' under the data line 62 but the two sides are not invested due to the staggered sides, but the exposed portion of the semiconductor layer 42 through the opening 85 can be removed after the opening 85. Therefore, the pixel electrode 71 / system is separated from the portion below the data line 62. The example of the limb layer is about the previous gate TFT array panel, but the first to the invention can be applied to a separate common line TFT array panel, which will be explained by four examples. 'FIG. 16 is a layout diagram of a TFT panel for an LCD according to a fourth example of the present invention, and 17 and 18 are cross-sectional views taken along FIG. 16 2 × νπ—χνι 1 and χνι ^, respectively. Λνΐ11, and the selection is shown in Figures 16 to 18, „Storing the left ο 7 〇〇 / 么 99 94 9 R ^ ^ ^ ^, Spring Road 27, 28 are slightly along a gate line 22, 24, 26 are formed on a p ^ ,,, and rim base material 10 'storage line 2 7, 9 0 The same material is made and on the same layer as the gate line 22, 24, 26. The door is made of The road includes the gate line (scanning signal line) extending in the horizontal direction for 2 days 2. _ = at the end of the gate line 2 2 and is bitter from the outside ^, ,, and is connected to the gate block 24 and a thin film mine Touch, I am the master, and the fruit 2 2 ~ The gates 27 and 28 that are part of the crystal package include a separate and parallel financial storage line such as the shell material line 2 2 after storage 2 7 and the agricultural β is allowed to be horizontal. , And a storage pad 28 connected to the "ten alpha Dingzi, urine" and its extension pa ^ s Qη ^ ^% storage line 27 end. Yizha Township's marginal layer d U is formed on A ^ / y 'closed lines 22, 24, and 26 on the storage line 9 7 28, and a semiconductor layer 42, 4q π ^, Lecun, Quanlu 27 ,,.. &Amp; 4 9 are formed on the gate insulation layer 30. The semiconductor patterns 42, 49 have a part of the force, a part of the part 42 is extended to the middle of the fan, and the part of the second part 49 is located in the second part. Loan straight brothers part 4 between 2 and located on the storage line

Page 27,557387 V. Description of the invention (23) 27, and isolated from the first part 42. An ohmic contact layer 55, 56, 58, 59 is formed on the semiconductor pattern 42, and a conductive material such as molybdenum or molybdenum-tungsten, chromium, and giant is formed on the 62, 64, 66, 68, and 69 series on On the ohmic contact layers 55, 5 '. The data lines 62, 64, 66, 68, 69 have an include-source :, 59 = a material line 62 extending in the vertical direction 62 'a first isolated data conductor 68, ^ formed on the second part 49 of the half-body layer The second isolation ohmic contact layer pattern 55, 56, 58, 59 series is between 9 and data lines 62, 64, 66, 68., 69, and =:? 9 lines 62, 64, 65, 68, 69 configuration. The door is on the other hand, located on the brake pad 24 and the storage pad 28: the semiconductor layer 42, the ohmic contact layer pattern 58 and the first isolation; ^ has a contact hole to expose the brake pad 2 4 and storage pads 2 8. ㈣ = 1 electricity; conductive materials 75, 76, and 77 made of raw materials such as IT0 (indium tin oxide) are formed on the data lines 62, 64 in the pixel area surrounded by the gate line and the capital, bucket, and water 62 , 66, 68, 69 and above. Conductive patterns 71, 72, 73, 74,? 5, 76, 77 include ^ #The fourth pattern, the first pattern formed on the data line 62 and the data pad 64 is divided into two parts, one is the part 7 5 on the source 65 and the other is The first patterns 71 and 76 include a portion 76 on the drain electrode 66 and a photo area. As shown in FIG. 16, the pixel electrode 71 is extended and formed at the first; To form a storage type holder which overlaps the storage line 27. The third pattern 74 is formed on the data pad 64 to assist the ohmic contact between the & ▲ 4 and an external circuit, and the fourth pattern 73 is formed.

O: \ 58 \ 58736.ptd Page 28 557387 I. Explanation of the invention (24) I The ohmic contact between the block 24 and the storage block 28, the entire block 24, and an external circuit. Exposed through contact holes and storage pads 2 8 and 1

'To assist the gate i external circuit I — a passivation layer 80 made of an insulating material such as SlNx is formed on the above structure. The second passivation layer 80 has an opening to expose the pixel electrode 71 and =, and the result is passivation. The layer 80 is divided along the data, 幵 π; except for the opening of the semiconductor layer 42 exposed through the opening, this can prevent two adjacent data lines 62 from shorting to each other, and at the same time, the pixel electrode 71 can be determined. The passivation layer 80 also has openings 83, 84 / V. The three and four transparent conductive patterns 73: 7 have 4 openings 83 84 ', respectively. The other structures are similar to those of the third example. ^ The manufacturing method of the example is almost the same as that of the first example, except that the Bedincun lines 27 and 28 are formed along the gate lines 22, 24, and 26. An example of applying the present invention to a ring gate TFT array panel will be described. FIG. 19 is a cross-sectional view taken along line XX-XX of FIG. 19 as a TFT 20 for a LCD according to a fifth example of the present invention. As shown in FIGS. 19 and 20, a 26 series extending in the horizontal direction is formed on an insulating substrate, and the gate line 22 is interconnected into a gate line bridge 25. Among them, one has a gate electrode. However, it can be seen that the gate block is the same as the front side panel layout of the previous example. The gate lines 2 2, 25, and 10 pass through in pairs. Although it is not connected to the gate line 22 in the figure—a gate insulation layer 30 is formed on the gate lines 22, 25, and 26, and a semiconductor layer 42 is formed on the gate insulation layer 30, and the semiconductor layer 42 is gasified. μ ¥ outside, one first

Page 29

557387 Fifth, the description of the invention (25) points is the first and second parts extending beyond the horizontal 6 ^ ^ channel part, and ′ is separated from the TFT bridge 25. σ | knife, and the gate line 22 and the gate line LI that are overlapped on a part are in contact with each other in 5 layers = 57 are formed on the semiconductor layer 42 with the data line 62, 65, 66 ohmic contact layers 55, 56, On the line 62, the line 62 has a -υ-shaped recess A7 including a data line 62, a drain 66 connected to the data input portion, and. — Pole 65 of the car, a storage electrode fi7 formed in the second part of the recess 65 of the source 65 —connected to the drain 66 and overlapped with the semiconductor layer in the data record ”2. Although not shown in the figure, a data pad Connected to the spacer block: = = The volume is the same as in the previous example. The terrain volume layer 42 and the data line 62, f5 layer pattern, 56, 57 are formed on the semi-conductive line 62, 65, 66, 676. 5: Set 6, between, and have the same as the other aspects-the gate insulation layer 3 〇, carved data conductors, etc. are located on the gate pad :: 42 / m contact layer and the isolation block 24. Charge 24 A contact hole is used to expose the picture = transparent 7 and 2 and 7! Γ6:;: ΙΤ〇 (indium tin-defined data lines 62, 65 1 ^ gate line 22 and # 料 线 62 surround the transparent conductive pattern 72, 75, 76, on the pixel area substrate 10, at this time, the configuration of 65, 66, 67, for example; the data line 6 below it 2, the transparent conductive pattern part on the pad, ::: pole 71 and The question block and the data M and 67 and the ohmic contact layers 55 and 56 are made of transparent conductive material because the data lines 62 and 65 and the pixel electrode 71 are extended and 75 and 76 are formed as an etching mask. Pattern 72, O: \ 58 \ 58736.ptd Page 30 557387

V. Description of the invention (26) It is on the storage electrode 67 and overlaps the gate line 22 and the gate bridge 25 to form a capacity is. The same as the previous example is the ‘brake pad and data block’. The storage conductive pattern can assist the brake pad. Among them, the passivation layer 80 made of insulating material such as Si Νχ is formed on the substrate. The passivation layer 80 has an opening 85 to expose the pixel electrode 71, and the 8 1 series exposes the gate insulation layer. 30 and the substrate 10 are formed along the edge of the pixel electrode 71. At this time, the groove 81 extends in the vertical direction and surrounds the pixel electrode 71, except for the part connected to the electrode 66. The groove 81 is prevented by removing the semiconductor layer 42 and the remaining ITO under the groove η. The two adjacent data lines 62, the pixel electrode 71 and the data line 62 are short-circuited to each other via the semiconductor layer 42 or the residual ITO. The manufacturing method of the four kappa cases is the same as that of the first to fourth examples. In the following, the sixth to eight examples are used to explain the other methods for achieving the purpose of the present invention.结构 The structure of the TFT array panel of the sixth example will be described with reference to Figs. 21 and 22. Fig. 21 is a configuration diagram of a TFT panel for an LCD according to a sixth example of the present invention, and Fig. 22 is taken along the line XXII-χΧΙΙ 'of Fig. 21 Take the face map.

First, gate wires made of metal or conductive materials, such as aluminum (A1) or aluminum alloy, molybdenum (Mo) or molybdenum tungsten (MoW) alloy, chromium (Cr), and tantalum (Ta), are formed on an insulating substrate 10 on. A gate line includes a gate line (scanning signal line) 22 extending in the horizontal direction, a gate pad 24 connected to the end of the open line 22 and from the external circuit to the gate line 22 to transmit the scanning signal, and as a thin film electrical Part of the gate of the crystal 26.

Page 31 557387 V. Description of the invention (27) — ~ '' ~~~~-The line 22, 24, 26 may be a multi-layer structure and the line 22, 24, 26 forms a multi-layer structure. ， == resistance material, and its other layer is made of 1 # u is a layer made of low-J materials, such as chrome / shaw (or Ming alloy) and shaw / pin are examples of double-layer : = Shi Xi (Sl =, the insulating layer 30 is formed on the intermediate lines 22, 24, 26; 4: Γ0 covers the substrate 10 of the display area, but does not overlap the substrate 10 and pads of the Qiongjie area 24 〇 The semiconductor pattern 42 made of semiconductor is, for example, formed on the gate insulation layer 30. One is, for example, a girl who exchanges non-Japanese silicon for flying, known as Φ 42. The W 6 series is formed on the semiconductor pattern. Conductive materials such as pins, data lines 62'64, 65, 6fi i, or aluminum alloys and buttons are made on top of one of the data line 62, 64, 65 ohm contact layer patterns 55, 56 and an external The "electrical history" section 64 is connected to the data line 62 and also has a drain electrode 66 # ^ 像 ㈣ to the data line 62. The vertical side of the data line. The relative data line 6 is related to the gate 22 and located at the source 65 2, 6 4, β ς β. The multi-layer structure of 26, when iron two lines 22, 24, it is best-the layer is made of low-power field points, the surface of the road has a multi-layer structure with good contact materials. And another layer with the pattern of ohmic contact layer with other materials ^ 55, 56 plays a role in reducing the semiconductor pattern 557387 V. Description of the invention (28) 4 2 and data line 6 2, 6 4, fi Rα is now called , The contact resistance between FI rra 6 and 6, and it has the same configuration as the negative material lines 62, 64, aa ^ /, /, 'M. ^ ig n iA ^, 66. Semiconductor pattern 42 j: 】 Yu Road 62, 64, 65, 66 and ohmic contact layers 55, 56 Γί 明 ί: Except the part of the channel between and electrode 66. Figure 7 丨 4 5 Electrical materials such as Π〇 (indium tin oxide) The made conductive " .tf ^, 74 are formed on the data lines 62, 64, 65, 66 and constitute :: f:;, 72, 73, 74 including a pixel area of the substrate 10 ί ί This area It is surrounded by the gate line 22 and the data line 62, and u㈣ extends and is formed on the drain 66 and overlaps the gate line ^ /, a dozen storage capacitors. The conductive patterns 71, 72, 73, 74 also include a 2 two! The material pad and a redundant gate pad '"cover the data line, the bead pad, and the pad pad respectively. In the sixth example, a passivation layer 80 covers the conductive patterns 72, 73, and 74, including Covered with conductive patterns 71, 72, 73, 74 and redundant gate pads like I-pole 71, semiconductor layer pattern 42, and gate gate lines 2 2, 2 4, 2 and 6 without gate insulation. However, the passivation layer 80 may form only a part of the semiconductor layer pattern 42 that covers only the channel portion, that is, between the source 65 and the drain 66, and the purification layer 80 may be made of si x or an organic insulator such as acrylate. In this example, the conductive pattern is made of a transparent material, but in a reflective LCD, it may be made of an opaque material. A method of manufacturing a thin film transistor array panel according to a sixth embodiment of the present invention will now be described with reference to Figs. 23A to 29B and Figs. First, as shown in FIGS. 23A to 23B, a metal conductor layer is deposited on a substrate 10, for example, by sputtering, and has a thickness of 1,000 to 3000 angstroms, and one includes

Page 33 557387 V. Description of the invention (29) 'a — a gate line 2 2, a gate pad 24, and a gate line 26 are made by dry or wet etching using a first photomask. Secondly, as shown in FIGS. 24A to 2B, a gate insulating layer 30, a semiconductor layer 40, and an ohmic contact layer 50 are sequentially deposited by chemical gas deposition at 1500 to 5000 angstroms, 500 To 2000 angstroms, and 300 to 600 angstroms. Subsequently, a metal layer 60 is deposited by, for example, sputtering to have a metal layer 60, an ohmic contact layer 50, a semiconductor layer 40, and a gate insulating layer 30 with a degree of 5,000 to anisotropy to form a metal. Layer pattern 61, a first ohm, a contact layer pattern 51 and a semiconductor layer pattern 42 below, as shown in FIG. 28. At this time, the metal layer pattern 61 is similar to the completed data line, the difference is that A source and a drain are connected to each other. Except for the metal layer pattern 61 and the drawings below, the metal layer 60, the ohmic contact layer 50, the semiconductor layer 40, and the gate insulating layer 30 are removed in the peripheral region p. However, the insulating layer 30 is not removed in the middle of the display area, nor is the metal layer pattern 61 and the layers below it. For this purpose, a PR layer is formed to have a thickness that varies depending on the position, and the layers below the pR layer are dry-etched using the PR pattern as an etching mask, which will be described with reference to FIGS. 24β to 27. f First, a preferred positive pR layer having a thickness of 50,000 to 30000 angstroms is coated on the metal layer 60 and exposed through three photomasks 300, 41, and 42 as shown in FIG. 2B. "PR layer in display area D and surrounding areas? Each of them is different, and the / composite in the exposed part is decomposed from the surface to a depth, and the lower part in the display area D is unchanged. However, the polymer in the exposed portion β is in the peripheral region ?: The upper surface element is completely decomposed to the bottom surface, and the metal layers of the exposed portions c and 6 are removed.

557387 V. Description of the invention (30) — Based on this purpose, one of the photomasks 300 used for the alignment of the display area D may have a structure that does not align the photomasks 41 and 42 used on the peripheral area P, These three methods will be explained. First, as shown in FIGS. 25A and 25B, the photomasks 300 and 400 respectively include normal substrates 310 and 410, opaque pattern layers 320 and 420 made of, for example, chromium, and covering the opaque patterns. The light transmittance of the mold layers 32 and 42 and the substrates 330 and 410 of the exposed substrates 310 and 410, and the light transmittance of the mask 300 for the display area D and the thickness 3j0 are lower than those of the peripheral area p. 4 The light transmittance of the thin film 43 is preferably 10% to 80% of that of the thin film 4 30, and the best A 9 η r π 〇 /. 1 ^

Secondly, as shown in FIGS. 26A and 26B, a thickness of 10 () to 30 () Angstroms is formed on the I display area D mask 3 ′, in order to reduce the light transmission rate, and the layer f periphery + side area P light In the mask 400, the chromium-free layer 35 is used, and the light transmittance of the display area 0, the mask 300, and the film 3 40 may be equal to that of the film 43. A mixed structure of the above two can be obtained. In the method, because the PR layer is a mask

The above two examples can be used for multiple shots with a stepper, and the mask in the display area D and the surrounding area p are made of separate pieces. The thickness can be controlled by adjusting the exposure time. However, the display The area D and the surrounding P can be exposed through a photomask, and this structure will be described with reference to Fig. 27. 51-Fig. 27. A transmission rate control layer 51 is formed on a substrate 500 or above. The pattern layer 5 2 0 is formed on the transmission rate control layer 5 1 0. The transmission rod control layer 5 5 0 is not only located on the top of the figure 9 9 n nr ·· m 惶 Han lying under the Bi jade layer, but also in alignment In the entire area of the display area, in the peripheral area p, it is only below the pattern layer 52.

Page 35 557387 A '----------__ V. Description of the invention (31) — ~~ -—-_____________________ side. Therefore, at least two _ g ± 51 0 on. /. Patterns of different thicknesses are formed on the substrate. A transmission rate control layer can be opened & M + ^ region D. 3, the transmission rate of the control layer should be greater than the display · display 2 = pass; = rate control layer 5500 mask 5. . A layer 550 having a -patterned layer ㈣ is Λ / placed Λ 2 and a layer 550 and one covers the entire substrate 2: put on. -Not shown in the figure) The coating layer is etched as an etching mask: the post-exposure and development 'pattern layer 520 uses PR, and the value is divided by' in order to obtain a complete mask 50. Shape pattern and + P g # π # f Control the resolution of the first mask with a long slit or a grid j% of the first device. The PR layer is exposed and exposed, as shown in FIG. 25B. The actual layer is formed into a PR pattern with a different thickness and a metal layer pattern 61. There is no hafnium layer, and a layer pattern is formed. Type 6 丨 In the case of ΪL, a thicker layer is formed on the place where the metal is provided. Whereas, a thinner p R layer C is formed in the display area d. At the same time, the thinner PR layer C is formed. The thickness is preferably 1/4 to 1/7 of the initial thickness,

The σ is 350 to 10,000 Angstroms, and preferably 1000 to 6000 Angstroms. For example, when the thickness of PR 2 Si! Is 16,000 to 2400 Angstroms, the thinner suppressive layer can have a transmission rate of 30% to have 3,000 to 70,000 Angstroms. The thickness of the PR layer is determined by dry etching conditions, so the thickness of the film, the remaining chromium layer, the rotation rate of the $ rotation rate control layer, and the exposure time should be controlled according to the etching conditions.

557387 V. Description of the invention (32) ·: The thin PR layer can be formed by re-flowing, and it can be developed first and often when exposed. Subsequently, the PR pattern and the following exhibitions such as Dongliwangjuju metal layer 60, ohmic contact layer 50, half ¥ 40 layer, and gate insulation layer 30 were all dry-etched. As mentioned above, at this time, the PR chart of the A-shirt ^ ^ ^ 13 A ^ points should still be retained, and the second part below the β part, the ohmic contact layer 50, the semiconductor layer 40, and the gate insulation layer 30 should = 丄 // The metal layer 60, the ohmic contact layer 50 and the semiconductor layer below the knife: two, and the part 30 of the gate insulation layer below the part C should be retained. In order to pay for this structure, the metal layer 60 exposed by the surrounding civil wing and bucket is removed by wet etching and freeze-dried to expose the ohmic contact layer 50. Secondly, the pR layer and the J: bottom ^ layers are engraved with -dry money and the last name is etched. The etching is performed until the thinner two-sided metal layer 60 is exposed. The ohmic contact layer 50 and the underlying semiconductor layer 40 are also etched away. Κ 丄 :: The layer 40 can still retain its thickness or be completely removed to reveal = 40 Vn, and the margin layer 30 can also be slightly sized, which depends on the thickness of the inscribed strips and the thickness of =, 50, which is thicker at this time. The PR layer A is also # apart from a little ^. / 、 _, The exposed metal layer 60 under the C part is removed by dry etching using wet etching to expose the ohmic contact layer 50, the ohmic contact layer and the i-type are etched and removed, thereby making it possible to Except for the ohmic connection fine layer 50, the + conductor layer 40, and the gate insulation layer 30, the etch contact 2 is exposed, and at this time, the ohmic contact layer 50 and the semiconductor layer of the C portion are removed; 0 is removed. Therefore, the metal layer pattern 61 and the first ohmic contact layer pattern 51 of the display area

557387 '~~ ------------ η V. Description of the invention (33) and the semiconductor layer pattern 42 are formed, and in addition to the metal layer pattern 61, the metal layer 60 and the ohm in the peripheral region The contact layer 50, the semiconductor layer 40, and the gate insulating layer 30 | are also removed using a light lithographic printing step. Secondly, after the remaining PR is removed, an ITO 0 layer is deposited to a thickness of 400 to 500 angstroms using, for example, money shots, and then the ITO layer is patterned to form conductive patterns 71, 72, 73, 74, as shown in the figure. 29A, 29B. At this time, the portion between the pixel electrode 71 and the redundant data line 72 of the metal layer pattern 61 is exposed. The exposed metal layer pattern 61 separates the source 65 to the drain 66 by wet etching, and exposes The first ohmic contact layer pattern 51 is shown below it. The first contact pattern 51 subsequently exposed is etched to expose the semiconductor layer 42, and a completed TFT is obtained. In the final step, a passivation layer exceeding 300 angstroms 80 is formed using SiNxi (chemical gas deposition) Or formed by spin coating of an organic insulator, and a pattern is produced using a fourth photomask. At this time, the passivation layer 80 can be made of a light-defining material. In this example, the patterning of the passivation layer 80 can be achieved only by exposure and development, without the need for a photoresist layer. With this, the redundant question block 73 and the redundant data block 74 are exposed. The pixel pole 71 is described above. The number of steps in light lithography is

i 2nd n: ohmic contact layer pattern 51 and semiconductor layer pattern 42, "丨 insulating layer 30 pattern covers the gate pad 24 and is reduced. Clothing out 丨 In the sixth example, the TFT array panel is only right Defeng κ y Ming's TFT array panel can also have a common electrode, but this is illustrated by the seventh example. Figures 30 to 35C show the seventh example. "This case will first explain the structure of the TFT array panel of the seventh example.

Page 38 557387 V. Description of the invention (34) Fig. 30 is a layout diagram of a TFT array panel used for a CD according to the seventh example of the present invention. Figs. 31 and 32 are along XX XI-XXXI 'and XXX along Fig. 30, respectively. A cross-sectional view taken along the line I-XXXI Γ. First, a gate line system made of metal or conductive material such as aluminum (Ai) or aluminum alloy, molybdenum (MO) or molybdenum tungsten alloy (MoW), chromium (Cr), and button (Ta) is formed on an insulation On the substrate 10, a gate line includes a gate line (scanning signal line) 2 extending in the horizontal direction. 2. A gate connected to the end of the gate line 2 2 and transmitting a scanning signal from an external Thai road to the gate of the gate line 22. The pad 24 and a gate 26 as a part of the thin body. 1. The common electrode circuit made of the same material as the gate circuit is a common electrode circuit insulation substrate 10, and the common electrode material includes-common line 27 = common electrode 28 of the vertical branch line of line 27, and the common line can also be packaged as common Common line 27 —The terminal is connected to the common line of r from an external circuit (not shown in the figure, the common block is 22, 5 nitrogen = silicon gate insulation layer 30 is formed in the gate green 30 Shun box — ί, on the same private circuit 27, 28 and covered with, the gate, the base material 10 of the road, but does not cover the peripheral block of the gate I, the common pad and the base material 10. The brake pad rope 24, formed by semiconductors such as hydrogenated Fei Shi on the gate insulation layer 30,-:: two reference conductor layer pattern 42 series non-placed Shi Xizhi made by, for example, soaring in the sky with impurities like a dish-"quote into the -Ohmic contact layer patterns 55 and 56: Doping ^; The semiconductor layer pattern 42 is made of conductive materials such as molybdenum or molybdenum tungsten, chromium, aluminum or aluminum alloy, and

557387 V. Description of the invention (35) --- ~~ ------------ Data lines 62, 64, βς ηο ，, data lines 62 6 are formed in the ohmic contact layer pattern 55, 56 source level 65 and extends to the Dingjigu 65, ^ has a lean material line 62, which includes one of the six, a straight direction, a data block 64 connected to the data line 62, and the road is also right one two / The external circuit sends an image signal to the data line 62. The vertical side of the data line: 5 6 6 'is a relative ohmic contact layer pattern M, which is related to the gate electrode 22 and located at the source electrode 6 5, ^ ^ ^ • The role of the data line in reducing the semiconductor pattern is the same as the data line 62 = the contact resistance, and it has a configuration of 64, 65, and 66 of the right η recognition system. Semiconductor pattern 42 :; shell = lines 62, 64, 65, 66 and ohmic contact layers 55, 56, except for the portion of the channel between the source 65 and the drain 66. Pattern 7 ^ Transparent 7 ^ Conductive Rfi made of conductive materials such as ITO (copper tin oxide), 74, 75, 76 are formed on the data lines 62, 64, 65, 6 = Electrical pattern 72, 73, 74, 75, 76 include ^^^ and the pixel polar line on the common line 27 and a pixel polar line 75 connected to the pixel electrode 76: the pixel electrode 76 on the common electrode, the pixel electrode 76 and the common electrode 2 by 2 An electric field is formed between 7 ° and the pixel electrode 76 may overlap the common electrode 7R ′ to form a storage capacitor. The conductive patterns 72, 73, 74, 75, and the network include a few more material lines 7 2 to cover the data line 6 2 and the source 6 5. A redundant p gas material pad 74 to cover the data pad 74, A redundant brake pad 73 covers the first block 24 and a redundant common pad line (not shown in the drawing) to cover the common pad. For the second time, a passivation layer 80 has contact holes 83 and 84 to expose redundant I dry blocks 3, redundant data pads 74, and redundant common pads, which are formed on 72, 73, and 74. . The passivation layer 80 may be organically insulated

Page 557387

3 2 Description of the present invention 丨 I. 5. Description of the invention (36) I marginal products, such as acrylic. 33A to 35C and FIG. 30 will be referred to the above-mentioned thin film transistor array panel manufacturing method. First, as shown in FIGS. 33A to 33C, a metal conductor layer is deposited on a substrate 10, for example, by sputtering. And has a thickness of 1000 to 3000 angstroms, and a pack of 7 = line 22, a gate pad 24 and a gate line S of the gate line S-including two 2: electricity? The wires 27, the common electrode block of the common pad and the common electrode 28 are made with a dry or wet instrument using a first photomask. Secondly, as shown in FIGS. 34A to 34C, an insulating layer 30, a semiconductor layer 40, and an ohmic contact layer 50 are sequentially deposited by chemical gas deposition (cvd) to 1500 to 50, respectively. 0 Angstroms, 50 to 2000 Angstroms, and 300 to 600 Angstroms in thickness. Subsequently, a metal layer 60 is deposited by, for example, sputtering to a thickness of 500 to 100 angstroms. The metal layer 60, the ohmic contact layer 50, the semiconductor layer 40 and the gate, and the edge layer 30 are patterned. In order to form a metal layer pattern 61, a first ohm, a contact layer pattern 51 and a semiconductor layer pattern 42 below, as shown in FIG. 28, this is a layer pattern 6 1 is similar to the completed data The difference is that a source and a drain are connected to each other. Except for the metal layer pattern 6 and the drawings below, the metal layer 60, the ohmic contact layer 50, the semiconductor layer 40, and the gate insulation layer 30 are removed in the peripheral region P. However, the insulating layer 30 is not removed in the middle of the display area, nor is the metal layer pattern 61 and the layers below it. The above is completed by the method in the sixth example, that is, a PR pattern whose thickness varies according to its position, and the pR pattern and the layers below it are etched once. Second, the conductor layer is deposited to have a thickness of 400 to 5 0 0 557387 by, for example, sputtering. 5. Description of the Invention (37) | Angstrom, and then the conductor layer is patterned to form conductive patterns 72, 73, 74; , 75, 76, as shown in Figures 29/1 and 2 9B. At this time, the part between the pixel electrode line 75 and the redundant data line 72 of the metal layer pattern 61 is exposed. The exposed metal layer pattern 61 is separated by wet etching to separate the source electrode 6 5 from the drain electrode. 6 and the first ohmic contact layer pattern 51 below it is exposed. The exposed first contact pattern 51 is subsequently etched to expose the semiconductor layer 42 and obtain a completed TFT. In the last step, a passivation layer 80 of more than 3,000 angstroms is formed by CVD (chemical gas deposition) of Si Nx or spin coating of an organic insulator, and a pattern is formed by using a fourth photomask. By making a pattern from this, the redundant gate pad 73 and the redundant data pad 74 are exposed. Another manufacturing method of a TFT array panel using only four lithographic printing processes will be described with an eighth example. In the eighth example, a common electrode and a pixel electrode are formed on the TFT array panel. A TFT array panel and a manufacturing method thereof according to an eighth example of the present invention will be described with reference to Figs. 36 to 41C. First, FIG. 36 is a layout diagram of a TFT panel for an LCD according to an eighth example of the present invention, and FIGS. 37 and 38 are cross-sectional views taken along lines XXXVI I-XXXVI Γ and XXXVIII-XXXVIII ′ of FIG. 36, respectively. A gate line system made of metal or conductive material such as aluminum (A 1) or aluminum alloy, molybdenum () or molybdenum alloy (MoW), chromium (Cr), and button (Ta) is formed on a mouthpiece of insulating substrate 1 On 0, a gate line includes a gate line (scanning signal line) extending in the horizontal direction 2 2. A gate block connected to the end of gate line 2 2 and transmitting a scanning signal from an external circuit to gate line 22 24. One is a thin film transistor-part of the gate electrode 26.

557387 I V. Description of the invention (38) -------------- j I = The common t-pole circuit made of the same material as the intermediate circuit is formed on an insulating substrate 10, and the common electrode line is lost. The common line 27 and the common electrode 28 serving as the common f7 vertical branch line can also include a common electrode 28 connected to the same electrode line 27-terminal and transmitting a common electrode signal to the common circuit from an external circuit. The common block of line 27 (pictured; u block 24. r wo not) 'common block is very similar to the gate 22-2 formed by ΛΓ = Νχ dead body _ layer 30 is formed between the lines 3〇 = if The base electrodes 10 and 27 are covered and covered with the gate insulation layer 30, but the common substrate and the base material 10 are not covered. Heart net 块 • Block Z4 is made of semi-conductor such as hydrogenated amorphous stone on the gate insulation layer 30, one is made of, for example, Stan ^, and is made of, for example, doped with impurities such as phosphorous doped in ali. An ohmic contact layer pattern 55, 56 is formed on the half-layer pattern 42. A conductive material such as molybdenum or molybdenum tungsten, chromium, aluminum, or aluminum data lines 62, 64, 65, 6β, M RQ ^, and ^ clothing made of 68, 69 are formed on the ohmic contact layer == material line 62 , 64, 65, 66, 68, 69 have-Zi 6 = Α a source level 65 and extend in the vertical direction,-data block block ^ shell;, one end of line 62 and transmits an image signal from an external circuit to: Quan # material line also has-not deleted, is related to the gate 22 and, on the opposite side of the source electrode 65, a pixel electrode line 6 9 extends from the drain electrode 6 6 and the Asian Union is on the common line 27, The pixel electrode 68 is a part of the pixel electrode 69 and is connected to the common electrode 28. The pixel electrode 76 and the common electrode 27 are sequentially disposed, and an electric field is formed between them. The pixel electrode 76 may overlap the common electrode line 27, so that

Page 43 557387 V. Description of the invention (39) Form a storage capacitor. The role of the zone κ contact layer pattern 5 5, 5 6 is to reduce the contact resistance between the semiconductor pattern 42 and the data lines 62, 64, 65, 66, 68, and ㈢, and it is the same as the data line 62 , 64, 65, 66, 68, 69. The semiconductor pattern 42 has the same configuration as that of the data lines 62, 64, 65, 66, 68, 69 and the ohmic contact layers 55, 56 except for the portion of the channel between the source 65 and the drain 66. The purification layer 80 is formed on the data lines 62, 64, 65, 66, 68, 69

^, The passivation layer 80 has contact holes 82, 84 to expose the data line 62 and the data pad 64, and a contact hole 83 to expose the gate pad 24. The passivation layer 80 may be S 1 Nx or an organic insulator. Made of, for example, acrylic. A conductive pattern 72, 73, 74, 75, 76 is formed on the passivation layer 80, = an electric pattern. The patterns 72, 73, 74, 75, 76 include a redundant data line 72 to cover the lean material line 62, A redundant data pad 74 covers the data pad 64 and a redundant interval pad 73 covers the brake pad 24. fA method of manufacturing a thin film transistor array panel according to an eighth example of the present invention will be described with reference to Figs. 39A to 41C and Figs. 36 and 38 described above.

Baixian is shown in FIGS. 39A to 39C. A metal conductor layer is deposited on a substrate 10, for example, by sputtering, and has a thickness of 1,000 to 3,000 angstroms. The gate circuit of a gate pad 24 and a gate electrode 26 and a common electrode circuit including a common electrode line 27, a common pad block, and a common electrode 28 are made by dry or wet etching using a first photomask. . Secondly, as shown in FIGS. 40 A to 40 C, a gate insulating layer, a semiconductor layer, and an ohmic contact layer 50 are sequentially deposited using chemical gas deposition (CVD).

Page 44 557387 I. V. Description of the invention (40) —- | Set the thickness to 1 500 to 5 0 0 angstroms, 5 0 to 2 0 0 0 angstroms, and 300 to 6 00 angstroms. i Subsequently, a metal layer 60 is deposited by, for example, sputtering to a thickness of 15,000 to 3,000 angstroms, and the metal layer, the ohmic contact layer, and the semiconductor layer are patterned by a second light lithography step to Form a data line 62, 64, 65, 66,

68, 69, ohmic contact patterns 55, 56 and the semiconductor layer pattern 42 below, at this time the semiconductor layer pattern 42 still remains under the data lines 62, 64, 65, 66, 68, 69 and below the source 65 and Between the drain electrode 66, but other parts are completely removed. The part of the semiconductor layer pattern 42 between the source electrode 65 and the drain electrode 66 is exposed and is called a TFT channel portion. In order to obtain this structure, we need a PR pattern, whose part on the channel is thinner than the part on the data line. This PR pattern can be obtained by using a photomask, and its part on the channel has Lower transmission rates than elsewhere.

After forming a PR layer pattern with a varying thickness, the layers under the PR layer pattern, the PR layer pattern, are engraved as a surname mask. First, the exposed portion of the metal layer is removed by this wet etching, and then the thin PR layer on the channel portion, the exposed ohmic contact layer, and the underlying semiconductor layer are simultaneously removed, except for the lower portion of the data line. Therefore, the metal layer of the channel portion is exposed to a thicker layer on the data line! The layer ^ is stripped to a thickness and the gate insulation layer 30 elsewhere is exposed. Secondly, the metal layer of the channel part is exposed by the wet etching to expose the underlying ohmic contact layer, and the exposed ohmic contact layer is removed by the dry etching 'and a pattern is completed. Secondly, as shown in FIGS. 41A to 41C, a passivation layer 80 of more than 3 00 angstroms is deposited by CVD (chemical gas deposition) of Si Nx or spin-coating method of an organic insulator. Four photomasks are made along the gate insulation layer 30 to produce a pattern,

Page 45 557387 V. Description of the invention (41) The drawing block 73, data block 74 and data line can be exposed. In the final step, a conductor layer is stacked to have a thickness of 400 to 500 angstroms, and I is patterned using a fourth photomask to form a conductive pattern 72, 73, 74, as shown in FIGS. 36 to 38. As described above, in the eighth example, the number of light lithographic printing steps can be reduced by fabricating a semiconductor layer pattern along the data lines 62, 64, 65, 66, 68, 69.

With the present invention, the manufacturing process of a thin film transistor array panel for a liquid crystal display can be effectively simplified, and at the same time, the gate pad and the data pad can be protected, and in addition, the leakage current of an LCD can be reduced. The typical and preferred examples of the present invention have been disclosed in the drawings and the description. Although specific phrases are used, this is general and explanatory rather than limiting. The scope of the present invention should be as described in the following application scope.

Page 46

Claims (1)

557387 6. Scope of patent application 1 · One for one Contains the following thin-film electricity used in the first array of LCDs: Steps: One-sided surface " Creative lithography process to form a line method, covering the material; using half of the guide material and the gate Use the conductors on the body layer; use the resources on the pattern; such as the quadruple purification of the gate signal of the gate line; 3, such as one of the gate signals of the gate line; a second body layer; a third electrographic pattern on the line Circuit One: The 40th application road includes the pole N and the gate pad layer. There is a layer with the application road including the pole and the gate pad;% In the insulating base lithography printing process to form a layer including an ohmic contact layer and a document. Conductor eyebrow gate insulation layer; ^ t quadruple layer in the basic light lithography printing process to form a conductive Thai pattern on the data guide to form a data uncovered data conductor layer partially etched away the uncovered ohmic contact layer; And the method of forming a passivation layer pattern in the light lithography process to form the first conductive range, wherein: a plurality of gate lines extending in a first direction are connected to one end of each gate line and from an external two As the brake wire branch; 1-way receiving scan The first contact hole to expose each brake pad; and the second contact hole to expose each first contact hole. The method of item 1 of the profit range, which: Extends to-flute. Connects to the multiple gate lines of A as the gate line branches; one end of each gate line receives scanning from an external circuit 0: \ 58 \ 58736.ptd Page 47 557387 6. The scope of the patent application has a first contact hole to expose the brake pads. The conductive pattern includes the first conductive pattern 通过, which passes through the first pad. ; And a contact hole to connect the passivation layer with a second contact hole to expose each of the first conductive patterns 4 · The method of item 1 in the scope of the patent application, wherein: the gate line includes a plurality of gate lines extending in a first direction The idler pole, and the brake pad connected to each gate line / end and from one outside = the gate line branch signal; 卩 The circuit receives the scanning data line including the line extending in the second direction to intersect the gate line, connected to each data One end of the line is received from an external circuit—a data pad with two =, a data line connected to the data line and adjacent to the source of the gate, ^ = the gate and located at the opposite side of the source; ; W, children; Ke and diarrhea are the opposite of j; ^ 1, the conductive pattern includes a plurality of first conductive patterns, which are formed on the electrode and the data pad, the second conductive pattern, Formed on the drain electrode and the pixel ί En ==; connected to the second conductive pattern and formed on the pixel electrode and the second opening exposed by the gate line and the data material to expose the current capital. The method of 4 items, in which the semiconductor layer portion between two adjacent data lines is exposed, and the first and second cattle are exposed: the exposed portion of the conductor layer facilitates the separation of semiconductors below the two data lines at 62: The method of item 5 in the patent, the pixel electrode in # is overlapped with J ^ and the part of the semiconductor layer placed between the pixel electrode and the gate line is O: \ 58 \ 58736.ptd page 48 557387 6. Scope of patent application Isolation from other parts of the semiconductor layer. 7. The method according to item 5 of the patent application, wherein the gate insulation layer includes a first part formed between the gate pads and the data pads, and the passivation layer has a fourth hole to expose the first part of the gate insulation layer. And the semiconductor layer portion located on the first part of the gate insulation layer is removed to facilitate the separation of the semiconductor layer portion under the gate pad and the data pad. 8. As in the method of claim 5 of the patent, the bean passivation layer covers the electrode edge. Eight elements and nine poles: Please refer to the method of the scope of the patent No. 5 'Among them-the open-hole exposure image I 0. If the method of the scope of the patent application No. 5 is adopted, the storage line of the serious consideration is based on its 妯 l, And, the pixel poles will be dismissed by the i ~~ On the earth material, the four layers are formed in the storage circuit ;: The semiconductor ashubeh between the storage circuit and the pixel electrode is separated from the other parts of the semiconductor layer. The burdock layer of the door is separated by a knife. II. If the patent application scope is ^ groove to expose the first conductive pattern and its poles: the purification layer has a plurality of semiconductor layers nearby, and the entrance-including U and adjacent The step of the body layer between the pixel electrodes. Except for the semi-conductor exposed through the trench 12. For example, the line in the patent application scope item η and the branch line connected to the second main line, and the gate line includes the two main points. The prime nucleus is superimposed on a part of the gate line 14. As in the part i of the scope of patent application. _ Where the conductive pattern is made by O: \ 58 \ 58736.ptd Page 49 13 · The square-shaped part and one end of the drain electrode in item 11 of the patent application scope are located, where the source electrode has a recess 557387 6. The patented transparent conductor system to make. Among them, the conductive pattern is made of indium tin oxide by the method of forming the four layers of the layer 15 as described in item 14 of the patent scope. '1 6 · The method according to item 丨 of the scope of patent application includes the following sub-steps: first; applying a photoresist layer with a thickness that varies depending on the position; applying a photoresist layer to the data conductor layer; Layered pattern; the layer is exposed to the brake pads to form a photo-resistant anti-money layer pattern and a four-layer material line with a 7 'mouth between the data and exposed data lines, and its source and drain Connect the gate insulation layers to each other. 1 7 · As for the method of applying for item No. 丨 6 of the patent scope, the first, i ϊ: ϊ? The data line whose source and pole are connected to each other: the upper part is taken between the second part. Brother-in-law, system type 18. If the method in the scope of patent application No. 6 is applied, the exposure of the basin is performed by using a photomask, which includes the photomask and the money layer. A 4-knife and its transmission rate 19 · As in the method of the patent application No. 丨 8, part of the method is to use the second light lithography process to remove one of the Y ,, and Y layers. Expose the gate circuit at u 20. If the method of the 19th scope of the patent application is applied, it will contact the first conductive pattern of the exposed end of the gate circuit. Hongtu type includes 557387 i VI. Application for patent scope 21 · As for the patent application scope No. 20 pattern, & 鎞 ^ ^ ϋ method, in which the first conductor is exposed. The contact holes are formed on the purification layer 2 ~ 2 · Q-after-type using the fourth light lithography process: the thin film transistor array panel for liquid display, including: A1,. 泉 路 'formed in one stroke. Direction of Fubei Η, ▲ ,, and Ba margin substrates, and include a brake pad that extends over a first ·? The gate electrode connected to the gate line, and the insulating layer connected to one end of the gate line, once ^ s τ 丨 & formed on the gate line and the substrate ΐ; expose the spacer block and form a semiconductor in an array shape Layer, formed on the gate insulation layer;: information line: formed on the semiconductor layer, and includes a plurality of data lines extending from a second μ == two to the gate line, a source adjacent to the gate, and a separation On the tank and the source and related to the intermediate electrode, the wave electrode on the opposite side of the source and the data pad connected to one end of the data line, a conductive pattern 'including a plurality of first formed on the source and the data line A pattern, a second pattern formed on the drain electrode, a second pattern formed on the data pad, and a pixel electrode connected to the second pattern; and a purification layer 'formed on the conductive pattern, semiconductor On the pattern and the substrate, and having a plurality of first openings to expose the pixel electrode, a second opening to expose the gate insulation layer between two adjacent data lines, a third opening on the gate pad, and The fourth opening is used to expose the third pattern; the lean line is formed only in the conductive pattern and the semiconducting Between the layers, the semiconductor layer is formed on the entire gate insulating layer, but the lower portion of the second opening separated from each other below the semiconductor layer, the part of the data lines and two adjacent lines. Page 51 557387 ^ Patent application scope 23, such as the thin film transistor array panel of the 22nd patent application scope, further comprising a contact layer formed between the semiconductor layer and the data 'circuit to have the same configuration as the data circuit, And reduce the contact circuit between the semiconductor layer and the data line. 2 4. The thin film transistor array panel according to item 23 of the patent application, wherein the conductive pattern further includes a fourth pattern connected to the gate pad via the contact hole, and the fourth opening exposes the fourth pattern. 25. The thin film transistor array panel according to item 23 of the patent application, wherein the pixel electrode is overlapped with an adjacent gate line, and the part of the semiconductor layer sandwiched between the pixel electrode and the gate line is isolated from other parts. 2 6. The thin film transistor array panel according to item 23 of the patent application, wherein the intermediate insulating layer includes a first part formed between the second gate pad and the second data pad, and the passivation layer has a fifth opening for exposure. The first part of the gate insulating layer and the semiconductor layer are not formed under the fifth opening. 2 7. The thin film transistor array panel according to item 23 of the patent application, wherein the passivation layer covers the edge of the pixel electrode. 2 8. The thin film transistor array panel according to item 23 of the patent application, wherein the first opening exposes the edge of the pixel electrode. 2 9. The thin film transistor array panel according to item 28 of the patent application scope, further comprising a storage circuit formed on the substrate, overlapped with the pixel electrode, and covered with a gate insulating layer, which is sandwiched between the storage circuit and the pixel electrode. The part of the semiconductor layer is isolated from the other parts. 30. The thin film transistor array panel according to item 28 of the patent application, wherein the conductive pattern is made of indium tin oxide. Page 52 557387 Method for manufacturing a board, including the following 3 1-a kind of thin film thunder step: lithography printing process on the array surface of the electric array to form-including a plurality of i-lines and a first insulating layer A layer on the gate line; a conductor layer, an ohmic contact layer, and a Kim = layer ^ first :::: process to form-metal layer pattern,-European layer has an array shape configuration and Cao f = type and A pattern of a first insulating layer, where a transparent conductor layer is deposited more heavily than the gate line, except for the gate pad; including-like pole formation-transparent conductor pattern, redundant data pad and redundant gate pad Block ;, several source electrodes, redundant drain electrodes, ohmic contact layers that are not covered by a transparent conductor pattern; a metal layer is divided and a second insulating layer is removed underneath; —Passivation layer pattern, straight, material, pixel electrode and connection ;; adjacent; material exposed gate pads, data-except for semi-conductive semiconductor layer exposed through holes, holes exposed; bulk layer exposed V range The method of 31 items, including-insulation ... Below the exposed part of the first-a method of manufacturing a diaphragm film transistor, eight, using a first-lithographic printing process to form-3 from the following steps: ___ G including a plurality of gate lines and gates O: \ 58 \ 58736.ptd Page 53 557387 / 、 The circuit between the patent application scope; the semiconductor layer, an ohmic contact layer and a gold layer, a first insulation layer, and a metal layer on the gate line; type The metal layer, the ohmic contact layer, the semiconductor layer, and the first insulating layer are patterned to form a metal layer pattern, an ohmic contact layer pattern, and a semiconductor layer separated into at least two pieces on a gate line, and a first An insulation pattern is applied to the gate line, except for the gate pads; a transparent conductive layer is deposited; the process of using a philosophical lithography process to form a transparent conductive layer pattern; The part of the metal layer covered by the layer pattern and the ohmic contact layer below, ，,,,, _. 乂 form a data line including a plurality of data pads, source and drain electrodes, and a pattern of contact layers below; A second insulating layer; and w, ^ ^ a fourth light lithographic printing process to form a passivation layer pattern, from the third to the third, such as the method of the scope of patent application item 33, wherein the second light lithographic printing process includes the following Sub-steps: coating The photoresist layer is on the metal layer; at least one is light, and the shirt is displayed to form a photoresist layer pattern, which has a thickness of up to 4 ^ and their thicknesses are different from each other; and one; the resist f removes the metal layer , Ohmic contact layer, semiconductor layer and the first and the second and third :: the first is: ... the thinnest part of the layer pattern contact layer, the conductor layer and ;; the factory knife to etch the metal layer, the second layer below the ohm An insulating layer, and an etched metal layer, O: \ 58 \ 5B736.ptd Page 54 557387, patent application scope Ou Qiao contact layer and the semiconductor layer below are protected by the second part, the second part is 3 5 The method exposure is performed using H, and the photomask is included to be different from each other. 36. If the method according to item 35 of the scope of patent application is used, a long slit with step resolution is used, or a material is formed. Qing # 37. If the method of applying for the scope of patent No. 36 is the first: a photomask to form a brake pad and a second photomask. The transmission rate of a photomask is different from that of the second photomask. 38. The first part of the method according to item 34 of the patent application is located on the brake pad. 3 9 · If the metal pattern, ohmic contact layer of the method pattern of the 38th item of the patent application, and the first-next sub-step: 1. Use the second and third parts as a stop to stop the metal layer and ohmic contact below the pattern. Layer, half layer; removing the first metal layer of the photoresist layer by an ashing process; and without removing the thickest part below the second part. Among them, there are three parts of the photoresist layer and its transmission rate. Among them, the photomask has at least two different rates. Among them, the photomask is divided into one to form other parts. The photoresist layer is etched away and the photoresist layer conductor layer and the first insulating two parts are removed by a piece, and the third part using the photoresist layer is exposed as an etching stopper. The exposed portions of the metal layer, the ohmic contact layer and the underlying semiconductor layer are etched away. -40. The method according to item 33 of the patent application, wherein the semiconductor layer is formed by Page 55 557387 6. Scope of patent application __—_ Made of amorphous silicon. By 4 ″ ': 定 申 方 ：. Two kinds of eight films for one liquid crystal display are manufactured by crystal array panel. Includes the following steps: · Pad: * Including multiple gate lines and multiple closed lines connected to the gate lines. — Display area and — On the substrate of the peripheral area, the gate lines are located approximately in the Song & and the gate pads are located approximately in the peripheral area; Conductor: 2 p ,: gate insulation layer, a semiconductor layer, an ohmic contact layer and -The conductor layer is on the gate line; a photoresist layer is coated on the metal layer; the position of the photoresist layer is changed by using exposure and development; the order is based on the use of a light lithography process to convert the metal Layers, ohmic contact layers, half-body layers, and inter-insulating layers are patterned at once to form a metal layer pattern, a first ohmic contact layer pattern, and a semiconductor layer pattern, and a gate pad is exposed. A conductor layer; 'using a light lithography process to form a conductor layer pattern, including a plurality of pixel electrodes to cover a portion of the metal layer, and a plurality of separate conductor layer patterns to cover other portions of the metal layer and located in relation to the gate Pixel Phase Opposite side; remove the metal layer between the pixel electrode and the separated conductor layer pattern and the ohmic contact layer below to form a data line, including multiple data lines, data pads, source and drain, and the second below Ohm contact layer pattern; and, 557387 6. Form a passivation layer within the scope of patent application. The method of applying the model is only to form a term. The Yin photoinduced anti-layer pattern is uploaded on the metal layer pattern, the photoresist layer pattern layer, the rest of the ohmic contact layer display area, and the metal layer. Contains the following sub-steps · One step of drawing the pattern of the insulating layer and the gate insulating layer Step 2: The exposed part of the metal layer of the week area is exposed to the exposed layer to remove the contact layer and the metal layer under the semiconductor ;,. · &Quot; Thinner photoresist layer in the area, in order to expose the metal layer of the display area t. The adjacent area can be exposed at once using a ^^ #knife to expose the ohmic contact layer, and In the etching method, the ohmic contact layer and the open insulation layer expose the gate pads in the peripheral area and remove the gate insulation layer to expose a portion. 'Human contact layer and semiconductor layer 44. If the method of the scope of patent application No. 42 is applied, the hole is exposed to the pixel electrode. The 8th layer of the recording layer has a 45. If the method of the 44th scope of the patent application, multiple redundant data lines are included to cover the data lines, redundant data ζ-layer pattern-packing pads and redundant gate pads Block to cover the brake pad block. 、, " To cover the capital 46. If the method of applying for the scope of the patent 45th item, love holes to expose the redundant brake pads and redundant data pads /, the dagger layer has an opening of 47. The 42-item method 'forms a step of forming a bull's spoon. The common circuit includes plural ^ 括 /, the same line, and the child pole, which can be compared with the pixel pole. Page 57 557387 Sixth, the scope of the application for a patent generates an electric field on the substrate. 4 8 · Methods for liquid crystal displays _Methods' include the following steps. = Gate line at the gate of the gate line and a formation-inter-insulation layer; type: ;;: = on the edge substrate; formation-semiconductor layer pattern on the gate insulation layer and common line; formation of an ohmic contact layer pattern Type in ^; formation-data line on ohmic contact layer = on; = connected to the source of the data line, separated from the source; plural data lines; and multiple Beco lines, but a part is not divided to form the plural The pixel electrode is connected to the non-electrode and field; ..., the u-electrode generates electricity, and the separation of the source electrode and the drain electrode is performed by using a photolithography lithography process, and the photoresist layer pattern package = etch The layer drawing system is inferior. Between the source and the drain, a second part is 4 points thinner than the first part of the 82nd part. Blade thickness and clumsiness 49. If the method according to item 48 of the patent application is adopted, the contact layer and the semiconductor layer are formed by using a photomask.束 v beam road, bee 50 · If the method of the scope of the application for the 49th item, where the gate ^ body pattern, ohmic contact layer pattern and data line layer, the following sub-steps: ~ 成 步 包 | Build the gate insulation layer , Semiconductor layer, ohmic contact layer and gray metal layer; 557387 6. Apply for a patent coverage on a metal layer; expose the photoresist layer through a photomask; ^ develop the photoresist layer to form a photoresist system on the data line; Describe the thickness of the metal layer under the third part, the ohmic points, some thickness along the part of the metal layer and the ohmic contact below to form the semiconductor pattern of the data line; and remove the photoresistive layer pattern. 5 1 · If the pattern of the square contact layer and the pattern of the semiconductor layer in item 50 of the scope of the patent application are as follows: < 'Etch 38 through wet or dry etching to expose the ohmic contact layer; Part of the underlying semiconductor layer is dry-etched to Hu Yun + +.卩 Segment of the gate insulation layer and the first part to remove the metal sounds below the first part are complete data lines and ohmic contact layers. ^ Type knife and O: \ 58 \ 58736.ptd page 59 layer pattern, the second part The first part of the contact layer and the semiconductor layer, and the pattern of the ohmic contact layer and the pattern of the ohmic contact layer and the data line and the European step include the metal layer portion below the following substeps, and the third portion of the ohmic contact layer and pattern is exposed. Lower layer; and ohmic contact layer below