TW548499B - Thin film transistor array panels and manufacturing methods of the same - Google Patents

Abstract

Disclosed is a simplified of manufacturing liquid crystal displays. A gate wire is formed on the substrate. A gate insulating layer, a semiconductor layer, and a ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, the first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than the second portion which is located on the data wire, and the photoresist layer are wholly removed on the third portion except for the first and second portions. The thin portion is made by controlling the amount of illuminating light or by a reflow process, and the controlling the light amount is done by using a mask which has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer. Next, the exposed portions of conductor layers are removed by wet of dry etching, thereby the ohmic contact layer thereunder is exposed. Then the exposed ohmic contact layer and the semiconductor layer thereunder are removed by dry etching along with the first portion of the photoresist layer. The source/drain electrodes are separated by removing the portion of the conductor layer at the channel and the ohmic contact layer pattern thereunder to complete a data wire. Then, a passivation layer, a pixel electrode, a redundant gate pad, and a redundant data pad are formed. Here, the channel portion may be formed with one shape selected from a group of shapes including a linear, a square, an open-ring, or a semicircular shape and the mask has first to third parts corresponding to the first to the third portions and a fourth part having transmittance larger than that of the first part and smaller than that of the third part and located between the first and the third parts.

Description

548499 V. Description of the invention (1) Background of the invention (a) Field of the invention The present invention relates to a thin film transistor array panel and a manufacturing method thereof. (b) Description of related technology A liquid crystal display (LCD) is one of the most popular flat panel displays (FPDS). The LCD has two panels and the panel has two electrodes for generating an electric field and interposing a liquid crystal layer therebetween. The transmission rate of incident light is controlled by the electric field intensity applied to the liquid crystal layer. In the widest range of liquid crystal displays, electrodes that generate electric fields are provided on two panels, and one of the panels has a switching element, such as a thin film transistor. In general, a thin film transistor panel array is made by lithographic printing using a plurality of photomasks, and uses five or six solid photolithographic printing steps. Due to the high cost of the light lithographic printing process, it is necessary to reduce the number of light lithographic printing steps. Even if it is recommended to use only four light lithographic printing steps, the methods are not easy to achieve. A conventional method for manufacturing a thin film transistor array panel using four lithographic printing steps will now be described. First, an aluminum or aluminum alloy gate circuit is formed on a substrate using a first mask, and a gate insulation layer, an amorphous stone layer, an η-amorphous stone layer, and a metal layer are formed on the substrate. Sequentially stacked, the metal layer, the η + amorphous stone layer, and the amorphous stone layer are patterned using a second photomask. At this time, the gate pads of the gate line are covered only by the gate insulating layer. An I TO (indium tin oxide) layer is stacked and patterned using a third mask. At this time, the I TO layer portion on the gate pad is removed.

548499 V. Description of the invention (2) After the ΓΤ amorphous silicon layer is patterned by using the patterned I TO layer as an etching mask, a passivation layer is deposited. The completed thin film transistor array panel is obtained by patterning the passivation layer and the gate insulating layer below with a fourth photomask, and removing a portion of the passivation layer and the gate insulating layer on the gate pad. As a result, the brake pad made of aluminum or aluminum alloy is presented in the conventional manufacturing method using four photomasks, but the Ming and Ming alloys cannot withstand physical and chemical stimuli and are easily damaged, although they have low resistance Advantages. To compensate for this, the brake wire is made of a multi-layer structure or made of materials resistant to physical and chemical stimuli, but the former complicates the process and the latter has a problem of material resistance to the south. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel method of manufacturing a thin film transistor array panel for a liquid crystal display to reduce the number of photomasks. Another object of the present invention is to protect the liquid crystal = display gate block. According to the present invention, a gate line including a gate line and a gate electrode connected to the interrogation line, a gate insulation layer covering the gate line, a semiconductor pattern, and an ohmic contact layer are sequentially formed on an insulating base. Wood. A data line is formed thereon. The data line includes a source electrode and a drain electrode which are composed of the same layer and are separated from each other, and a data line connected to the source electrode. A passivation layer is formed, which covers the data lines but exposes at least part of the drain electrode, and forms a pixel electrode to be connected to the drain electrode. The source / drain separation is formed using an etching and photolithography process and using a photoresist layer with three parts. The first part is located between the source and the drain and has a first thickness. , The second portion has a second thickness layer larger than the first thickness, and the third portion has a zero thickness.

548499 V. Description of the invention (3) The light used in this step-the first part that partially transmits the light ^ has two parts and is aligned in the following way ... The second substantially opaque imitation is the first facing the photoresist layer The third part is facing the third part; the second part is facing the second part, and the first part of the substantially transparent ^ reticle has at least one opaque part I 1 "a part of a transparent layer or a part The figure shows the resolution of the source. · The size is smaller than the light used in the exposure step. The photoresist layer is formed. Part of the photoresist layer can be used to reflow the photoresist layer. First, the one-half 'special & preferably has a thickness equal to or less than the thickness of the second part # part is less than 4,000 angstroms ~ the thickness of the part is} to 2 micrometers, and the first addition, 氺 宏 心 ^ first The cover can contain ~ | + resolution 5 2 its size is smaller than the first,: f at least · an opaque part of the fourth part: Shikou-the example shown + conductor pattern can be Beco line, an ohmic contact layer Figure :, ohmic contact layer pattern, J f: J,-inter-insulation layer, semiconductor hundred first integrated gate ... the shell material line is formed by the following steps: a bulk layer, and a light exposed from a semiconductor layer, an ohmic contact layer, and a light guide and exposed; a worm layer is coated on the i, and a photoresist layer is then passed through -The above second part ^ 2 forms a photoresist pattern, the path of the photoresist pattern, -ohm, followed by a conductor layer data line layer part, ohm connection; Except for the conductor contact layer, the semiconductor layer under the first and third parts, and the solution of the light source used in the exposure step between the guides and the knife. Page 9 548499 V. Description of the invention (4) _ The body part and the lower part are removed after European transport. The photoresist pattern contact layer and the upper part of the second part are formed, and the semiconductor pattern can be formed by two data lines, the ohmic contact layer pattern, and a part of the conductor layer in a wet or p 2 step. First, Below the third part, the euro-type etching under the third part is used to expose the ohmic contact layer, and then the dry money engraving is used to expose the? Layer and the semiconductor layer. The lower part of the conductor insulation layer, the lower part of the gate insulation layer, and the first and last, the completed information ^ t, the same The completed semiconductor pattern can be obtained at that time. Part of the pattern of the conductor bank = circuit and ohmic contact layer can be obtained by etching the first, here, if the data line = and the ohmic contact layer below. Semiconductor pattern Available —: dry etching, the steps of the ohmic contact layer pattern and the etching conditions ^ = the first part of the photoresist pattern thickness and dry At this time, the source and non-polar = include-straight , -L has the shape of the following one, hook-shaped, with sharp ridges, and with the crotch part of the Syrian corner, and the third part is ancient, Η-of + conductor pattern needs to be removed. Manufacturing method "Part or all of the insulation layer in the circuit of the present invention may have _ receive a 1% ^ Ge pad connected to the gate line, and self-recognized μ, bluff, the data line can present a data hot hold, _ External circuit is connected from-external circuit receives a hole; said: the material pad is connected to the data line, and: the brother-the contact hole to expose the cabinet pad and the second contact layer can-and also: at this time can be added-step Form-redundant data and then connect to the spare pad, and-redundant data pad: Pass-connected to the bead pad, redundant Brake pads

Page 10 548499 layer composition. As shown in the example, a passivation layer circuit can have a gate pad signal, and a data line and receive the body pattern from an external circuit, an ohmic contact ~ the pixel pole is composed of the following step conductor layer, an ohmic contact-the source The electrode is connected to one of the ohmic contact, the ohmic contact layer, and half of the entire surface under the drain bridge, and is shaped so that the second and third parts and the second part are located on the conductive insulating layer of the gate and A redundant data pad is formed in the second part of the photoresistance pattern. The thickness is reduced to obtain the completed data example. A gate line and an external circuit receive a message to connect to the data line. Gate insulation layer, _Semiconductor V. Description of the invention (5) The same as a pixel electrode according to the present invention-pattern formation 'a gate line and an external circuit receiving-to connect to the data line, the gate insulation layer, _ The semiconducting circuit, the passivation pattern, and a gate insulation layer, half of a subsequent data line, the contact layer pattern, and the conductive system are coated with a photoresistive layer of the conductive layer to form a photoresistive pattern pad. , And on the pole, by removing the brake The pad upper pole, a redundant gate pad, and the data pad are exposed, and the conductive bridge is exposed, and the contact layer part is a layer delamination pattern. According to another aspect of the present invention, it is connected to the gate line, and can have a data pad and a signal. At this time, a pattern can be connected to the gate line by a photoresistor, and it can have a-data pad--signal. iHl @, _ layer pattern Λ data line is formed suddenly 0 Firstly, layers and conductive layers, conductive bridges, an ohm bridge, and semiconductor pattern _ conductor layers are formed. A mask is used for exposure and development. It is located on the gate pad and the data bridge. After one field pad is exposed, one pixel should not cover the drain electrode and the gate pad. The first part is eroded. 5 The conductive bridge and the European circuit below and one ohm. Contact Φ can have a brake pad to connect to a data line-the external circuit receives the pattern one ohm contact

Page 11 548499 V. Description of the invention (6) The layer pattern, data line, passivation pattern, and one pixel electrode are formed by the following steps. Firstly, a gate insulating layer, a semiconductor layer, an ohmic contact layer, and a conductor layer are stacked, followed by a data line, a conductive bridge connecting a source to a drain electrode, an ohmic contact layer pattern, and a layer under the conductive bridge. An ohmic contact bridge and a semiconductor pattern are formed by etching a conductor layer, an ohmic contact layer, and a semiconductor layer. When an insulating layer for passivation is deposited, a photoresist layer is coated on the insulating layer, and exposed and developed through a photomask to form a photoresist pattern, so that the third part is located above The gate pad, the data pad, and the drain, and the second part is located on the conductive bridge. Second, a passivation pattern of one of the insulating layers is formed by etching the insulating layer portion and the gate insulating layer above the gate pad. At this time, the gate pad and the conductive bridge are exposed, and then the photoresist pattern is removed. . A pixel electrode, a redundant gate pad, and a redundant data pad cover the drain electrode, the gate pad, and the data pad, respectively. JtT is formed on the passivation pattern, a completed data line and an ohmic contact layer. The pattern is obtained by etching the conductive bridge and the contact bridge. Brief Description of the Drawings The related drawings are incorporated in and constitute a part of this specification, which illustrate an example of the present invention, together with a description, to explain the principle of the present invention. FIG. 1 is a configuration diagram of a thin film transistor Φ array panel for a liquid crystal display according to a first example of the present invention. Figs. 2 and 3 are plan views taken along the lines I I-I Γ and I I I-III 'in Fig. 1, respectively. FIG. 4A is a configuration diagram of a thin film transistor array panel in a first manufacturing step of a manufacturing method according to a first example of the present invention.

Page 12 548499

Figures 4B and 4C are cross-sectional views taken along the lines I VB-IVB and IVC-IVC of Figure 4A. Figures 5A and 5B are taken along the lines IVB-IVB and IVC-IVC 'of Figure 4A. A cross-sectional view of the 4C Junji manufacturing steps. FIG. 6A is a layout diagram of the thin film transistor array panel in the subsequent manufacturing steps of FIGS. 5A and 5B. 6B and 6C are cross-sectional views taken along the lines VIB-VIB 'and VIC-VIC in FIG. 6A, respectively. 7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, and 9C are examples of photoresist layers having different thicknesses. Figs. 108, 11 and 12 are the cross-sectional views of Fig. 6 taken along the line ¥ 16-\ '16 of Fig. 6 to resume the manufacturing steps. Figs. 10β, 11B, and 12B are cross-sectional views taken along the FIC-VIC line in Fig. 6A in the subsequent manufacturing steps of Fig. 6C. FIG. 3A is a layout diagram of the thin film transistor array panel in the subsequent manufacturing steps of FIGS. 12A and 12B. Figs. 13B and 13C are respectively wearing figures taken along the lines XI I IB-XI I IB, & XiiiC_X I I I C 'of Fig. 13A.

Fig. 14 is a layout diagram of a thin film transistor array panel for a liquid crystal display according to a second example of the present invention. Figures 15 and 16 are sectional views taken along the lines XV-XV and XVI-XVI of Figure 12, respectively. FIG. 17A is a layout diagram of a thin film transistor array panel in the first manufacturing step of the manufacturing method according to the second example of the present invention.

Page 13 548499 V. Description of the invention (8) Figures 176 and 17 (: are sectional views taken along lines / \\ 7116-\\ 7116 'and 乂 711 (:-XVIIC' in Figure 17 respectively. Figure 1 8 A is a thin-film transistor array panel layout diagram in the subsequent manufacturing steps of Figures 17 A, 17 β, and 17 C. Figures 18 B and 18 C are along XVIIIB-XVIII Β in Figure 18 A, respectively. And XVIIIC-xvinr lines. Figure 1 9 A is the layout of the thin film transistor array panel in the subsequent manufacturing steps of Figures 8 A, 1 8 B, 1 8 C. Figures 1 9 B, 1 9 C It is the plan view taken along the line XIXB-XIXB and XIXC-XIXC of Fig. 19 A. Fig. 2 0 is taken along the line XIXB-XIXB 'of Fig. 19 A. Fig. 19 B, 1 9 C Cross-sectional views in subsequent manufacturing steps. Figure 2 A, 2 1 B are cross-sectional views taken along the lines of FI XB-XIXB 'and XIXC-XIXC, shown in Figure 19 A, respectively. 22 and 23 are respectively taken along the line XV-XV and XVI-XVI in Fig. 14. Figure 24, 25 and 8 are taken along the line \ 1 \ 641) of Figure 19, Figure 18 Eight, 1 "the third embodiment of the present invention The subsequent fabrication steps of the wear surface in FIG.

Figs. 24B and 25B are cross-sectional views taken along the XIXC-XIXC 'line of Fig. 19A in the subsequent manufacturing steps of the third example of the present invention in Figs. 18A and 18B. Figures 26 and 266 are sections taken along the lines \ 1 乂 311 乂: 6 and \ 1 \ (: 11 '\ (:, in Figure 19) of Figure 19, respectively, in the subsequent manufacturing steps of the third example of the present invention. Fig. 27 is a thin film transistor for a liquid crystal display according to a fourth example of the present invention

Page 14 548499 V. Description of the invention (9) '' Array panel layout. Fig. 28 is a layout diagram of a thin film transistor array panel for a liquid crystal display according to the fifth example of the present invention. FIG. 29 is an enlarged configuration diagram of a portion T in FIG. Fig. 30 is a sectional view taken along the line XXX-XXX 'in Fig. 29; Fig. 31 is a cross-sectional view taken along the line XXX-XXX of Fig. 29, illustrating a method of manufacturing a thin film transistor array panel according to a fifth example of the present invention. Figs. 3, 2 and 3 are cross-sectional views of a thin film transistor array panel for a liquid crystal display according to the sixth example of the present invention taken along the lines I I-I I 'and I I I-π Γ in Fig. 1, respectively. Figures 3A and 3B are cross-sectional views illustrating the thin film transistors in the subsequent manufacturing steps of the sixth example of the present invention, taken along the lines VIB-VIB and VIC-VIC 'in Figure 6A. Array panel manufacturing method. Figures 3A to 3C are partial channel layout diagrams of the second photomask used in the manufacturing method of the thin body transistor array panel of the example of the present invention. Figures 3 6 A and 3 6 B are photoresistance | insect diagram views formed through the masks of Figures 3 5 A to 3 5 C, and Figure 3 6 B is taken along line XXXVIB-XXXVIB of Figure 3 6 A. The cross section taken. Figures 37A to 37C are partial channel layout diagrams of the new second photomask used in the manufacturing method of the thin film transistor array panel of the example of the present invention. 38A and 38B are photoresist pattern views formed by the photomasks of FIGS. 37A to 37C, and FIG. 38B is a cross-sectional view taken along the line XXXVI I IB-XXXVI I IB in FIG. 38A. Figures 3 A through 3 9 C are used in the fourth example thin film transistor array panel of the present invention

Page 15 548499

V. Description of the invention (10) The second photomask in the manufacturing method has a D-house dark. The channel part of the long structure is shown in Figures 40A to 40E. The second photomask with a transmission control layer used in the method of the present invention is a manufacturing method of a 3-core array panel. Figures 4 and 4 2 It is used in the fourth embodiment of the present invention. The layout of the channel part of the second photomask in the manufacturing method.% Crystal Array Panel System For a better implementation example, the present invention will be described with reference to the related drawings. However, the present invention is limited to the implementation example described in the text. 'The person who explained the invention and learned the thickness of the field for this technician has been enlarged for clarity. It can be understood that when one yuan is on another element, this is an intervening element; otherwise, when There is no intervening element at the gate. The month is as follows. The figure reveals this issue: it is implemented in different ways, and it is not used: the example can be used to fully and completely explain its Fan Tianshou. In the diagram, the same number in the layers and areas The same element such as a layer, region or substrate may be referred to as directly on another element or a component may be referred to as being directly on another element, by forming a photoresistance in the step of separating the source from the drain The etching pattern has a thinner part between the electrodes, so the manufacturing steps are reduced. Figure 1 is a layout diagram of a thin film transistor array panel for a liquid crystal display according to the first example of the present invention, and Figures 2 and 3 are along Figures II-II 'and III-III' taken on the surface. A metal or conductive material such as Ming (A 1) or Ming alloy, key (μ 〇) or indium (Mow) alloy, chromium ( Cr) and button (Ta) gate circuit is formed on 4 insulating substrate 10, the gate circuit includes a gate extending in the horizontal direction shown in Figure 1

Page 16 Fifth, description of the invention Π1), spring (―known signal line) 2 2 connected to the gate line 2 2 ㊇ head — external circuit to one of the gate block 22 gate block and also send a scanning signal The common voltage of one of the gates 26 and the gate 22 is connected in parallel to the gate electrode 22 (not shown) as a thin-film transistor. The storage electrode 28 is connected to one of the panel 82 and the storage capacitor, and is described in detail later. The liquid crystal capacitor includes a common electrode for the pixel electrode. If the storage capacitance between the pixel electrode 82 and the gate line 22 is sufficient, the storage electrode 28 may not be used. Office = line 22, 24, 26, 28 can have a multilayer structure and a single layer = only, when the gate line 22, 24, 26, 28 has a multilayer structure, it is best _ 上 由, = resistance material The other layer is made of materials that can be in good contact with other materials, such as chrome / aluminum (or aluminum alloy) and aluminum / molybdenum double-layer materials. 9/1 A gate insulation 130 made of silicon oxide (SlNx) is formed on and covered by the question lines 22, 26, and 28. A semiconductor pattern 4 made of ^ ΐ ^ body (such as hydrogenated amorphous silicon) 4 2, 4 8 on the edge layer 30 '(made of, for example, a large amount of impurities and petrochemicals / amorphous silicon) ) An ohmic contact layer pattern 5 5, 5 6, ^ is = formed on the semiconductor layer pattern 42, 48. 56 Two conductive materials such as molybdenum or molybdenum tungsten, chromium, aluminum, or aluminum alloy are formed on the ohmic contact layer. Patterns 5, 5, 6, 5, 8 Injury, including a shell line 62 that extends from the water shown in Figure 1, a video signal connected to the data line 6 and the direction of the thousand feet to the fifteenth day of the week 2 2 4 circuit transmission of the night field a " thousand The poor material pad 64 and one are used as the source of the data poem + 溥 fe transistor source 6 5. Zi, Qin, and Quan 6 2 branch line Quan Lu also includes the thin film transistor-wave 548499 V. Description of the invention (12) The pole 6 6 'is located on C and separates the channel part on the y side or the thin film transistor 28 Shangxin, 65; and-located in storage 7 for: ,, conductor pattern 68 also; for ^ " pattern 68. When the storage electrode 28 has a multi-layer structure of the 62, 64, and 65 n circuit parts, when the lean circuit layer is made of other low-resistance materials, and the other-ohmic : Made of materials with good contact. Human interface layer patterns 55, 56, 58 Body patterns 42, 48 and corresponding data lines: The role of 2 is to reduce semiconducting

65, two: I have the same! The material line part H ohmic contact layer part 55 has a phase;: the first part below the f part, the first part below the drain part: 4 parts 6 2, 6 4, 6 5 the shape of the pole 66 The shape and conductor pattern; K 3 :: part 56 is the same as part 5 and a half 8 = same as the conductor pattern contact layer part of the storage capacitor + ¥ μ patterns 42, 48 have the same shape. 634: 65, and the corresponding ohmic contact layer diagram. Line 5: Part 6.2, except for channel part c, which is a bay film transistor, or the configuration of / 55 ″ 6, but the conductor pattern 68 and the third ohmic contact two and two semiconductor parts (shape, but semiconductor Part 42 has a shape of 2: 158¾ with the same contact pattern. The county _ ^ is the same as the tributary line and the ohmic source input and the non-polar 6 pass; the parts 62, ", 65 are especially away, and the electricity below The passage part c is separated from each other and the contact layer pattern parts 55 and 56 are also separated from each other. ”P.18 548499 V. Description of the invention (13) 疋 = Guide opening F injury 4 2 Asia is not divided into two, so In other words, the transistor passivation layer 70 is formed on the substrate. The passivation layer 70 has contact holes 71 / = W 64 Μ, 66, 68 66, data pad 64, and :: U2: 3: 74. The polarizing layer 7 is exposed separately. The insulating block 24 can be exposed by the insulation 72. Pure other transparent light ::; into _ ;: such as inspection, acrylic organic materials, for receiving-== and ^ Organic material. The pixel electrode 82 is formed on the passivation layer = the electric field 71 and is connected to the drain electrode 66 in a qualitative and electrical manner, and it is connected to the contact hole Xun. When the image The pole 82 overlaps / the pole receives an image diameter ratio increases, but when it is necessary, although the hole is connected by the contact hole 74 to the pixel electrode 82 for transmitting the image signal to the conductor pattern 68. Large .... of- Body type 68, and connected to the open pad ⑽ and 分别, respectively, and more than one question pad 8 4 and a redundant bell: Cangzu's percent. 0 block 24 i data 埶 诒 μ & Yu Beike block 86 is formed in The brake pads, 64 redundant blocks 84, 86 are used to protect the lumps of lumps .... work ... between the external circuit and the blocks 24, 64. Adhesive 2iIT0 is an example of the pixel electrode 82 material, but Electric materials can also be used in reflective liquid crystal display thin film transistor array panels according to embodiments of the present invention: Manufacturing method will

Page 19 54M9 ^ V. Description of the invention (14) Description will be made with reference to FIGS. 4A to 13C and FIGS. 1 to 3. First, as shown in FIGS. 4A to 4C, a metal conductor layer is deposited on a substrate 10 by a method of occlusion to a thickness of 1,000 to 3,000 angstroms, and includes a gate wire gate. The gate circuit of the pad 24, a gate electrode 26, and a storage electrode 28 is formed by using a dry or wet coin of a first photomask, as shown in Figs. 5A and 5B. A gate insulation layer 3 〇, a semiconductor layer 40, and an ohmic contact layer 50 are sequentially deposited to 1,500 to 5,000,000, 500 to 2, respectively, using, for example, a chemical gas deposition (CVD) method, 〇 00, 300 to 600 Angstrom thickness, and then a metal conductor layer 60 is deposited by sputtering method to a thickness of 1,500 to 3,000 Angstrom, and a thickness of 1 to 2 microns of light A resist 110 is applied to the conductive layer 60. 1 The photoresist layer 110 is formed through—the second photomask is exposed and developed—iLf patterns 112, 114, as shown in FIGS. 6B and 6c. At this point, the first part of the L-etch pattern 114, which is located between-source 6 5 and 1> and 6 β, is the first part 114 of the L etch pattern, that is, the figure is not uniform. Part C of the transistor channel, which is thinner than the line 62, 64, 65, 66 to be formed. Few times. 112, and the remaining part of the photo-induced anti-money pattern above the first-^^ road material, the bean line, that is, the photo-induced anti-engraving method located in part 6 has -thickness:,. The third part can be described as having a thickness of approximately zero, as a result; the point has a degree when using wet engraving, and at this time, the -part 114 has a non-zero thickness at the rest of the Λ type. Money carved status, detailed ,. "The thickness ratio between coffee is determined by or smaller than the brother of the second part 112-the thickness of the part 114 is the best. There are many ways to depend on the position," or for example less than 4, _ Angstrom. The thickness of the anti-surname layer, and the following

Page 20 548499 V. Description of the invention (15) Two methods of using Erguang to induce anti-surname agents. As shown in FIGS. 7A to 7C, the first method is to control the amount of projected light by forming a pattern such as a long slit or a grid, which is smaller than the resolution of the exposure device ^ or by providing a part of a transparent layer to the light Hood. First, as shown in FIG. 7A, a photoresist layer 200 is coated on a thin film 300 on a substrate. At this time, the photoresist layer 200 is thicker than normal. Thickness of the photoresist layer. & Secondly, as shown in FIG. 7B, light passes through a photomask 400 having a plurality of slits 41 and irradiates the photoresist layer 200. At this time, the size of the slits 41 and the slits The opaque portions 42 are smaller than the resolution of the lighting system. When a part of transparency is used, a chrome layer (not shown) is left on the mask 400 of a certain degree to reduce the exposure. Alternatively, you can also use "a mask that includes films with different transmission rates. __ When the photoresist layer 2000 is exposed, the polymer of the photoresist layer 2000 is disintegrated from the surface by light, and When the amount of light increases, even the meaning of the polymer is resolved. When the polymer at the bottom of the directly exposed part is completely decomposed, that is, as shown in Figure 7B, the exposure steps are completed, but Take the photo of the photoresist layer close to a photoresist layer which is exposed through the slit pattern 4 1 0 and the 5 objects at the bottom are not decomposed 'because the amount of projected light is less than the direct exposure part t: if the exposure time is too long' then all light The polymer of the resist layer 2000 is disintegrated, so it should be avoided. In FIG. 7B, the number 21o indicates the disintegrated portion and the number 22o indicates the portion that has not yet acted. The photo-resistant rice layer 2 1 〇 After the 2 2 0 development, only the non-disintegrated portion 2 2 0 remained and the upper crotch injury remained in the center, because the exposure here was less than complete

Page 21 548499 —-—----- V. Description of the invention (16) Exposure section. The second method of changing the thickness of the photoresist layer is explained by using reflow according to the examples shown in Figs. 8A to 8C and Figs. As shown in the figure, the two portions 21 and 22 of a photoresist layer are exposed by a mask with 8 degrees and an opaque portion at 4 °, and the portion 21: H "is the disintegrated portion. , And the other ㈣. For all: and 幵 η: shares. Then 'as shown in Figure 9β' =-light with a portion of zero and non-zero thickness': member: reproduction of anti-surname pattern, pass = if the remaining thickness of the anti-money agent. Photoinduced & π ^ 仃 仃 ran into the pre-resistance part 22 0 into the zero-thickness production F i to form a new photoresist pattern 25.0. 7 each However, if the photoresist part is burned between 22 and 0, the sores are reflowed and completely covered with photoresist, so that the opaque pattern of the exposure device resolution cannot be used. 43 The shape is smaller than that shown in Figure 9A. Then, if it is between the thicker part 2 and 20, the dream is re-introduced: Li Yi, a relatively restrained part "0-shaped dry dwelling mouth P injury and a thinner part is located Thicker-type 2 3 0 is formed. .丨 77 Photoresist Maps When using the methods, you can get them at different locations. The photoresist pattern with various thicknesses is shown in FIG. 6C. The photoresist pattern U4 and 苴 60, the ohmic contact layer 50, and the semi- and:, and the conductor layer are included below. When this is done, its layers are then passed through the Baifeng W layer on the transportation section C. In addition, the rest on page 22 548499 V. Description of the invention (17) The three layers 60, 50, 40 in part β are all from The gate insulation layer 30 is removed. As shown in Fig. 10 A, 1 ο Β, part of the β ohmic contact layer 5 〇 is exposed by removing the conductor layer 60 above it, at this time both wet and dry etching can be used, and the etching f is The conductive layer 60 is etched and the photoresist layers u2, 1-4 are not etched. However, 'this is extremely difficult to achieve in dry engraving, rice can be carried out in a state where the photoresist pattern 丨 丨 2, 丨 丨 4 is also eroded. At this time, the first wound 114 can be made thicker. In the case of wet etching, the conductive layer 60 is not exposed. If the conductor layer 60 is made of molybdenum or molybdenum-tungsten alloy, aluminum or aluminum alloy, or button, then wet or dry etching methods can be used. However, if the conductor layer 60 is made of chrome, then wet Etching is preferred because chromium is not easily removed by dry etching. CeNHO, 3 can be used as a wet etchant to facilitate the engraving of a chrome conductive layer 60, and a mixture of CL and HC1 or Cl and% ^ gas system can be used for dry etching or I mesh tungsten conductor layer 60 'in this case The etching rate of the next system on the photo-resistant layer is similar to that of the conductive layer β 0. Meal reading Fig. 10A, 10B 'Results are only used for the source / in the channel part c and the data line part B ;: and the photoresistor of the storage capacitor-and the capacitor under the 114 The 60 part is still left, and the remaining part of the conductor layer 60 in the part 6 is completely removed to expose the ohmic contact layer 50 below it. In the case of daggers, the conductor patterns 67 and 68 have the same configuration as the data line parts M, M, π, M, and M, except that the source 65 and the pole 66 are connected to each other. & With dry etching, the photoresist layers 112, 114 are also etched to a specific thickness. Secondly, in FIGS. 10A and 10B, the ohmic contact layer 50 of the part B and the semiconductor layer 40 and the like under the part B have been dried along the first part 114 of the photoresistance layer.

Page 23 548499 V. Description of the invention (18) The type of etching is removed, as shown in FIGS. 1A and 1B. The etching state is photoresist pattern 112, 114, ohmic contact layer 50, and semiconductor layer. 40 is etched away (semiconductor layer and ohmic contact layer have almost the same engraving rate), but the gate insulation layer is not engraved, the photoresist pattern 丨 丨 2, 丨 丨 4 and the etch rate of the semiconductor layer 4 〇 Almost the same, this example is a mixed gas system using SF6 and 11 (: 1 or SF6 and 02. When the etching rates of photoresist pattern Π 2, 1 1 4 and semiconductor layer 40 are almost the same, the first part The thickness of the part n 4 may be equal to or less than the sum of the thicknesses of the semiconductor 40 and the ohmic contact layer 5 0. As shown in FIG. 11A and 11B, the conductor pattern 67 is exposed by removing the first portion 114 of the channel ^ Now, the gate insulation layer 30 is exposed by removing a portion of the ohmic contact layer 50 and the semiconductor layer 40, as shown in FIG. 11β. At the same time, the data is 1 and the second portion above the A. The thickness is reduced by etching. These two 丄: f $ semiconductor pattern 42, 48 取得 obtained in the steps. No. 57, six: 'represents the conductor diagram Below 67 and 68 are the ohmic contact layer patterns for source / drain and storage type. The remaining conductors on the conductor pattern 6 and 7 are y "$. Divide them. W Yujiu resist layer is grayed again. Or plasma etching to remove pen I gas or microwave is used in the ashing step.… -1, and lice gas is mainly used. Secondly, as shown in Figures 1 2A and 12B, the figure of sound and sound is 67. And Figure 11B is used for source two KC for source / drain lead removal. At this time, the dry ohmic contact pattern 57 can be etched with the money contact layer 57 'or wet etching method; = body pattern 67 and ohmic connection to etch the ohmic contact layer 57. The front _ t main sink middle = return type 67 and dry etching moon / zhonglang good use in the conductor pattern 67 548499 V. Description of the invention (19) between type 57 A large narrative selective narrative state, this # i ^ ",] A # " j ^^^ and 〇2 mixed gas system to achieve ° ^ 42 thickness, which can be used, for example, in the latter case, the > Ό Wet engraving using wet money and dry money engraving, but using dry money to engrav the conductor pattern 67 on the horizontal side is also divided. 'In addition, the two patterns 67 and the contact layer pattern 57 are geometrically non-corrosive. The contour of the gas field A can be formed into a class-like shape by using the gas system. Cf4 and 〇? Mixed money carved gas system real: carved;; = 4 Figure 2 type 57 and the semiconductor pattern 42 body system appears in the remaining moment Lifting ^ Γ type 2 can also use CF4 and 〇2 mixed gas pattern 42 of the wide production two = sentence uniformity, as shown in Figure 12β, at this time the semiconductor # 刻 至 -ί 少, and the light induced resistance to the surname The second part of the pattern 112 is also 30, and it is restored. The M condition can also be a continuous insulation layer, M, 62: 6 " 5 parts 6; fruit 64 source ^, 5 = drain 66, and obtained Done ^^ 58. , 68, and the completed contact layer patterns 55, 56, (Figure "Removal of the remaining second part 112 of the photo-resistant anti-money layer on the data line, area 112 in Figure A), but this removal of the second part 112 may The part of the channel that is not in the Fengguang map (; ± the source ㈣ conductor pattern ^ step after the step / line. Except the conductor pattern 67 below the ohmic contact layer pattern 57 step forward or = use available wet dry type ❹丨 Sequentially, Μ fiber Page 25 548499 V. Invention description (20) — In the former case, the conductive layer of part B is firstly wet-etched to remove the contact layer and the semiconductor layer below it, and then dry-etched. ， 人 JL 于 ，， J: ΘΘ 丰 卩 么 > The photoresistive recording layer of C is assumed to be a certain thickness, and part of the [photoresist that can be left in the factory depends on part C The light / 〃, ,, and any thickness. When part C has a residual photoresist, residual = 7 Initial: 丨 :: Removed by ashing. Finally, the conductor layer of part c is open source. Electrode and drain electrode, and the ohmic contact layer of part c is dried up. In the case, the fine conductive layer and European-style rice carving are removed. As in the previous case, Part of the heliocentric = photoresist with a wicked edge, and when there is or can be used ashing to remove the residual photoresist / σ /, / with a residual edge photoresist ^ ^ ,, ~ left first The resist is removed. Finally, the source layer of part C is separated by two types of dry worms, and the source electrode is removed by dry etching. The core contact layer is further removed. The material line can be formed in one time + ¥ limb pattern, contact layer pattern and 114 and lower contact layer 50 to form 'i.e. part 0 of the photoresistance shoe pattern conductor layer, ohmic contact f engraving' and In Part B of Carved Dry Rice

The pattern Π2 part also makes dry a and rice. During the body layer, the photoresist of part A is only simple to obtain the correct etching because of the latter process & —an etching method ', so it is relatively simple but difficult to get the correct etching. Second, the converse, the advantages of the previous process The easy way is to use the above steps to 'complicate capital. After the use of 2,000 Å or more factory shell / + wire parts 62, 64, 65, 66, 68, Ziyou's passivation layer 70 is CVD method using Si Nx or 548499 V. Description of the invention (21) Organic It is formed by spin-coating method of ·, 彖, 彖, as shown in Figure 1 3 A to 1%. Divide: and pole 66, idle pad 24, data pad and storage type = contact holes 71, 72, 73, 74 of type 68, and then; cover: passivation layer 70 and insulating layer 30 are formed. -Produce it first: Lee: 1 ~ i as shown in 1 to 1 layer stacking is 4 0 to 5 0 0 Angstrom ^ ^ ^ ^ ^ ^ ^ ^ four hood etch to form a pixel pole 8 2, a redundant gate pad Earn 84 and a few more data pads 86. The sentence block is as follows: In the first example, the data lines 62, 64, 65, 66, and 2 / touch patterns 55, 56, 58 and semiconductor patterns 42, 48 are used. In this step: In the middle of the step: In the example, the source electrode and the non-electrode electrode are formed in the step of forming a passivation layer. One of the second examples of the present invention is a liquid crystal display device and 1 1 to 2 1 B. Fig. 14 is a layout diagram of a panel of the second example of the present invention, and Fig. 15 is a cross-sectional view of the film transistor array hi. 6 仏 Don't follow xv-xr and XVI in the figure. As shown in Figures 14 to 16, this example is the same as the thin-film transistor panel of the first example: ‘quasi-one body panel structure is similar. With-openings 75 to expose source 65 and non-polar difference = in passivation layer type 42 and passivation layer 7 () (covered with pixel electrode δ.), Semiconductor block 84 between 6 and redundant data pad Block 86 is slightly omitted (with the exception of stings), the source of the redundant gate pad is separated from the non-pole, and is opened; At this point, the opening 75 is completely covered by a subsequently formed alignment layer and the exposed semiconductor pattern 42 will be covered.

Page 27 548499 V. Description of the invention (22) The thin film transistor array panel according to the second example of the present invention is illustrated in the above 17A to 21B and FIGS. 14 to 16. First, as shown in FIGS. 17A to 17C, a gate line 22, a gate electrode 26, and a storage electrode 28 are used in a first ancient manner. The first cover is formed on the substrate 10, and the second one, as shown in FIGS. 18A to 18C, is a gate insulation layer 30 ′ 40 and an ohmic contact layer 50, which are sequentially equal to the body layer f. After the CVD method is applied and the ¥ 60 layer (for example, a metal) is used for low-level emission, there is no conductor pattern for the source / drain electrode 6 7,1. Ohmic contact layer pattern 5 with source / drain electrode, 7 or 12 V 脰 pattern 6 7 conductor pattern 42 below, a half-body pattern 68 for storage type electric six cry field and one film transistor 68 The following Europe for storage capacitors :::: 68,-The semiconductor pattern for conducting storage capacitors is priced at 2 :; 58 and-supply and output patterns are formed. Alas, it is used for source / drain: firstly, the mask is sequentially manufactured on the structure of a completed thin film transistor, and Gusheng 67 has the same connection. What's more, the source and the drain are connected next. As shown in FIGS. 19A to 19C, the passivation layer 70 of a giant 74 and an opening 75 is formed using a second number: 72. At this time, the passivation layer Thickness p of 70% —The passivation layer 70 on the crystal channel portion C is first covered with a pattern, and the position of the passivation layer 70 is changed. The thin passivation layer is relatively thin; ^ is thin. Second, the contact holes 71, 72, 73, 74 and the openings 75 between the source 65 and the drain 66 are shown in the same way as in the first part. . Photoresist method with multiple thicknesses in fabrication examples of resist patterns 112, 114 with multiple thicknesses, but the photoluminescence in the first example

548499 V. Description of the Invention (23) ___ The resist pattern 112 and U4 are removed, but the bluntness in this example is part of the thin film transistor panel. .. ㈢70, then as shown in FIG. 20, 'the spacer 24 is exposed by removing the gate insulation ⑽ :: removed' At this time, the etching state is preferably set to ㈣, but the passivation layer 7 and the conductor are not etched. Patterns 67, 6 and '' Bao Qiao make passivation layer 70 and inter-insulation layer 3 from different materials. However, it is better to use the passivation layer 7 if the passivation layer 70 is also etched. Thicker than positive i: as shown in Figures " and Figures m and 21B 'A pixel pole 82, an upper block 84, and a redundant data pad 86 are conductors that are stacked using a first and a fourth photomask The layers are patterned. .toa is used as shown in FIGS. 15 and 16. The passivation layer 70 is then dry-etched to form an opening 75. The etching is completed by using the pixel electrode 82, the redundant gate block ^, and the redundant block 86 as the etching stopper. At this time, the etch-like history is determined. 'The ending point of the last name is the car when the purification layer 70; the thin part: (the part of Qiong Qiao 70) is completely removed and the conductor for the source / drain is shown in Figure 2. A photo-induced "_" can make the pixel electrode , And redundant data block 86 is a "engraved stop, not f." For the wound itself, this pattern can be used in any subsequent steps and == pattern 67 and the ohmic contact layer pattern 57 below. The source 65 and / or the electrode separation method is the same as in the first example. However, what is different from the first example is that the redundant brake pads take 8 6 as an important part in this example. This' 64 appears without redundant blocks 84, 86, then = 塾, and data blocks. J to Ghost ^ 4, 64 will be divided in the step of separating the source 65 548499, the invention description (24) and the immortal 66. Next, the liquid of the third example of the present invention is described with reference to FIGS. 22 to 26B. Second, you can use the reference layer to make the passivation layer into a pattern, but it does not have any separated light due to the thin film transistor panel in this example ^ f In this example The red picture of the thin crystalline transistor panel of this third example is shown in Fig. 14 and 23, and the latter is the third embodiment of the present invention. XV-XV will be referred to Fig. 14 and Fig. 22 , And XV and XVI, taken from the line. The cross-sectional view of the FAW example is shown in Figure 14 as shown in Figures 1, 2, 2, and 3. This example "is similar to the second example, but it is different from & The structure of the film transistor panel is near the pixel pole 82, the redundant gate pad, and the redundant two = the example is that it is not covered and not etched. ', The passivation layer 7 6 of the lean pad 8 6 and the thin film electrical crystal barrier of the third example of the present invention are shown in FIGS. 24A to 26B and FIGS. 14, 22 and 24. 24, 26, = Mingzhi. Conductor pattern 67 for source / drain electrodes-Gate insulation layer 30, One-m contact layer pattern 57-For thin-film transistor 7-body figure ^ European ohmic contact for storage capacitors The pattern 42 and the semiconductor pattern 48 of the device use the same 8 = for storage capacitors. This method is consistent with the conventional method: To: Γ 24A, 24B, a passivation layer 70 is deposited or coated, two layers are coated on the passivation layer 70, and then the photoresistance layer is transmitted through. Photographic development to form a photoresistive pattern 122, 124, " Protozoan pattern 122, 124 is intended to be a contact hole 71, 72, 73, 548499 5. Part of the invention description (25) 74 has Zero thickness' and want to be-the portion 124 of the opening 75 is smaller than the portion 122. As described above, the photoresist layer having a plurality of thicknesses is made in the same manner as in the first example. Subsequently, as shown in FIGS. 25A and 25B, the thinner photoresistive layer 1 on the channel 1 and the lower passivation layer 70 are along the exposed passivation layer 70 and the gate insulation layer 30 under the exposed passivation layer 70. However, since the remaining state is provided with the passivation layer 7G and the gate insulating layer 3G, the phase layer 70 and the gate insulating layer 30 are preferably used. π takes pure dagger to obtain the completed contact holes 71, 72, 73, 74 and opening 75, and the conductor pattern 67 for the source / drain is exposed through the opening 75. Secondly, as shown in FIGS. 16, 26A, and 26B, the photoresist pattern 122 is removed by stacking an ITO conductor layer, and then the conductor layer uses a fourth photomask coin-shaped pole 8i, which is a redundant block 84, and redundant data. The reason for the consistent example of the pad, the redundant gate pad "and the redundant data pad 8 2 are shown in Figures 14, 22, and 23. The source 65 and the drain pole ⑽ are exposed through the opening 75. The supply / discontinuity conductor pattern 6 is completed by tearing the ohmic contact layer pattern 57 below. This and the example are shown in the example. 『% 弟 —— Ben, Ming, and one of the four examples The manufacturing method will be explained as follows, # = 日, which presents a liquid crystal display with a U-shaped channel portion c, and its description will be referred to FIG. 27. This example is less than this example, two or three examples. A bright liquid Figure 27 is a thin film transistor for a crystal display of the fourth example of the present invention 548499 V. Description of the invention (26) Array panel layout. As shown in Figure 27, most of its structure is the same as that of the first example. However, the source 65, which is the branch of the data line 60, extends so that it overlaps slightly on the two edges of the gate 26, so the data line 62 and the source 65 are associated with the three sides of the U-shaped channel portion C. The drain 66 in this example extends in the opening portion of the U-shaped channel portion C. This structure can obtain a wider channel portion width, but its area is smaller. Since most of the cross-sectional structure and manufacturing method of the thin film transistor array panel for the liquid crystal display device of the fourth example are the same as those of the first example, the details will not be repeated. However, if the U-shaped channel part C has an acute angle or edge, the photoresist pattern 1 1 4 cannot have a uniform thickness because of the diffraction phenomenon of light generated in the edge of the channel part when the channel part C is exposed. . That is, if the channel part C is J-shaped and has a corner 隅, and the two straight parts of the joint are in different directions, the light on the edge of the channel C is projected because the light on the edge is diffracted. The amount is different from the other parts of the channel part C, and accordingly, the thickness of the photoresist pattern 1 1 4 is not uniform after development. At this time, if the corner part is thinner than other parts, the quality of the thin film transistor will be deteriorated, and if the corner part is thicker than other parts, it will form a connection source electrode 6 5 and φ drain. Thin film transistor with electrode 6 6 (or contact layer pattern 5 5 and 5 6 below). According to this, the semiconductor pattern of the corner part of the channel part C is removed by removing the photoresist pattern, as in the case of the part B of the first example, which will be explained in the fifth example. A thin film transistor array panel according to a fifth example of the present invention will be referred to FIGS. 28 to 30.

Page 32 548499 V. Description of Invention (27) Explained. FIG. 28 is a layout diagram of the fifth and first array panels of the present invention, and FIG. 29 is a thin-film transistor for a TFT display of FIG. 28. FIG. 30 is taken along the line XXX-XXX 'of FIG. 29: : Τ enlarged configuration diagram, and as shown in Figures 28 to 30, the thin cut-out drawing of the thin cymbals. Four instances. Most of the structure of the solar body is the same as the first one, a source 65 and a question 66-,,, and a semiconductor pattern has openings 4: Through this part C has a 匸 -shaped edge Layer 30, one of the corners of the channel c * now part of D is completely removed from part D.半导体 The semiconductor pattern here is the thin film thunder θ of the fifth example of the present invention, θ, +,, and the sun and sun limbs' array panel 4 #, the table must be done & described above with reference to FIGS. 28 to 30 and FIG. 31 . The drawing V is to draw Lingling Figure 31 along the XXX nxu line in Figure 29 to take 7 kg to illustrate the manufacturing method of the thin crystalline transistor array panel of the fifth example, illustrating the present invention ▲ manufacturing method of the thin film transistor panel of this example Similar to film transistor panel. The only difference between this example and the method is that the photoresist layer 110 is coated and exposed through a second photomask, and developed to form the photoresist pattern shown in FIG. 31- Type 11 2, 11 4 at this time, the photoresist is completely removed in the corner portions D and B of the channel portion c. As described above, the light irradiated at the corners of the channel part c, 77, part D, is different from other parts of the channel part C due to the edge effect light diffraction phenomenon, and can be formed to have an uneven thickness. The semiconductor pattern 'or the source 65 and the drain 66 (or the underlying contact layer patterns 55 and 56) may not be completely separated. Therefore, when a sufficient amount of light is irradiated, the photoresist of Part D

Page 33 548499 V. Description of the invention (28) The pattern is completely removed, so the semiconductor pattern of part B is completely removed. Here, the second part of the data part A 1 1 2 has the data line part 6 2 , 64, 6 5, 6, 6, 6 8 and includes a 匸 -shaped source electrode 6 5. Secondly, in a similar manner of the first example, the exposed conductor layer 60 of the remaining portion B and the corner portion D of the channel portion C are etched, and the ohmic contact layer 50 and the underlying semiconductor layer 60 are along The first part 1 1 4 of the photoresist layer is dry-etched, and then the source electrode 65 and the electrode 66 are separated, and the semiconductor pattern 4 2 is exposed between the source electrode 65 and the electrode 66. Accordingly, if the semiconductor layer in the corner portion of the channel portion C is removed, the semiconductor pattern 42 of the channel portion C can be uniform. Lu In this example, the drain electrode 65 extends to the opening of the source electrode 65, but its position can be changed. In the fourth example, a channel portion having a U or J shape is formed, and since it is convenient to adjust the irradiation light amount of the channel portion =, the semiconductor pattern portion between the source 65 and the drain 66 cannot be removed. The mask structure used to form the photoresist pattern 1 4 of uniform thickness will be described in detail below. On the other hand, in the same manner as in the first example, the conductor layer 60, the contact layer 50, and the semiconductor layer 40 of part B are removed, and the gate insulating layer 30 of part B remains. However, a part or all of the gate insulating layer 30 of Part B can be removed, and a manufacturing method of removing all the gate insulating layers 30 of Part B will be explained by a sixth example. 3, 3 and 3 are cross-sectional views of a thin film transistor array panel for a liquid crystal display according to a sixth example of the present invention, and are taken along lines I I-I Γ and I I I-I I Γ in FIG. 1, respectively. Most of the structure is the same as that of the first example.

Page 34 548499 V. Description of the invention (29) = As shown in Figures 32 and 33, there is only a semiconductor pattern 42 Insulation layer pattern 3 2, 3 8 capture, Ertun miscellaneous 0 million yuan gate S Baoyuan Patterns without gate insulation layer 32, μ substrate 10 and gate line part 22, 9R 90 ai, and so on, Japan, Japan, and Japan 26, 28 are covered with passivation layer 70. / Yuedi /, Bayan's crystal transistor array surface Figures 34A, 34B, 32, and 33 described above. Figure 34A and 34B are cross-sectional views illustrating the manufacture of the sixth example thin film transistor array panel of the present invention shown in FIG. 10A; do not take along VIB-VIB and VIC_VIC line of FIG. 6A. And, as shown in Figure 2 of the knife β, / °? Shows the manufacturing process of 16 examples until the ¥ limb layer 60 of the engraved part 3 to expose the lower ohmic contact layer 50 to the first example. 1 is only added. However, the difference between this method is shown in Figure 34A and 34β. The remaining exposed contact of 1 Β, the semiconductor layer 4Q and the insulation between the bottom ^ along the first part of the pre-resistance pattern Part 丨 14 etching, in order to expose the current source / body pattern 67 and form the gate insulation pattern 32, 3δ and semiconductor pattern 42: ¥ Secondly, as shown in Figures 32 and 33, the data line parts 62, 64, 65. 68 and the lower ohmic contact layer patterns 55, 56, and 58 are completed by separating the source electrode and the drain electrode 66. The passivation layer 70 is formed with contact holes 71, 72, 73, and 74 to expose the drain 66, the gate pad 24, the data pad 64, and the conductor pattern 68 for the storage capacitor, respectively. SiNx, made of storage materials, and ITO pixel poles 82, redundant gate pads 84, and redundant material blocks 86 are formed to complete the thin film for liquid crystal displays of the present invention; . Λ, crystal

Page 35 548499 V. Explanation of the invention (30) The photoresist pattern of +, k, β is smaller than the exposure used in the exposure step, especially with a fine pattern, and Figures 35A to 35C are used for Taijijin The opaque part C of the mask of degree. Fang Xi, Gong Xi Xigu / Yu Ben ^ Ming Guan Example Thin Film Transistor Array Panel Manufacturing Fine Schematic Second Photomask Channel Partial Layout Drawing 7 Formation, and the formation of the long electron beam or laser system with the% / + type or its width interval: Π:: mask, at this time the micrograph in the photomask ^ y ^ should be greater than 1 micron when testing the accuracy. In addition, the interval between the light, 7? T Γ ^ pattern or its width should be smaller than the light Y, used in the exposure step, and it is particularly necessary if it is less than one and a half of the resolution. According to ^^, the resolution is 3 to 4 microns, and the interval of the fine pattern or its width should be in the range of 1 to 2 microns. The pattern of one of the plurality of slits in the mask 400 channel portion c can be formed as shown in FIG. 35A, and the channel portion c of the mask 400 can be the slit pattern in FIG. 35B, and has A slit pattern passing through the partial strips 4 and 0 can form the channel portion C shown in FIG. 3C. However, the photoresist pattern with a thickness of 2,000 to 4,000 angstroms is formed by exposing the photoresist pattern with the masks of Figs. 3A to 3C. The pattern has no uniform thickness. Figures 36A and 36B are photoresistances formed using the masks of Figures 35A to 35C! Worm_ Figure view, and Figure 36B is a cross-sectional view taken along the line XXXVIB-XXXVIB 'of Figure 36A. As shown in FIGS. 36A and 36B, the photoresist pattern 100 in the central part of the channel part C is uniform, but the thickness of the photoresistance pattern 100 is thicker than

548499 V. Description of the invention (31) The peripheral part of the channel part C is due to the photoresist pattern of the peripheral part of the channel part C being exposed less than the central part of the channel part C due to peripheral effects. Accordingly, in order to remove peripheral effects and use the second photomask of the example of the present invention to make all parts of the photoresist pattern with three thicknesses uniform thickness during exposure and development, especially photoresist If the middle thickness of the pattern is 100 (shown in FIG. 3 6B or 1 1 4 in the first example), the second photomask should have four areas with different transmission rates. The photomask includes a first region that transmits most of the light, a second region that blocks most of the light, a third region that controls the transmission of light, and a peripheral portion that is interposed between the first and third regions. The fourth and fourth zones have transmission values between the first and third zones. At this time, if you want to control the transmission rate of the third and fourth zones, you need to have a slit or mosaic-like fine pattern or The opening portion formed by the width t of the fine pattern can be smaller than the resolution of the exposure device, and a translucent layer having a transmission rate higher than that of the second portion can be formed in the third and fourth regions, and the above methods can be mixed . This means that if a mask with the same magnification as the LCD array panel is used and the exposure device resolution is 3 to 4 microns, the fine pattern or the interval between its widths is less than 3 to 4 microns. Of course, the photoresist pattern The thickness can be controlled by adjusting the fine pattern smaller than the resolution of the exposure device or the interval of its width to adjust the transmission rate of the photomask. Here, a uniform photoresist pattern can be formed, that is, the channel C is formed. Medium-thickness semiconductor pattern. The former case will be explained by Figs. 37A to 39C, and the latter case will be explained by Figs. 4A to 4OE. Fig. 3 7A to 37C are manufacturing methods of thin film transistor array panels according to an example of the present invention

Page 37 548499 V. Partial layout of a channel in a new second mask used in the description of the invention (32). As shown in FIG. 37A, the “lots of slit patterns 412 and 4n are formed in the channel portion C of a mask 400” and the slit pattern 4 1 2 is a slit pattern longer than the central portion. 4 1 2 'and the long slit pattern 4 1 3 is formed outside the slit pattern 4 1 2. Here, the slit pattern 4 1 2, 4 and 3 are changed to increase the light transmittance of the peripheral part of the peripheral area of the channel portion c. At this time, the width L 3 of the slit pattern 4 and 3 is preferably narrower than the narrow pattern. The width L 丨 of the stitch pattern 4 1 1 is preferably less than about 80%. The structures of Figs. 37B and 37C are similar to those of Fig. 3 "and 35C, but the interval L2 of the edge portion of the channel C is longer or wider than the channel portion [the central portion of L1. Figures 38A and 38B are used in Figures 37A to 37C. Photoresistive anti-erosion pattern view formed by the photomask, and FIG. 38B is a cross-sectional view taken along the line IB-XXXVI IIB of FIG. 38A. As shown in FIGS. 38A and 38B *, a uniform light The reactance is formed by using a photomask shown in FIGS. 37A to 37C, a smooth earth type, or its width is in the periphery of the channel portion c; a wide mask; a pattern having a longer slit is next. Mask knot with split ring structure ... ^ corpse 'π shaped electric product

Middle: The pass in the second photomask with a split ring structure = = The photomask pattern for the source / drain is related to the channel part c and ㊁ As shown in Figures 39A to 39C, the channel part 〇 is provided The split ring has a wide space or a narrow shape with a narrow shape of +0, and has the light transmission rate of the surrounding area and removes the surrounding two: ... increasing the channel part

548499 V. Description of the invention (33)-It has a slit with a strip shape as shown in Fig. 37C ~ In the channel part c of Fig. 39A, and the channel part 10 is formed in the part 420 with a wider width than the others In part, the light transmittance of the concave humanoid peripheral region. A large number of slit patterns 4 in the channel part c shown in FIG. 39B around the force-passing part C are not shown in FIG. 37A. Here, the peripheral part of the channel part c is wider as shown in the central part of the figure c. , And smaller than the slit pattern 41 丨 == longer than the channel portion to form a long strip on the two sides of the channel portion C. Λ, '' pattern 4 1 3 series The structure of FIG. 39C is similar to the photoresist pattern of FIG. 39β, and it can be used to have a uniform thickness—the thickness will be described next. ^ Part C of the bevel is used. FIG. 40A to the second embodiment of a thin film transistor array according to the present invention with a transmission rate control layer of the second method, and the reverse method. Figures 40A, 40B, 40C reveal the configuration of different structures. Figure, Figure, Sectional view of 40. And FIG. 40β is a graph as shown in FIGS. 40A and 40B. A transmission control layer formed by m 0.. Control layer & opacity: material such as: each made. In addition, the transmission control layer 51. It is formed on the i-transmittance c, and is adjacent to the transmission rate control layer 510 on both sides, so as to remove the Tuesday. The width of the transmission rate control layer 511 is preferably smaller than the resolution of the light. The transmission rate control layer 5 1 0, 520 or the mask substrate used in the knowledge is to increase the peripheral area of the channel portion c shown in FIGS. 40C to 40E. The light transmission rate is 548499. V. Description of the invention ( 34) The width of the transmission rate control layer 520 of the peripheral area E is narrower than that of the other parts of Chuanna. Peripheral-Mask Substrate 2 = Control 5 :, Λ becomes "; 4 ° D has a peripheral area £ long strip of transmission rate control layer; Γ Peripheral Region E, the mask substrate widened 5 0 0 And Figure 4〇E: The second passer ’s loss rate: the width of the layer 520 is wider than the transmission rate control layer 5 1 〇7. The channel part c and the transmission rate are controlled by m and = shown in the old picture F = Γ, which forms the photoresist pattern of three different thicknesses, that is, the photomask includes a -th-region and-has a pattern with an open edge,-= catty, and light transmission. The third value of the median value of the rate is smaller than this; analysis = greater than the third region transmission, the fourth region Γ has a photoinduced anti-money pattern that is thinner than that of the four anti-residue agent. In the example of f-four & The lines are respectively aligned with the peripheral parts of the data lines / brothers 1, 2, and vice versa, in the-two pass. Among the children, the passage part, the second, ... area 2; Part, part of the channel part]]. For the back of the data line part, here, when considering the 3 micron solution, the interval between R ± can be about 丨 micron ", the width of the slit pattern and Its slit pattern 4 1 2, 4 1 3, η Ξ 3 / Α ° The opening pattern of the narrow slit in the peripheral area ^ ί 3 plus the light transmission rate, if the resolution is greater than the central part, the size is smaller than the exposure device Figure 39A to 548499 V. Description of the invention (35) 3 9C mixing. / f on a reticle to form a slit with a uniform thickness of the photoresist pattern Ξ ^ The design rule for the width will be illustrated by forming an example of a channel section with a split ring or an oblique curve semicircle. , 42 are layout diagrams of channel portions in a second photomask used in the fourth example thin film transistor array panel manufacturing method of the present invention. A slit pattern structure having a long strip formed in the channel portion c shown in FIG. 41 is similar to that shown in FIG. 39, and a channel portion c forms a slit pattern. 1 * 隹 U open y or J-shaped channel portion C has a 45-degree slant curve in the curved portion D 'instead of sudden_degree' as shown in FIG. 39A. Furthermore, the size of the channel portion c is larger than that of other bucket wounds, so as to increase the light transmission rate at the end E of the channel portion c to form a photoresistance pattern with uniform thickness. ^, No. 41, the width of the slit pattern 4 in the bow portion D and the width of the source / injury (except bow σ 卩 D) to increase the light transmission rate. Furthermore, the peripheral part of the C-end of the channel part ^ is extravagant to the actual production of a "mesh s, I here" visibility of the curved part ^ and the rule should be 1.41 ± 0. 05 to 1. In the range of 24 ± 0.05 μm, and the other parts except the curved part D are in the range of 1.25 ± 0.05 m. When the resolution of the exposure device is about 3 μm, the watt lens type. Μ % I 马 再 Moreover, as shown in FIG. 42, the mask of the peripheral portion E is within 1.5 to 2.5 microns, and the width of the vehicle is wider than, preferably 1 interval U 0. 25 microns. Of course, as shown in the diagram, a portion with a width of ^ can be from 1 to a cut force application port 548499 V. Description of the invention (36) In other parts, except the peripheral part E, in order to increase the light transmission rate by local A photoresist pattern with a uniform thickness is formed. Although the first to third examples are structures for a panel with a pixel electrode and no common electrode in the present invention, it can be applied to a panel structure with a pixel electrode and a common electrode at the same time. In this case, the common electrode can be formed along the gate line. , And the pixel poles can be formed along the data line. The thin-film transistor panel can be manufactured in many other variations and involves many other variations. With the present invention, the manufacturing process of a thin film transistor panel for a liquid crystal display can be effectively simplified, and at the same time, the gate pad and the data pad can be protected. Furthermore, the quality of the thin film transistor is because the sharp bend in a semiconductor pattern channel portion is removed, a channel portion with a gentle bend is formed, or the light transmission f in the peripheral region of the channel portion is increased to form a channel portion semiconductor pattern. And improve it. The preferred examples of the present invention have been disclosed in the drawings and description. Although specific words and phrases are used, this is only general and explanatory, and is not intended to be limiting. The scope of the present invention is described in the following application scope. in.

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Claims (1)

548499 6. Application scope 1. A method for manufacturing a thin film transistor array panel, including the following steps: forming a gate line on an insulating substrate; the gate line includes a gate line and an interrogator connected to the gate line; forming A gate insulating layer to cover the gate line; forming a semiconductor pattern on the gate insulating layer; forming an ohmic contact layer pattern on the semiconductor pattern; forming a data line including the same layer made on the ohmic contact layer And a source and a pole separated from each other and a data line connected to the source; and _ forming a passivation layer to cover the data line; wherein the source and the drain are formed by using a photoresist pattern The light lithography process is separated, the channel part between the source and the drain has a corner, and the photoresist pattern has a first part, which has a first thickness and is located in the channel part. A part except the corner part of the channel part, a second part, which has a second thickness greater than the first thickness, and a third part, which includes the corner part of the channel part And has a small The third person of the thickness of the first thickness. 2. The method of claim 1 further includes the step of forming a pixel electrode to connect to the drain electrode. 3. The method according to item 1 of the patent application, wherein the thin film transistor array panel is used in a liquid crystal display. 4. The method according to item 1 of the patent application, wherein the photoresist pattern is made of a positive photoanthroid, and a photomask used to form a phototype anti-money pattern Page 43 548499 6. The scope of patent application includes the first, second, and third parts. The transmission rate of the third part is higher than the first and second parts, and the transmission rate of the first part is higher than the second part. Or, the photomask is aligned so that the first, second, and third portions face the first, second, and third portions of the photoresist pattern during the exposure step, respectively. 5. The method of claim 4 in the patent application, wherein the photomask further includes a fourth part, which is located between the first and third parts, and has a transmission rate value greater than the transmission rate value of the first part and less than The third part of the transmission rate value. : 6. The method according to item 5 of the patent application, wherein the first and fourth parts of the photomask include at least one pattern whose resolution is smaller than that of the exposure device used in the exposure step. _ 7. If the method of applying for item 4 of the patent scope, wherein the first and fourth parts of the photomask include a part of the transparent layer. 8. The method of item 1 in the scope of patent application, in which the I material circuit, the ohmic contact layer pattern and the semiconductor pattern are formed in the same light lithographic printing process. 9. The method according to item 8 of the patent application, wherein the steps of forming a gate insulating layer, a semiconductor pattern, an ohmic contact layer pattern, and a data line include: stacking a gate insulating layer, a semiconductor layer, an ohmic contact layer, And a conductor layer; · coating a photoresist layer on the conductor layer; exposing a photoresist layer through a photomask; forming a photoresist pattern to make the second part photoresist resistant by development Etched layer on the data line; by removing the conductor layer, semiconductor layer and the Page 44 548499 VI. Patent Application: The thickness of the ohmic contact layer, the first part, the conductor layer and the ohmic contact layer below the first part, and the thickness of one part of the second part, to form the conductor layer and the ohm respectively. Data lines composed of contact layers and semiconductor layers, ohmic contact layer patterns, and semiconductor patterns; and removal of photoinduced anti-surname patterns. 1 0. For example, the method of claim 9 in the patent application, wherein the steps of forming a data line, an ohmic contact layer pattern, and a semiconductor pattern include: removing a portion of the conductor layer under the third part by dry or wet etching to expose The ohmic contact layer is present; the ohmic contact layer below the third part, the semiconductor layer below and the first part are dry-etched to expose the gate insulating layer below the third part and the conductor below the first part Layer to obtain the completed semiconductor pattern; and remove the conductor layer below the first part and the = ohmic contact layer below to obtain the v-completed data line and the completed ohmic contact layer pattern. 1 1. The method according to item 9 of the scope of patent application, further comprising the step of etching the gate insulating layer under the third part in the step of forming the data line, the ohmic contact layer pattern and the semiconductor pattern. 1 2. The method according to item 1 of the patent application scope, wherein the gate circuit further includes a gate pad connected to and receives a signal from an external circuit, and the data 0 丨 the circuit further includes a gate connected to and received from an external circuit A signal data pad, a passivation layer and a gate insulation layer respectively have a first contact hole and a second contact hole to expose the gate pad and the data pad; and further include forming a redundant gate pad and A redundant data pad is composed of the same layer as the pixel electrode, and is connected through the first and second contact holes respectively. Page 45 548499 VI. Scope of patent application Gate block and data block. 1 3. A method for manufacturing a thin film transistor array panel, including the following steps: forming a gate line on an insulating substrate; the gate line includes a gate line and a gate electrode connected to the gate line; forming a gate insulation layer To cover the gate line; to form a semiconductor pattern on the gate insulation layer; to form an ohmic contact layer pattern on the semiconductor pattern; to form a data line including the same layer made on the ohmic contact layer and separated from each other A source and a drain, and a data line connected to the source; and forming a passivation layer to cover the data line; wherein the source and the drain are separated by a light lithography process using a mask; The photomask has a first part, a second part having a transmission rate greater than the first part, a third part having a transmission rate less than the first part, and a third part having a transmission rate greater than the second part Part Four of the Participant. 14. The method according to item 13 of the patent application scope, further comprising the step of forming a% pixel electrode to be connected to the drain electrode. 15. The method according to item 14 of the scope of patent application, wherein the thin film transistor array φ array panel is used in a liquid crystal display. 16. The method according to item 13 of the scope of patent application, wherein a positive photoresist is used in the process of light lithography, the first part, the second part, the third part, and the fourth part It is aligned between the central part of the channel part between the source and the drain, the peripheral part of the channel part, the data line, and the first, second, Page 46 548499 VI. Scope of Patent Application Except for Part III. 17. The method according to item 13 of the scope of patent application, wherein the first and second parts of the photomask include a plurality of slit patterns, and the width and the interval therebetween are smaller than the resolution of the exposure device used in the exposure step. 1 8. The method according to item 17 of the scope of patent application, wherein the width of the slit pattern in the second part is smaller than the slit pattern in the first part, and the interval between the slit patterns in the second part Larger than the slit pattern of the first part. 19. The method according to item 18 of the scope of patent application, wherein the interval between the second part is wider than that of the first part. 20. The method according to item 13 of the scope of patent application, wherein the first and second parts are a slit pattern, and the interval between the first part is smaller than the second part. 2 1. The method according to item 13 of the scope of patent application, wherein the first and second parts include a slit pattern and have a strip shape formed along the channel = part. 2 2. The method according to item 13 of the scope of patent application, in which the first and second parts include a fifth part with the remaining parts with a wider interval than the first and second parts. 2 3. The method according to item 13 of the scope of patent application, wherein the first, second and channel portions are formed by one of the following shapes, including a straight line, a square shape, a split ring, or a semi-circular shape. 2 4. The method according to item 13 of the scope of patent application, wherein a negative photoresist is used in the process of light lithography, and the second, first, fourth and third parts are aligned between the source and the drain. Between the central part of the passage part, the peripheral part of the passage part, the data line, and parts other than the first, second and third parts. 2 5. —Thin-film transistor array panel for LCD Page 47 548499 6. The scope of the patent application includes: an insulating substrate; a gate circuit formed on the insulating substrate, and including a plurality of gate lines for transmitting a scanning signal and a thin film transistor as a branch line of the gate line A plurality of gate pads; a gate insulation layer covering the gate line; a semiconductor pattern formed on the gate insulation layer and made of a semiconductor; a data line layer formed on the semiconductor pattern and including the intersecting gate lines A plurality of data lines, a thin film transistor's multiple source are connected to the data line, a thin film transistor's multiple drain is related to the gate, and is opposite to the source and separated from the source; a passivation layer pattern, formed on The data line has a contact hole to expose the drain electrode; and two or more pixel electrodes formed on the passivation layer pattern and connected to the drain electrode through the contact hole; a channel portion is provided between the source electrode and the drain electrode It has a corner part, and a part of the semiconductor pattern is removed at the corner part. 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