TW556238B - One-cylinder stack capacitor and method for fabricating the same - Google Patents

Abstract

An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

Description

556238 V. Description of the invention (1) Background of the invention 1. The scope of the present invention is generally related to single-cylinder stacked (OCs) capacitors and manufacturing methods thereof. method. 2 · Relevant technical descriptions Due to the increase in the density of memory cells in semiconductor devices, the area occupied by memory cards has been reduced. The capacity is proportional to the dielectric constant of the capacitor dielectric and the surface area of the capacitor electrodes. Therefore, it is necessary to choose a dielectric with an increased dielectric constant. 'And / or increase the surface area of the capacitor electrode to increase capacity. However, the use of new dielectric materials is usually expensive and time-consuming. Often, new manufacturing equipment needs to be supplied to verify the reliability of the dielectric materials, and it is determined that the dielectric materials have the capacity to mass-produce devices. Therefore, increasing the surface area of the electrode is often used to increase the device capacity with conventional dielectrics (such as a dielectric (NO) layer composed of gas and oxygen). Hemispherical particle (HSG) electrodes' are used in conventional 128 megabit (or less wDRAM) to increase the effective surface area of the electrodes, but any reduction in inter-electrode space is limited due to the presence on the electrode surface, and therefore in These electrodes cannot be applied in W million-bit 70 (or higher) high-volume devices. As such, examples of single-cylinder stacked (0CS) viable electrodes, for example, usually increase the electrode height from i.4㈣ to The height of! .6 _ is regarded as the most efficient way to increase its capacity. The following will explain the manufacturing of storage electrodes with reference to Figure W, especially 1 is generally formed using a single mode with less than 1 &2; handsome design Prescribed book binding t -6- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) V. Description of the invention (2) Combined into storage electrode. Refer to Figure 1, the surface has a contact plug 1 $ An inner-layer insulation layer (H) is formed on the inner-layer insulation layer (not shown), and an oxide layer (not :) is formed to a thickness hl, which substantially corresponds to the desired electrode height. The emulsion layer and the stop layer are engraved to have the right to oxidize the stop layer 20. In this way, an opening 40 is defined in the contact plug i5, thereby exposing the contact plug 15. Thereafter, as shown in FIG. 2, polycrystalline silicon is deposited on the side wall of the opening 40 and the contact plug 15 to form a columnar electrode 50. Referring to the scanning electron microscope (SEM) image of FIG. 3, as mentioned above, as an example of a high-volume device, to increase its capacity, it is desired to increase the resolution of the capacitor capacitor electrode to 1.6 #m (or higher). However, if the height of the oxide mold layer is increased from μ to h2 (, force 1.8 // m) and the lower critical dimension of the opening 4 () is still maintained, it is necessary to note ^ to limit the setting of the sidewall slope of the opening 4G, @ 可A bridging B is formed between the storage electrodes of the adjacent pseudocapacitors (Figs. 2 and 3), thereby causing double-bit destruction. Focusing on avoiding double bit destruction, the upper key size (a) of the opening 40 can be reduced by reducing the lower key size ⑷ of the opening 40. However, this method has the disadvantage that the surface area is reduced at the bottom of the opening 40 and the capacity is reduced. It should also be noted that the occurrence of double-bit destruction will cause the storage electrode to fall and touch adjacent electrodes. If so, it is necessary to consider the structural integration of the electrodes. Reference is made to FIG. 4, which means that it has been determined that after the storage electrodes are separated to isolate the cells, the oxide mold 30 is removed by wet etching. During this wet etching process, an etchant can be infiltrated into the interface between each storage electrode 50 and an etch stop layer 20 to thereby etch the interlayer insulating layer 10. This can weaken the base of the storage electrode, causing the storage electrode to tilt and touch the adjacent electrode. Figure 5A illustrates an example using an SEM image, where a falling electrode causes a @ (CNS) A4 specification (210X297 public love) 5. Description of the invention (concave of shape and pattern; and Figure 5B shows the cross section of the other electrode when the electronic electrode is dropped into the + T tracing polar (SEM) picture. Therefore, the new structure of OCS capacitors and the increase of one system and one system have increased the demand for A + p π + / and clothing methods. Even if the capacitor height is h6, ancient (μ) second grade examples can be effectively avoided. Depressions and bridges between adjacent electrodes. Summary of the invention According to one aspect of the present invention, a method for forming a layered valley valley electrode includes forming an insulating layer on the surface of the interlayer # and the second layer extending into the insulating surface of the interlayer. Upper deposition-lower ^ ρ layer; stop collecting debris at the last engraving layer. Γ As the lower mold layer is added during the formation of the lower mold layer, the lower mold layer is annealed to adjust the wet erosion ratio of the lower mold layer; deposited on the Guangzhen layer A mold , I 中 的 湿 # ratio is less than adjusted to form one, that is, the dry mold upper mold layer, lower mold layer, and engraved stop layer, with: mold sound: mouth 'which at least exposes the-contact part of the plug surface; ㈣ near = = Layer, which causes the opening size of the lower mold layer to increase and expose the adjacent surface parts of the ㈣stop layer; and on the upper and lower molds: the opening surface, the surface portion of the engraved stop layer, and the exposed surface of the conductive plug A conductive material is deposited. According to another aspect of the present invention, a method of manufacturing a capacitor includes forming a lower electrode on an acoustic insulation layer, forming a dielectric layer on the lower electrode, and forming an upper electrode on the dielectric layer. The formation of the lower electrode includes forming an etch stop layer on the surface of the sandwich insulation layer and a surface formed by the conductive plug extending into the sandwich insulation layer at a depth; depositing a lower mold layer on the narration stop layer 'And due to the inclusions in the lower mold layer during the formation of the lower mold layer, and by annealing the lower mold layer, the wet erosion ratio of the' a π I lower mold layer; depositing an upper mold layer on the lower mold layer, wherein the upper mold The ratio of the sound and the wet surname is less than the adjustment Lower mold layer wet # ratio; dry-etch the upper mold layer, the lower mold layer and the engraved stop layer ... to form an opening 'where at least the exposed contact surface of the plug-name]: the branch layer and the lower mold layer, resulting in the lower mold layer] Increase the size, and expose the surface of the etch stop layer + the surface of the conductive plug on Zheng Jin; and the opening surfaces of the upper and lower mold layers, the worm stop layer, the surface portion of the layer and the exposure of the conductive plug A conductive material is deposited on the surface. Still according to another aspect of the present invention-a capacitor includes a layered insulating layer having a surface;-a conductive plug extends into the interlayer insulating layer at a depth;-an etch stop layer extends on the insulating layer And expose the conductive plug;-the cylindrical lower electrode is defined by the cylindrical side wall and the bottom wall, the bottom wall extends on the surface of the conductive plug and a part of the etching stop layer adjacent to the conductive plug, wherein the cylindrical side wall extends upward from the bottom wall and away from The surface of the interlayer insulation layer; a dielectric layer is formed on the pillar-shaped lower electrode; and an upper electrode is formed on the dielectric layer. The pillar ㈣ of the cylindrical electrode is defined by-the upper pillar ㈣ part,-the lower cylindrical wall part, and the middle cylindrical wall part located between the upper and lower cylindrical i 4 blades. The diameter of the upper cylindrical wall portion and the diameter of the lower cylindrical wall portion increase as they move away from the bottom wall surface, and the diameter of the intermediate cylindrical side wall portion decreases as they move away from the bottom wall surface, and

A ^ C, C > B, and C &D; where A is the diameter of the upper cylindrical wall portion farthest from the bottom wall surface, B is the diameter of the upper cylindrical wall portion closest to the bottom wall surface, and c is the lower The diameter of the cylindrical wall part farthest from the surface of the bottom wall, and D is the diameter of the lower cylindrical wall part at the bottom wall. -9-This paper size applies to Chinese National Standard (CNS) A4 (2i × x297) 55623δ

Brief Description of the Drawings The above and other aspects and advantages of the present invention will be made clearer in the following detailed description made with the accompanying drawings, in which: Figures 1 and 2 illustrate a conventional method for manufacturing a capacitor using a single model in a sectional view; Figure 3 is a conventional method Electron scanning microscope (SEM) image of the storage electrode manufactured by the method; Figure 4 illustrates another conventional method for manufacturing a capacitor using a single model; Figures 5A and 5B are obtained by conventional methods from above and side views respectively SEM image of the storage electrode formed; FIGS. 13 to 13 illustrate cross-sectional views of a method for manufacturing a single-cylinder capacitor using a dual model according to an example of the present invention; and FIG. 14 illustrates cross-sectional views of defects that may occur when the manufacturing conditions of the present invention are not met. Figures 15 to 17 compare the characteristics of capacitors made by the conventional single-model method with the dual-model method of the present invention in a graphical illustration; Figures 18 and 19 illustrate storage made without removing the lower mold insulating layer with SEM images Double bit failures seen in the electrode; and Figure 20 graphically illustrates the relationship between the wet etch time of the electrode of the present invention and certain key dimensions. Detailed Description of the Invention An example of the present invention will be described with reference to the accompanying drawings. Please note that the illustrations shown are for clarity and explanation, and are not necessarily drawn to scale. A single-cylinder stacked (0cs) capacitor according to the present invention will be described with reference to Figs. 6-13. The i-size sheet is suitable for aa household materials (CNS) A4 specifications (21GX 297 public reply) ------- -556238

'Cylindrical'-the word electrode, with a general round shape, rather than any method of making a pure number, as understood by those skilled in the art, is used here to mean a special type of capacitor, ellipse or elliptical sidewall (may be Create precise geometric shapes as defined by the scientific concept. Then, as shown, 'the lower and upper mold layers 130 and 135 are successively formed on the last stop layer 120. Referring to FIG. 6, a conventional process is used to form a sandwich insulation on a substrate (not shown). The layer-cutting and -contact plug __ deeply extend into the surface of the layer 100; then, a layer 131 stop layer 12 is formed on the layer 155 plug 155 and an upper and lower mold insulating layer 135 is formed on the layer 120 During subsequent etching (described later) of 13 °, the etch stop layer 120 is used as an etching barrier layer. Therefore, when selecting the material of the etch stop layer 120, the #etching characteristics of the upper and lower mold insulating layers 135 and 130 must be considered. It will be described by way of example only. If the upper and lower mold insulating layers ⑴ and 130 are oxide layers, the etch stop layer 120 may be formed of silicon nitride with a thickness of 100-5. The upper and lower mold insulating layers 135 and 130 constitute a double layer, which will be etched into a double mold to manufacture the lower capacitor electrode. The material forming the lower mold insulating layer 13o shows a larger wet-etching ratio than the material of the upper mold insulating layer 135. The wet erosion ratio of the sampan marginal material is affected by the concentration of the dopants implanted in it. The larger the dose, the higher the wet residual ratio. Therefore, in order to achieve the above-mentioned different wet etching ratios, the replacement insulating layer 130 may be formed of a doped insulating layer, and the upper mold insulating layer 135 is formed of an undoped (or less doped) insulating layer. The lower mold insulating layer 130 is preferably formed of a doped oxide layer by chemical gas deposition (CVD). Suitable doped oxide layers include borophosphosilicate glass (BPSG) and phosphorus-11. CNS) A4 specification (210X297 mm) 556238 5. Description of the invention (7) Silicate glass (PSG). The upper mold insulating layer 135 is preferably formed of an undoped oxide layer by plasma-enhanced chemical gas deposition (CVD). Suitable undoped oxide layers include electropolymer-enhanced tetraethylorthosilicate (PE_Buteos). Layer, high-density electrodeposited p) oxide layer and P-SiH4 oxide layer. The height H1 of the lower mold insulating layer 130 and the height of the upper mold insulating layer 135 are determined based on the target height of the storage electrode to be manufactured, the upper and lower mold insulating layers, and U0 engraving characteristics. In particular, the judgement of the height of the lower mold insulating layer 应 should be such that the opening to be formed can show the maximum diameter up and down (explained later). When the storage electrode is L6Mm (or larger), the height of the lower mold insulating layer 13 is preferably in the range of 0.5-0.6, and the height H2 of the upper mold insulating layer 135 is in the range of 丄 μ4. The height m of the insulating layer of the lower mold and the thickness of the upper layer of the insulating layer of the upper mold will be different depending on the material used for the insulating layer and the target of the storage electrode made twice. After the lower mold insulating layer 130 is deposited and before the upper mold insulating layer is deposited, the lower mold insulating layer 13G may be subjected to an annealing and / or surface cleaning process, as appropriate. That is to say, the wet lasting ratio of the lower mold insulating layer 130 can be controlled by annealing. More specifically, in order to increase the ratio, the lower mold insulating layer_human ion is added too much, which is effectively used after implanting ions. Annealing to more accurately reduce the wet I-worm ratio. For example, annealing after implantation is an effective mechanism for fine-tuning the thirst erosion ratio. For example, the current mold insulating layer 13. It is formed by changing the miscellaneous paste and: :) The layers are formed 'by weight ... when each is 2-3% Han degrees, the second is) the fire reduces the wet erosion ratio. Weight; when the concentration of Nongji is not more than 5❶ / ❶, the lower mold insulation layer 130 I________ _ k Qiao Zhang Nu Nu Caiqing 12- B7 8 V. Description of the invention (There is no need for annealing. The annealing itself is to avoid the lower mold insulation layer 13 〇 The temperature within the cracking temperature range is preferably lower than the deposition temperature of the etch stop layer 120. For example, when the etch stop layer 120 is formed of a silicon nitride layer, it is preferable to lower the lower mold at a temperature of less than 700 t. The insulating layer 130 is annealed. After annealing, the lower mold insulating layer 130 can also be subjected to a surface cleaning process, for example, 'the lower mold insulating layer 130 and the upper mold insulating layer 135 are not formed in place, then the lower mold insulating layer 130 is formed and the upper layer is formed. A considerable amount of time has passed in the mold insulating layer 135. In this case, moisture will be absorbed by the dopants implanted in the lower mold insulating layer 130. Therefore, an amorphous defect layer is formed on the surface of the lower mold insulating layer 130. This amorphous The imperfect layer can exhibit a wet erosion ratio larger than that of the remaining lower mold insulating layer 13 Therefore, it is best to perform surface cleaning to remove the amorphous defect layer after annealing or depositing the lower mold insulating layer 13; for this purpose, a sulfuric acid solvent can be used. Avoid the formation of the amorphous defect layer (ie in the original The lower mold insulating layer 130 and the upper mold insulating layer 135) are formed on the ground, or before the upper mold insulating layer 135 is deposited, the lower mold insulating layer 130 is completely (or only for a short period of time) exposed to the air, and the removal of non- Removal process of the crystal defect layer. Next, referring to FIG. 7, a mask (not shown) is used to continuously dry-etch the upper mold insulating layer 135, the lower mold insulating layer 13 and the etch stop layer 12 to form an opening. 140 'CFX gas (such as C4f4 * C3F8 gas) can be used to perform dry etching. The process limitation of dry etching causes the opening to be defined by oblique (non-vertical) sidewalls (relative to the sandwich insulation layer 100)' In other words, the opening is outward with a height The direction is gradually tapered 'so that the diameter of the opening is larger at the top than at the bottom. Refer to Figure 8' Perform a selective wet etch to complete the formation of the dual mold 138_ -13- This paper size applies to China National Standard (CNS) A4 ' (21〇X 297 & ^) ----- V. Description of the invention (9) 'Since the lower insulating mold UG is formed of a material that is harder than the upper insulating mold 135, the lower insulating mold 13 removed by wet etching will be more than the upper insulating The mold 135, as it does, defines a vase-like opening 14 in the dual mold 138. Although the insulating mold 135 is only slightly etched, this slight etching is advantageously used as a pre-formation for the storage electrode (described later). Clear in advance, it is best to use sci (NH4〇H / H2〇2 / deionized water) and hydrofluoric acid (HF) in order to perform wet etching. Wet etching is conditionally limited, that is, a certain amount of These designed dimensions are referred to herein as critical dimensions A, B, c, 0 and £. As shown in Fig. 8, A is the maximum width (or diameter) of the opening 14o of the upper insulating mold 135; b is the minimum width (or diameter) of the opening 140, of the upper insulating mold 135; [the opening for the lower insulation please ⑽ is the maximum width (or diameter) of ⑽; d is the minimum width (or diameter) of the opening of the lower insulation _; ㈣ is the opening ⑽, and the bottom is engraved with the stop-exposure exposure. For example, the critical dimension C of the opening 14 is preferably equal to or smaller than the critical dimension A. In addition, the critical dimension E is preferably in the subsequent process (description), which is sufficient to prevent interlayer insulation during the removal of the dual mold 138. Layer. Storage electrode, in nm, and the etch stop layer, for example, in order to form a lower critical dimension d having a high opening 140 ′ of 1 μm (or greater), it is preferable that the exposure length E is not less than 145 120 15 nm. He influences the impurity concentration of the dual-mode 138 wet-etching conditions (that is, the material-to-cut ratio), and the wet-etching time u Refer to FIG. 9, along the side wall, the bottom and the top electrical layer 150 of the dual-mode 138, the conductive layer 150 is defined The lower electrode can be formed overnight: doped-doped polycrystalline silicon layer, and the conductive layer is a silicon layer _____ -14- I paper size suitable for a standard (CNS) A4 specification (21GX 297 g 14_ The sub-degree F can be between ㈣ 556238 and 5. Description of the invention (10) If the storage electrode has a height of 1 > 6 mm (or greater), the thickness F is about 45 nm. Next, as shown in FIG. 10, Using a flowable material (such as BPSG, PSG, or undoped osmium salt glass)), the entire structure of the structure is deposited on the entire surface of the structure 160, to fill the opening 14. Then, as shown in Figure u Using the dry mechanical grinding method (CMp) or dry back, the insulating layer 导电 and the conductive layer 150 are partially removed until the top of the dual mold 138 is exposed. Next, as shown in FIG. 12A, the last name is used. The etchant removes the dual mold 138 and the insulating layer 160, so that each unit forms a storage electrode 150 having a single pillar stack structure. When removing the dual-mode 138, it is best to use a mixture of album and simplification as an insecticide. Here, since the conductive layer 150 overlaps the rest stop layer 12o, the tincture must be substantially moved during the removal of the dual-mode 138. -A distance is used to enter the central insulating layer ⑽. In this way, the penetration of the elixir can be avoided. Figure 以 2β illustrates the storage electrode 形成 formed according to the preferred embodiment of the present invention with an SEM image. As shown, no visible Disadvantages of the previous manufacturing method. Next, as shown in FIG. 13, a dielectric layer 170 is formed to cover the storage electrode 150 ′, and an upper electrode 180 is formed by the Xi process to obtain a whole capacitor. The I electric layer 170 may be a nitrogen oxide (NO) layer, but other materials having a large dielectric constant (k) may be used. Referring to FIG. 12A again, the storage electrode 150 is in contact with the contact plug 115 and has a similar structure. The single cylindrical structure of the vase. In particular, the cylindrical wall of the storage electrode is composed of an upper cylindrical wall portion extending between A and B, a lower cylindrical wall portion extending between, and B # C It is defined by the middle cylindrical wall portion. The further away from the bottom wall surface, the straighter the upper cylindrical wall portion is. And the lower column-shaped wall portion of this paper is suitable for the standard of B home standard (CNS) A4 specifications (21GX297 public -15-556238) V. Description of the invention (11) the diameter increases (thinner), and the center column The diameter of the shaped wall portion decreases as it gets farther from the bottom wall surface (thinner). According to the preferred embodiment of the present invention, when the storage electrode 150 is configured, the following relationship is established:

A g C, C &gt; β, and c &gt; D where A is the diameter of the upper cylindrical wall portion furthest from the bottom wall surface, B is the diameter of the upper cylindrical wall portion closest to the bottom wall surface, c is The diameter of the lower cylindrical wall portion farthest from the surface of the bottom wall, and D is the diameter of the lower cylindrical wall portion at the bottom wall. Then the size requirements prevent bridges between adjacent storage electrodes, and during the manufacturing of the storage electrodes, the critical dimensions of the outer diameter at the bottom of the storage electrode can be monitored online by measuring only the key Z inch A of the outer diameter at the top of the storage electrode. Figure 14 shows that if the critical dimension c of the storage electrode 15 is larger than the critical dimension A ', bridging will occur, and even if no bridging actually occurs between adjacent storage electrodes, unless C is set to be less than or equal to A, otherwise Unable to ensure adequate processing margins. According to the characteristics of the OCs capacitor of the present invention and the various processing parameters applied in the manufacture of OCS capacitors, they are determined through the experimental examples described below. The values appearing in the following experimental examples will be based on the target height of the surviving capacitors to be manufactured and Capacitance varies. Experimental Example 1 Fang: The characteristics of a capacitor manufactured using a single mode are compared with the characteristics of a capacitor manufactured using a dual mode according to the present invention. Except that in the present invention, a PE-layer with a thickness of 0.5 μm and a thickness of BPSg is used as the upper mold to form a dual mold = and ^ ^, and the conventional method consists of _____-I. This paper is applicable to gg * standard (CNS) 4 visual grid (Ca> <297) 16- 556238 V. Description of the invention (12) Single-1.7 PE_TE0s layer with a thickness of 1 forms a single mode, and is in the same mode These two methods are used under conditions to manufacture a storage capacitor with 16 tons (or more). "Refer to Fig. 15" In each unit of a capacitor manufactured using a single-mode capacitor, approximately 15 double-bit 疋 failures are shown in each unit of the capacitor. Three-fold proves that the method of making a dual-mode capacitor according to the present invention can significantly reduce bit destruction in the formed cell. The storage method uses the conventional method and the capacitor manufactured according to the present invention to measure the storage point capacitance Cs. As shown in FIG. 16 'in each unit, the storage node capacitance Cs of the capacitor manufactured according to the present method is about 15 Is larger than the storage node capacitance Cs of the capacitor manufactured by the customer. The reason is that the storage electrode formed by the dual-mode method according to the present invention has a larger bottom area than the conventional method using a single-mode user. Experimental example 2 ^ 14_high μ manufactured by using the conventional method to make the material mold] = capacitor 'and μ :: stored electricity manufactured by using the dual mode according to the method of the present invention' 'Investigate bit defects and charging (update ) The relationship between time. As shown in Figure Π, at the same unit element defect level formed according to the method of the present invention, the f ^ n ± Ba is formed by the relative emperor-update time than the conventional method

Electric valley theft increased. A phenomenon according to the present invention. The extra capacitance in the early 70 caused this experimental example. 3 In accordance with the Gu Jie method of capacitor manufacturing of the present invention, a suitable insulating material is selected. This paper ruler_Home standard (⑽) A4 specification 556238 A7 B7 V. Description of the invention (13 ) Layer is used for the lower mold of the dual mode. Each of the P-SiH4 layer and a doped BPSG layer is used to form the lower mold, and the PE-TEOS layer is used to form the upper mold. The storage electrodes formed by the respective dual molds, the critical dimension A of the outer diameter at the top of the opening, the critical dimension C of the outer diameter of the second bending point, and the critical dimension D of the outer diameter at the bottom are shown in Table 1. 0 Table 1 Materials Top outer diameter off Second bending point outer diameter Bottom outer diameter off Bottom to top (D: A) Key size A (nm) Key size C (nm) Key size D (nm) Opening ratio (%) P- SiH4 215 170 109 51 BPSG 205 192 149 73 As shown in Table 1, according to the dual mode used in the manufacture of the capacitor of the present invention, the doped insulating layer is suitable as the material layer of the lower mold. Experimental Example 4 In order to determine the proper dopant concentration of the lower mold insulating layer, the storage electrode was manufactured according to the method of the present invention under the same conditions, but the concentrations of dopants, boron and phosphorus in the lower mold layer of BPSG were different, and then The capacitor measures the critical dimension A of the outer diameter at the top of the opening, the critical dimension C of the outer diameter of the second bending point, and the critical dimension D of the outer diameter at the bottom. The results are shown in Table 2. -18- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding% 556238 Concentrations of B and P in BPSG layer (percent by weight) Critical dimension of top outer diameter A (nm) Critical dimension of bottom outer diameter D (nm) Middle to top (C: A) Open bottom to top (D: A) Kailuo main one ----------- --- two_ a, 1 No, when the concentration in the BPSG layer of the lower mold insulation layer increases, 'storage electrode' Second bending point

In addition, the key dimensions DM are increased. For a surviving electrode formed by 35 weight percent of MW weight percent of P, the outer diameter of the second ridge curvature of the key is larger than the key dimension A of the outer diameter of the top, which is a cause of gratitude. The middle opening ratio. f In addition, the high etching ratio of the lower insulating layer of the lower mold insulation layer also ensures sufficient pre-cleaning effect because the fabrication process before forming the electrode is also used as a pre / month removal. Therefore, the concentration of B and P is preferably 2-3% by weight. "Experimental Example 5 Experiments are performed to determine the optimal thickness of the lower mold insulation layer. When the critical dimension D of the external control at the bottom of the opening is the largest, it can be accompanied by **. The critical dimension of the diameter A. In particular, when the total thickness of the ϋτ mode insulating layer is maintained at 17 μ, the thickness varies between 0.3 μm and 5 μm, and the GTM layer is θ meshed against the formed storage electrode, and 1 opening is measured. The key dimensions of the outer diameter of the top A,, I-· The paper size is suitable for the financial city (⑽㈣7 公 爱 y 19, a key point of the outer diameter of the bending point 556238 V, A7 ____B7 Description of the invention (15) inch C 'and Open the key dimension D of the outer diameter at the bottom. The results are shown in Table 3. Table 3 BPSG layer thickness (μηι) Key dimension of the top outer diameter A (nm) Key dimension of the outer diameter of the second bending point C (nm) Bottom outer diameter Key dimension D (nm) bottom to top (D: A) opening ratio (%) 0.3 217 164 138 64 0.5 207 198 163 79 As shown in Table 3, the thickness of the BPSG layer with a thickness of 0.3 pm, the bottom opening ratio (D A) and the critical dimension of the outer diameter of the second bending point of the storage electrode, which are all larger than the BPSG with a thickness of 0.5 μηι Additional storage electrodes were made using a dual mold with a thickness of 1.9 μm dual mold, but each BPSG lower mold layer with different thicknesses, such as 0.5 μm, 0.6 μm, 0.7 μm, and 0.8 μm, was used to measure each storage. The critical dimension A of the outer diameter of the electrode at the top of the opening, the critical dimension C of the outer diameter of the second bending point, and the critical dimension D 'of the outer diameter of the bottom of the opening are shown in Table 4. Table 4 Thickness of the BPSG layer (μηι) Outside the top Critical dimension A (nm) Critical dimension of the outer diameter of the second bending point C (nm) Critical dimension of the bottom outer diameter D (nm) Middle opening (C: A) ratio (%) Bottom opening (d: a) ratio (%) 0.5 243 206 183 85 75 0.6 248 216 176 87 71 0.7 235 221 188 94 80 0.8 243 233 186 96 77 As shown in Table 4, even if the thickness of the BPSG layer is increased to 0.5 μm or more, although the second bend The critical dimension C of the point outer diameter changes significantly, but the bottom opening ratio is -20- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 556238 A7 B7 V. Description of the invention (16) The rate change is extremely small, Therefore, it proves that once the BPSG layer as the lower mold, its thickness reaches a special Level, not substantially affected by the increase in the thickness of the BPSG layer critical dimension D of the outside diameter of the reservoir electrode. Therefore, when the lower mold insulating layer is formed of a BPSG layer, the thickness of the BPSG layer is preferably in the range of 0.5-0.6 μm. Experimental Example 6 BPSG layers were formed on respective silicon nitride layers, and then annealed at 650 ° C for 60 minutes and 750 ° C for 10 minutes to determine the optimal annealing temperature to be performed after forming the BPSG lower mold layer. . After annealing at 750 ° C (greater than the deposition temperature at which the silicon nitride layer is formed), many cracks can be seen in the BPSG layer. Therefore, it is proved that the annealing temperature should be lower than the deposition temperature of the silicon nitride layer. Experimental Example 7 After annealing the BPSG lower mold insulating layer, the surface of the BPSG layer is not removed to remove surface defects, that is, an upper mold insulating layer is formed on the BPSG layer, and then a storage electrode is formed using a dual mold according to the present invention, and then scanned by electrons Microscope (SEM) observation. As a result, as shown in Figs. 18 and 19, adjacent storage electrodes (so-called wing defects) bound by a ring were seen at the interface between the upper and lower mold insulating layers of the storage electrode. Such wing-like defects are the cause of double-bit destruction and are believed to be caused by the formation of an amorphous defect layer with a high etching ratio on the aforementioned BPSG layer. In order to remove these defects, a BPSG undermold insulation layer is formed followed by The defective layer is removed under the conditions shown in Table 5. A sulfuric acid solvent is used to perform the process of removing the defective layer. -21-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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.Line 556238 A7 B7 V. Description of the invention (π) Table 5 Suspension time before sample removal (hours) Suspension time after removal (hours) Wing defect 1 18 0 No 2 24 0 No 3 0 8 No 4 0 18 No 5 0 24 No 6 0 48 Yes As shown in Table 5, 'Even after the lower mold insulation layer is annealed, it is left untreated for about 24 hours before being cleared with sulfuric acid solvent. Samples i and 2 can be removed to avoid double-bit damage. Similarly, for samples 3, 4 and 5, if the upper mold layer is formed within 24 hours by removing the lower mold insulation layer with sulfuric acid solvent, double-bit damage can also be avoided. Experimental example 8 Under different conditions (ie, SCI 5 minutes / HF 90 seconds, SCI 7 minutes / HF 90 seconds, and SCI 10 minutes / HF 90 seconds), wet etching of the upper and lower mold insulation layers was performed, and the measurement of the respective storage electrodes was measured. The critical dimension D and the bottom opening ratio (D ·· A) are shown in Fig. 20. As shown in FIG. 20, when the wet etching time is increased, both the critical dimension D of the bottom outer diameter and the bottom opening ratio (0: a) of the storage electrode are increased. Therefore, the storage electrode can be properly controlled by adjusting the wet etching time. Key dimension D at the bottom outer diameter. In the method for manufacturing a single-cylinder stacked (Ocs) capacitor using a dual mode according to the present invention, the height of the storage electrode can be increased while avoiding double-bit destruction. 〇cs capacitor manufacturing method also ensures that there is a large enough key size at the bottom of the storage electrode to meet the capacitor requirements. It is also possible to monitor the storage electricity being manufactured online. 22- The paper size is suitable for a 81 standard i (CNS) A4 specification (21GX 297 public shame) '-------

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556238 A7 B7 V. Description of the invention (18) J pole, which can prevent #etching agent from penetrating into the interlayer insulation layer, and the remaining flaws produced by penetrating agent. Although the present invention is described with a preferred example, the preferred example is only for illustrative purposes. Those skilled in the art should understand that the illustrated example may be modified without departing from the spirit and scope of the present invention. The scope of the appended patent application | is understood to be limited to these examples.丨 Φ Pack f -23- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

556238 A8 B8 C8 1 · A method for manufacturing capacitor electrodes, including: ▲ forming a stop layer on the surface of the interlayer insulation layer and-the surface of the conductive plug; the conductive plug extends into the surface of the interlayer insulation layer to a depth; Deposit a mold layer on the stop layer, and adjust the wet etching ratio of the lower mold layer by adding a dopant to the lower mold layer during the formation of the lower mold layer, and by annealing the lower mold layer; ^ 六 * T 工 都 滘 f : Install less than the adjusted wet erosion ratio of the lower mold layer; dry the upper mold layer, the lower mold layer, and the engraved stop layer to form an open [where at least a part of the surface of the contact plug is exposed; wet upper mold layer and lower mold layer To increase the size of the opening of the lower mold layer, and expose the surface portion of the engraved stop layer adjacent to the surface of the conductive plug; the opening surfaces of the upper and lower mold layers, and the exposure of the conductive plug on the surface of the etching stopper layer A conductive material is deposited on the surface. 2 · As for the method of applying for the patent scope, it still includes removing the upper and lower mold layers after depositing the conductive phase. 3 · If the scope of patent application is the first one, change the product produced by her, and remove the lower mold layer by chemical gas deposition doped oxide. 4 · Method 3 of the scope of patent application ^ Beijing's Manufactory includes at least a borophosphosilicate glass (BPSG) and a phosphosilicate glass layer. ) Any-Material formation 7 Plasma-reinforced chemical gas Plasma-reinforced four 5 · The method as described in item 1 of the scope of the patent application, wherein the upper mold layer is formed by electro-deposition with non-doped oxide. 6. The method of claim 1 in the scope of patent application, wherein at least -24- 556238 A8 B8 C8 Patent application scope Any material such as ethanoate (PE_TE0s), high density plasma (DP) oxygen S1H4 oxide forms the upper mold layer. 7 · The method as stated in the scope of the patent claim, wherein the lower mold layer is formed of borophosphosilicate glass (BPSG), and the phosphorus and boron systems are added to the BPSG before the annealing. 8 · The method of item 7 of the patent scope, such as adding and deleting by weight percentage, and adding the scale by Bps (^ 2-3 weight percentage. 9. The method of applying patent scope, item !, where The lower mold layer is formed by scaly acid glass ionization (PSG) and its phosphorus is added before the annealing. (U method of claim 9 of the patent scope 'wherein it is added in an amount of less than 5 weight percent of the offense. Π: The method of applying for the scope of patent application No. ，, also includes the step of forming the upper mold layer, and first removing the surface of the mould layer with the adjusted over-wet erosion ratio. 12. For the method of applying scope of patent application 丨 丨, which uses h2S〇4 to remove the surface of the mold layer. 13. For example, the method of the scope of the patent application, wherein the conductive layer is deposited into a polycrystalline silicon by low-pressure chemical gas deposition. 如. The method of the scope of the patent application, which uses The upper mold layer and the lower mold layer are wet-etched by at least one of magic (NH4〇H / H2 02 / deionized water) and HF (hydrofluoric acid). '15. If the method of the scope of patent application item No.!, F The etch stop layer is nitrogenstone, and the τ mode layer is annealed at a temperature lower than 700V. 16. According to the method of applying for item i in the scope of patent application, a conductive material is formed into a pillar and added with salt. I _ -25- This paper · size applies to China Solid Standard (CNS) A4 specification (210X297 mm) 556238 The electrode is defined by a cylindrical wall and a bottom wall extending from the surface of the conductive plug, wherein the cylindrical wall extends upward from the bottom wall and leaves the surface of the interlayer insulation layer; wherein the cylindrical wall of the cylindrical electrode is formed by an upper cylindrical wall portion The lower cylindrical wall portion and the cylindrical wall portion defined between the upper and lower cylindrical wall portions; where the further away from the bottom wall surface, the diameter of the upper cylindrical wall portion and the diameter of the lower cylindrical wall portion increase, where The diameter of the middle cylindrical wall portion decreases as it gets farther from the bottom wall surface, and A-C, C &B; and C &D; where A is the diameter of the upper cylindrical wall portion farthest from the bottom wall surface, B The diameter of the upper cylindrical wall portion nearest the bottom wall surface, C is the diameter of the lower cylindrical wall portion furthest from the bottom wall surface, and D is the diameter of the lower cylindrical wall portion at the bottom wall. 17. A method of manufacturing a capacitor, comprising forming a lower electrode on an interlayer insulating layer, forming a dielectric layer on a lower electrode, and forming an upper electrode on the dielectric layer, wherein the step of forming the lower electrode includes: on the interlayer An etch stop layer is formed on the surface of the insulating layer and on the surface of a conductive plug, and the conductive plug extends a depth into the surface of the interlayer insulating layer; a mold layer is deposited on the etch stop layer, and the lower mold layer is formed during the formation of the lower mold layer. Adding dopants, and adjusting the wet etching ratio of the lower mold layer by annealing the lower mold layer; depositing an upper mold layer on the surface of the lower mold layer, wherein the wet etching ratio of the upper mold layer is less than the adjusted lower mold layer Layer wet-etching ratio; dry-etch the upper mold layer, the lower mold layer and the etch stop layer to form an opening 6. The patent application park shall expose at least a part of the surface of the contact plug; wet etching of the upper mold layer and the lower mold layer causes the opening of the lower mold layer and exposes the surface portion of the etch stop layer adjacent to the surface of the conductive plug and the electrical plug A conductive material is deposited on the exposed surface. 18: The method of applying for item 17 of the patent scope, wherein the forming of the lower electrode still deposits an insulating layer on the conductive material and in the opening; removing-part of the insulating layer and conductive material to expose the upper mold layer; and removing the insulating layer Residue and upper and lower mold layers. 19. As claimed: The method of item 17 of the patent, wherein the lower mold layer is formed by depositing a doped oxide with a chemical gas. 2．If the method of the 17th scope of the patent application is applied, at least one of the vermiculite salt glass (BPSG) and the acid salt glass (psG) is used to form the lower mold layer 21 The method of claim 4, wherein the upper mold layer is formed by plasma-enhanced chemical deposition with undoped oxide. 22. The method according to item 17 of the patent application, wherein at least one of electro-enhanced mono-orthosilicate (PE-TEOS) 'high-density electro-chemical (HDp) oxide and p_SiH oxide is used to form an upper mold layer . 23. The method of claim 17 in which the lower mold layer is formed of borophosphosilicate glass (BPSG), and the phosphorus and boron systems are added to the BPSG before the annealing. 24. The method according to item 23 of the scope of patent application, wherein boron is added in an amount of 2 to 3 parts by weight, and BPSG22-3 is added in an amount of -27 to 27-wrapped with hyaluronic acid and 100 papers. The standard is applicable to China National Sample Standard (CNS) A4 specification (210X 297) 556238 ABCD VI. Patent application park '1 ~ Fill in. 25. The method of claim 17 in which the lower mold layer is formed of phosphosilicate glass (PSG), and the filler is added to mg before the annealing. 26. The method of claim 25, wherein phosphorus is added in an amount of less than 5 weight percent of pSG. 27. The method according to item 17 of the scope of patent application, further comprising, before the formation of the upper mold layer, first removing the surface of the lower mold layer having an adjusted wet erosion ratio. 28. The method of claim 27, wherein hj% is used to remove the surface of the lower mold layer. 29. The method according to claim 17 in which the conductive layer is deposited as a polycrystalline silicon by low-pressure chemical gas deposition. 30. The method according to item 17 of the patent application scope, wherein at least one of sci (NH4OH / H2O2 / deionized water) and HF (hydrofluoric acid) is used to wet the upper mold layer and the lower mold layer. 31. The method according to item 17 of the application, wherein the etch stop layer is silicon nitride, and the annealing of the lower mold layer is performed at a temperature lower than 700 ° C. 32. The method of claim 18, wherein the conductive material forms a cylindrical electrode, which is defined by a cylindrical side wall and a bottom wall extending from the surface of the conductive plug, wherein the cylindrical side wall extends upward from the bottom wall and away from the interlayer insulation layer. The surface of the cylindrical electrode is defined by an upper cylindrical wall portion, a lower cylindrical wall portion, and an intermediate cylindrical sidewall portion located between the upper and lower cylindrical wall portions; wherein the diameter of the upper cylindrical wall portion and The farther the diameter of the lower cylindrical wall part is 2. The patent application increases as the distance from the bottom wall surface increases, and the diameter of the intermediate cylindrical side wall portion of the iif decreases as it recedes from the bottom wall surface. Among them, A-C, C &gt; B, and c &D; where A is a cylindrical wall. The position where the part is furthest from the bottom wall surface is the diameter of the position where the upper cylindrical wall part is closest to the bottom wall surface. C is the diameter of the position where the lower cylindrical wall part is furthest from the bottom wall surface, and D is the lower cylindrical wall part. Diameter at the bottom wall. Two 33 ·· Capacitors, comprising a sandwich insulation layer with a surface; a conductive plug extending from the surface of the sandwich insulation layer to a depth; an etch stop layer extending on the insulation layer and exposing the conductive plug; The electrode is defined by a cylindrical side wall and a bottom wall. The cylindrical lower electrode is extended on the surface of the conductive plug and a part of the etching stop layer adjacent to the conductive plug. The cylindrical side wall extends upward from the bottom wall and away from the surface of the interlayer insulation layer. A dielectric layer is formed on the cylindrical lower electrode; and an upper electrode is formed on the dielectric layer; wherein the cylindrical side wall of the cylindrical lower electrode is composed of an upper cylindrical wall portion, a lower cylindrical wall portion, and an upper and a lower cylindrical portion. The space between the lower cylindrical wall part is defined by the columnar sidewall part; the diameter of the upper cylindrical wall part and the diameter of the lower cylindrical wall part increase as the distance from the bottom wall surface increases, and the diameter of the middle cylindrical side wall part is more reverse. The lower the bottom wall surface, and among them A-C, C &B; and C> D -29- This paper size is suitable for towels ® 8 standards (CNS) A4 specifications (210X297 mm) 556238 8 8 8 8 A B c D VI. The scope of patent application, where A is the diameter of the upper cylindrical wall part farthest from the bottom wall surface, B is the diameter of the upper cylindrical wall part closest to the bottom wall surface, and C is the lower cylindrical wall part The diameter of the position farthest from the bottom wall surface, and D is the diameter of the lower cylindrical wall portion at the bottom wall. 34. The capacitor of claim 33, wherein the etch stop film is a silicon nitride film. 35. The capacitor according to item 33 of the patent application, wherein the lower electrode is a polycrystalline silicon electrode. 36. The capacitor of claim 33, wherein the dielectric layer is a nitric oxide (NO) layer. -30- This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)