554466 五、發明説明（ 經濟部智慧財產局員工消費合作社印製 5-1發明領递： 本發明係有關於半導體元件及製造方法，特別是有關 於一種在絕緣層碎基材上之高功率半導體元件及製造方 法。 5-2發明背景： 雙載子連接電晶體（BJT)為現今最重要的半導體元件 之一，這種元件雖然可作為高功率半導體元件及高^邏輯 電路之用，但是在操作的過程中消耗大量的能量。目前， 金氧半場效電晶體（MOSFET)的發展，已經逐漸取代了雙 載子電晶體之應用。由於其能節省電能的緣故，金氧半場 效電晶體已成為積體電路中最常被使用的半導體元件。 在傳統技術中，功率型金氧半場效電晶體（p〇WER Μ 0 S F E T)的基本操作和任何的金氧半場效電晶體相同，但 疋其流通電流可達數安培。此外，功率型金氧半場效電晶 體的優點是可以在耗費低功率的狀況下，利用小控制電壓 進行元件的操作。 第1圖顯示傳統高功率半導體元件的剖面示意圖。高 功率半導體元件具有一基材100、第一源極區102、第二 源極區104、汲極106、基體區108及閘極1 10。其中第一 源極區102及第二源極區104位於基材100中，且第一源 極區102及第二源極區104之間的基材1 00上設有閘極 1 10，而在基材100的下方設有汲極106。 當高功率半導體元件進行操作時，電子由第一源極區554466 V. Description of the invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 5-1 Invention Delivery: This invention relates to semiconductor components and manufacturing methods, especially to a high-power semiconductor on a broken insulating substrate 5-2 Background of the Invention: BJT is one of the most important semiconductor devices today. Although this device can be used for high power semiconductor devices and high logic circuits, A large amount of energy is consumed during the operation. At present, the development of metal-oxide-semiconductor field-effect transistors (MOSFETs) has gradually replaced the application of bipolar transistors. Because of its ability to save electricity, metal-oxide-semiconductor half-effect transistors have been used. Becomes the most commonly used semiconductor element in integrated circuits. In the traditional technology, the basic operation of power metal-oxide-semiconductor field-effect transistor (POWER M 0 SFET) is the same as that of any metal-oxide-semiconductor field-effect transistor, but 疋Its current can reach several amperes. In addition, the power metal-oxide half field effect transistor has the advantage that it can use a small control voltage under the condition of low power consumption Perform the operation of the device. Figure 1 shows a schematic cross-sectional view of a conventional high-power semiconductor device. The high-power semiconductor device has a substrate 100, a first source region 102, a second source region 104, a drain 106, a base region 108, and Gate 1 10. The first source region 102 and the second source region 104 are located in the substrate 100, and a gate is provided on the substrate 100 between the first source region 102 and the second source region 104. The electrodes 1 and 10 are provided under the substrate 100. When a high-power semiconductor element is operated, electrons pass through the first source region
I 背 面 5 意 事 項 再 場m本裝 訂 § 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 經濟部智慧財產局員工消費合作社印製 554466 A7 _____B7 _ 五、發明説明（） 102及第二源極區1〇4垂直地向下流動，經過基材1〇〇中 不同濃度的井區100a，100b，而流向沒極區1〇6。 由於源極區1 02,1 04與汲極區1 〇6之間的電子只能以 單一垂直方向流動，亦即源極區丨〇2,1 〇4與汲極區1 06的 電阻值較高，使得高功率半導體元件的操作速度無法提 升。而且基材100中之不同濃度井區l〇〇a，丨〇〇b之間的接 面電容值較高，將減低高功率半導體元件的切換速度，更 會影響源極區1 02,1 04與汲極區丨〇6之間的電子流動，降 低元件的操作速度。 因此，如何改善高功率半導體元件的電流流通能力， 以及I疋升南功率半導體元件的切換速度之問題，已經成為 目前半導體業界亟需解決的課題。 g_-3發明目的及概述： 本發明之一目的為利用高功率半導體元件及製造方 法’在源極區與沒極區之間形成橫形及立形的汲極連接結 構’提升高功率半導體元件的電流流通能力。 本發明另一目的為利用高功率半導體元件及製造方 法’藉由絕緣層碎基材之緩衝氧化層，以減少高功率半導 體元件的接面電容值。 根據上述之目的，本發明提出一種在絕緣層矽基材上 之高功率半導體元件及製造方法，製造方法包含下列步 驟·首先，依序於主動區及場氧化區上形成閘氧化層及第 一導電層。接著進行第一微影蝕刻製程，以分別於閘氧化 • 3 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) (說先閲讀背面之注意事項再填寫本頁) _ 554466 經濟部智慧財產局員工消費合作社印製I Back 5 Reminders on the back page m Binding § This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 554466 A7 _____B7 _ V. Description of the invention () 102 The second source region 104 flows vertically downward, passes through well regions 100a and 100b of different concentrations in the substrate 100, and flows to the non-electrode region 106. Since the electrons between the source region 102, 104 and the drain region 106 can only flow in a single vertical direction, that is, the resistance value of the source region 〇 02,104 and the drain region 106 is relatively small. High, making it impossible to increase the operating speed of high-power semiconductor elements. In addition, the high junction capacitance between 100a and 100b in well regions of different concentrations in the substrate 100 will reduce the switching speed of high-power semiconductor elements and affect the source region 1 02, 1 04. The electron flow between the drain region and the drain region reduces the operation speed of the device. Therefore, how to improve the current flow capability of high-power semiconductor devices and the switching speed of power semiconductor devices has become an urgent issue for the semiconductor industry. g_-3 Object and summary of the invention: One object of the present invention is to improve the high-power semiconductor device by using a high-power semiconductor device and a manufacturing method of forming a horizontal and vertical drain connection structure between the source region and the non-electrode region. Current carrying capacity. Another object of the present invention is to use a high-power semiconductor element and a manufacturing method 'to break the buffer oxide layer of the substrate by the insulating layer, so as to reduce the junction capacitance value of the high-power semiconductor element. According to the above object, the present invention proposes a high-power semiconductor element and a manufacturing method on an insulating silicon substrate. The manufacturing method includes the following steps. First, a gate oxide layer and a first oxide layer are sequentially formed on an active region and a field oxide region. Conductive layer. Then the first lithography etching process is performed to oxidize the gates separately. 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). (Please read the precautions on the back before filling this page) _ 554466 Ministry of Economic Affairs Printed by the Intellectual Property Bureau Staff Consumer Cooperative
層上形成閘極，形成第一開口於鄰接閘極的主動區上，以 及形成第：開口於鄰接場氧化區的主動區丨。然後，形成 第-罩幕層’以覆蓋閘，且曝露第一開口。並進行第一 摻雜，以形成基體區於第一開口之基材中。 接著移除第-罩幕層，以曝露主動區之第一開口及第 二開口。進行第二摻雜，以形成源極區於第一開口之基體 區中，且形成沒極區於第二開口之基材中。然後依序形成 第一介電層及第二罩幕層，以覆蓋閘極。並且進行第二微 〜蝕刻製程，以曝露源極區、汲極區、基體區及一部份的 基材，其中源極區與汲極區之間的漂移區，於源極區形成 第一接觸窗，並於沒極區形成第二接觸窗。接著經第三罩 幕層，矽蝕刻及緩衝氧化層蝕刻。隨後形成第二導電層， 以填入第一接觸窗及第二接觸窗，其中第二導電層高於第 二介電層。最後進行平坦化製程，以移除一部份的第二導 電層’並曝露第二介電層，以形成導電插塞。 具體而言，本發明的高功率半導體元件進行操作時， 一部份的載子由源極區經過通道區及漂移區橫向地移動 至汲極區，接著載子利用導電插塞移動至導電層，而且另 一部份的載子由源極區經過通道區及漂移區，藉由導電插 塞縱向地移動至基材的基板，然後流向基材下方的導電 層。換言之，來自源極區的具有兩個流動方向，水平及垂 直方向，並且移動至基材上方及下方的導電層，利用在源 極區與汲極區之間形成橫形及立形的汲極連接結 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閱讀背面之注意事項.再填寫本頁) 554466A gate is formed on the layer, a first opening is formed on the active region adjacent to the gate, and a first: opening is formed on the active region adjacent to the field oxidation region. Then, a first mask layer is formed to cover the gate, and the first opening is exposed. A first doping is performed to form a base region in the substrate with the first opening. Then, the first mask layer is removed to expose the first opening and the second opening of the active area. A second doping is performed to form a source region in the base region of the first opening, and a non-electrode region in the substrate of the second opening. A first dielectric layer and a second mask layer are sequentially formed to cover the gate electrode. And a second micro-etching process is performed to expose the source region, the drain region, the base region, and a part of the substrate. The drift region between the source region and the drain region forms a first region in the source region. A contact window, and a second contact window is formed in the non-polar region. Then through the third mask layer, silicon etching and buffer oxide etching. A second conductive layer is subsequently formed to fill the first contact window and the second contact window, wherein the second conductive layer is higher than the second dielectric layer. Finally, a planarization process is performed to remove a part of the second conductive layer 'and expose the second dielectric layer to form a conductive plug. Specifically, when the high-power semiconductor element of the present invention is operated, a part of the carriers are laterally moved from the source region to the drain region through the channel region and the drift region, and then the carriers are moved to the conductive layer by using conductive plugs. In addition, another part of the carrier moves from the source region through the channel region and the drift region, and is moved longitudinally to the substrate of the substrate by the conductive plug, and then flows to the conductive layer below the substrate. In other words, the source region has two flowing directions, horizontal and vertical, and is moved to the conductive layer above and below the substrate, utilizing the formation of horizontal and vertical drain electrodes between the source region and the drain region. The paper size of the connection paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 554466
五、發明説明( 上，使高功率半導體元件的PN接面電容值大為減低。特 定而言，源極區與汲極區間的橫形及立形汲極連接結構， 的低電阻值，以及低的PN接面電容值，以有效提高元件 的操作速度。 總之，本發明利用絕緣層矽基材上的高功率半導體元 件及製造方法，利用橫形及立形的汲極連接結構，降低高 功率半導體元件的電阻值。並且藉由絕緣層_基材的絕緣 層，降低高功率半導體元件的接面電容值，以提高半導體 元件的汲極電流。 g-4圖式簡單說明： 第1圖繪示傳統高功率半導體元件之剖面示意圖；以及 第2-12圖繪示依據本發明一較佳實施例之一高功率半導 體元件的製造流程剖面示意圖。 .............•裝： (、請先閲讀背面之注意事項再場寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 5-5 圖號對照說明： 100 基材 100a ,100b 井區 102 第一源極區 104 第二源極區 106 汲極 108 基體區 1 10 閘極 200 基材 202 第一介電層 204 基板 206 緩衝氧化層 208 珍層 210 主動區 212 場氧化區 214 閘氧化層 § 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 554466 A7 B7 經濟部智慈財產局員工消費合作社印製 五、發明説明（） 216 導電層 218 閘極 220 第一開口 222 第二開口 224 第一罩幕層 225 第一罩幕層 226 源極區 228 沒極區 230 第三罩幕層 232 第二介電層 234 第二罩幕層 236 第一接觸窗 238 橫形連接結構 240 通道區 242 漂移區 244 第—接觸窗 246 導電層 248 導電插塞 250,252 導電層 254 立形連接結構 5-6發明詳細說明： 針對傳統高功率半導體元件的缺點，本發明提供一種 絕緣層矽基材上的高功率半導體元件及製造方法，利用橫 形（Lateral)及立形（Vertical)的汲極連接結構，使載子在源 極區與汲極區之間產生水平及垂直方向的流動。並且利用 絕緣層矽基材上的緩衝氧化層，降低高功率半導體元件的 接面電容值。 首先參閱第2 -1 2圖，繪示本發明一較佳實施例之一 高功率半導體元件的製造流程剖面示意圖。在第2圖中， 於基材2 0 0上形成弟一介電層2 0 2 ’例如以化學氣相：冗積 (Chemical Vapor Deposition，CVD)法形成第一介電層 202,第一介電層202的材質例如可為氧化矽（si〇2)或是氣 化矽（ShN4)，其中第一介電層202的厚度介於1埃至 6 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) ,I...........«^---------、可......... (請先閲讀背面之注意事項再場寫本頁) 554466 A7 B7 五、發明説明（） 1 Ο μ m。基材 2 0 0例如可為絕緣層碎基材（S i 1 i c ο η ο η Insulator，SOI)或是一般矽晶圓材質。 ("請先閲讀背面之注意事項再填寫本頁) 具體而言，絕緣層矽基材（SOI)包含基板2 04、緩衝氧 化層206及矽層208。其中基板204的材質可為N型或P 型，緩衝氧化層206的厚度介於1埃至1〇 μιτ1，矽層208 材質可為Ν型或Ρ型，其厚度介於1〇〇埃至looopm。 接著在第3圖中，進行第一微影蝕刻製程，藉由第一 介電層202，以於基材200上形成主動區210及場氧化區 212。隨後在第4圖中，於主動區210及場氧化區212上 依序形成閘氧化層2 1 4與導電層2 1 6。例如以熱氧化 (Thermal Oxidation)法形成閘氧化層214，閘氧化層 214 的厚度介於1至2000埃。而以低壓化學氣相沉積（L〇w5. Description of the invention (above, the capacitance value of the PN junction of the high-power semiconductor element is greatly reduced. In particular, the horizontal and vertical drain connection structures of the source region and the drain region, the low resistance value, and Low PN junction capacitance value to effectively improve the operating speed of the device. In short, the present invention uses high-power semiconductor components and manufacturing methods on a silicon substrate with an insulating layer, and uses horizontal and vertical drain connection structures to reduce the high The resistance value of the power semiconductor element. And through the insulating layer_the insulating layer of the substrate, the junction capacitance value of the high power semiconductor element is reduced to increase the drain current of the semiconductor element. The g-4 diagram is briefly explained: Figure 1 A schematic sectional view of a conventional high-power semiconductor device is shown; and FIGS. 2-12 are schematic sectional views of a manufacturing process of a high-power semiconductor device according to a preferred embodiment of the present invention. .. • Installation: (Please read the notes on the back before writing this page) Order the 5-5 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, drawing number comparison description: 100 substrate 100a, 100b well area 102 first Source 104 Second source region 106 Drain 108 Base region 1 10 Gate 200 Substrate 202 First dielectric layer 204 Substrate 206 Buffer oxide layer 208 Rare layer 210 Active region 212 Field oxide region 214 Gate oxide layer § Applicable to this paper standard Chinese National Standard (CNS) A4 specification (210x297 mm) 554466 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs 5. Description of the invention () 216 conductive layer 218 gate 220 first opening 222 second opening 224 first Mask layer 225 First mask layer 226 Source region 228 Non-polar region 230 Third mask layer 232 Second dielectric layer 234 Second mask layer 236 First contact window 238 Horizontal connection structure 240 Channel region 242 Drift Zone 244—contact window 246 conductive layer 248 conductive plug 250, 252 conductive layer 254 vertical connection structure 5-6 Detailed description of the invention: Aiming at the shortcomings of traditional high power semiconductor components, the present invention provides a high power on an insulating silicon substrate Semiconductor device and manufacturing method, using horizontal and vertical drain connection structure, so that carriers generate horizontal and vertical between source region and drain region Flow in the direction. And the buffer oxide layer on the silicon substrate of the insulating layer is used to reduce the junction capacitance value of the high-power semiconductor element. First, referring to FIGS. 2 to 12, a high power according to a preferred embodiment of the present invention is shown. A schematic cross-sectional view of a manufacturing process of a semiconductor device. In FIG. 2, a first dielectric layer 2 02 ′ is formed on a substrate 200, for example, a first method is formed by a chemical vapor deposition (CVD) method. The dielectric layer 202 and the material of the first dielectric layer 202 may be, for example, silicon oxide (SiO2) or siliconized silicon (ShN4). The thickness of the first dielectric layer 202 ranges from 1 Angstrom to 6 papers. Applicable to China National Standard (CNS) A4 specification (210x297 mm), I ........... «^ ---------, but ......... ( Please read the notes on the back before writing this page) 554466 A7 B7 V. Description of the invention () 1 〇 μ m. The substrate 2 0 0 may be, for example, a broken substrate (Si 1 i c ο η η η Insulator, SOI) or a general silicon wafer material. (" Please read the precautions on the back before filling this page) Specifically, the insulating silicon substrate (SOI) includes the substrate 204, the buffer oxide layer 206, and the silicon layer 208. The material of the substrate 204 may be N-type or P-type, the thickness of the buffer oxide layer 206 is between 1 angstrom and 10 μmτ1, and the silicon layer 208 may be N-type or P-shaped, with a thickness between 100 angstrom and looopm. . Next, in FIG. 3, a first lithographic etching process is performed, and an active region 210 and a field oxidation region 212 are formed on the substrate 200 by the first dielectric layer 202. Subsequently, in FIG. 4, a gate oxide layer 2 1 4 and a conductive layer 2 1 6 are sequentially formed on the active region 210 and the field oxide region 212. For example, the gate oxide layer 214 is formed by a thermal oxidation method. The thickness of the gate oxide layer 214 is between 1 and 2000 angstroms. With low pressure chemical vapor deposition (L0w
Pressure Chemical Vapor Deposition，LPCVD)法沉積導電 層2 1 6 ’導電層2 1 6例如可為複晶碎層，複晶碎層的厚度 介於1埃至ΙΟμπι。 在第5圖中，進行第二微影蝕刻製程，藉由導電層 2 1 6 ’以於閘氧化層2 1 4上形成閘極2 1 8，並且在鄰接閘極 218的主動區210上形成第一開口 220,以及在鄰接場氧 化區2 1 2的主動區2 1 0上形成第二開口 222。 經濟部智慧財產局員工消費合作社印製 接著在第6圖中，形成第一罩幕層2 24,例如光阻層， 以覆蓋於閘極2 1 8上，並且曝露主動區2 1 〇的第一開口 2 2 0。接著利用佈植製程及高溫擴散法進行換雜，以於第 一開口 220之基材200中形成基體區（B〇dy RegiQn)224, 其中高溫擴散法的溫度介於500至20001：之間，捧質例如 7The Pressure Chemical Vapor Deposition (LPCVD) method is used to deposit the conductive layer 2 1 6 ′. The conductive layer 2 1 6 may be, for example, a multicrystalline fragment layer having a thickness of 1 angstrom to 10 μm. In FIG. 5, a second lithography etching process is performed. A gate electrode 2 1 8 is formed on the gate oxide layer 2 1 4 by a conductive layer 2 1 6 ′, and is formed on an active region 210 adjacent to the gate electrode 218. The first opening 220 and a second opening 222 are formed in the active region 2 10 adjacent to the field oxidation region 2 12. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and then in FIG. 6, a first cover layer 2 24, such as a photoresist layer, is formed to cover the gate 2 1 8 and expose the active area 2 1 0. An opening 2 2 0. Then, the implantation process and the high-temperature diffusion method are used to perform hybridization to form a base region (Body RegiQn) 224 in the substrate 200 of the first opening 220. The temperature of the high-temperature diffusion method is between 500 and 20001: Holding quality such as 7
554466 五 經濟部智慧財產局員工消費合作社印製 發明説明（ 可為硼、磷或珅。或是利用第一 奸 離子佈植法形成基體區 224,弟一離子佈植的濃度介於丨Χ1010至丨xl〇i8/cm2。 在第7圖中，移除第一罩幕層 m 、切 早恭層225,以曝露主動區210 又第一開口 220及第二開口 222。 ,, 接耆進行第二離子佈 植，以於第一開口 220之基體區22 甲开》成源極區226， 且於第二開口 220之基材200 Φ犯1 1 千形成汲極區228 ,其中第554466 Printed invention description of employee cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (may be boron, phosphorus, or thorium. Or use the first ion implantation method to form the matrix region 224, and the concentration of the younger ion implantation is between X1010 to丨 x10i8 / cm2. In Fig. 7, the first cover layer m and the early layer 225 are removed to expose the active area 210 and the first opening 220 and the second opening 222. Then, proceed to the first step. The two-ion implantation is such that the source region 226 is formed in the base region 22 of the first opening 220, and the substrate 200 in the second opening 220 is φ1 1 thousand to form the drain region 228.
二離子佈植的濃度介於1\1〇1〇至1U 王1X10 /cm2。此外，第二 離予佈植的電性（P型或N型）與某耖F ^ ^ 土 丞髖區224的電性（n型或 p型）相反。 本發明較佳實施例中，在移除第一罩幕層224之後， 亦可形成第三罩幕層230 ,例如光阻層，以覆蓋一部份的 基體區224,藉由第二離子佈植製程形成多個源極區226 , 例如一個基體區224中括二個源極區226 ,以增加元件的 集積度。 接著在第8圖中，形成第二介電層232以覆蓋於閘極 218上。第二介電層232例如可為磷矽玻璃（PSG)或是硼磷 碎玻璃（BPSG) ’其中利用常壓化學氣相沉積（AtmoSpheric Pressure Chemical Vapor Deposition, APCVD)法沉積磷矽 玻璃（PSG)’而以電衆增強化學氣相沉積（piasma-enhanced Chemical Vapor Deposition, PECVD)法沉積硼磷矽玻璃 (BPSG)，且第二介電層232的厚度介於1埃至ΙΟμηι。 在第9圖中，於第二介電層232上形成第二罩幕層234 並進行第三微影蝕刻製程，以分別曝露基材200之源極區 226、汲極區228及基體區224，以於源極區226形成第一 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) *^、可 Γ請先閲讀背面之注意事項再場寫本頁) A7The concentration of diion implantation was between 1 \ 1010 and 1U Wang 1X10 / cm2. In addition, the electrical properties of the second implantation (P-type or N-type) are opposite to the electrical properties (n-type or p-type) of a 耖 F ^ soil 丞 hip region 224. In a preferred embodiment of the present invention, after removing the first mask layer 224, a third mask layer 230, such as a photoresist layer, may be formed to cover a part of the base region 224, and a second ion cloth is used. The implantation process forms a plurality of source regions 226, for example, one base region 224 includes two source regions 226, so as to increase the degree of component integration. Then in FIG. 8, a second dielectric layer 232 is formed to cover the gate electrode 218. The second dielectric layer 232 may be, for example, phosphosilicate glass (PSG) or borophosphorus shattered glass (BPSG), wherein the phosphosilicate glass (PSG) is deposited using the AtmoSpheric Pressure Chemical Vapor Deposition (APCVD) method. 'Phosma-enhanced Chemical Vapor Deposition (PECVD) method is used to deposit borophosphosilicate glass (BPSG), and the thickness of the second dielectric layer 232 is between 1 Angstrom and 10 μηι. In FIG. 9, a second mask layer 234 is formed on the second dielectric layer 232 and a third lithography process is performed to expose the source region 226, the drain region 228, and the base region 224 of the substrate 200, respectively. Based on the formation of source paper 226, the first paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) * ^, but please read the precautions on the back before writing this page) A7
554466 五、發明説明（） 接觸窗236，並於汲極區228形成橫形連接結構238，橫 形連接結構238包括通道區240及漂移區242 ,其中通道 區位240於部份的基體區224中，而漂移區242位於源極 區226與汲極區228之間的基材200中。 然後在第10圖中，利用微影蝕刻製程蝕刻絕緣層矽 基材200之矽層208及緩衝氧化層2〇6，並曝露出絕^層 矽基材200之基板204，以於汲極區228形成第二接觸窗 244 〇 接著在第11圖中，於第二介電層232上形成導電層 246，以填入第一接觸窗236與第二接觸窗244，其中導電 層246高於第二介電層232。而導電層244的材質例如可 為金屬鎢（W)，導電層246的厚度介於】埃至1〇μηι，以低 壓化學氣相沉積（LPCVD)形成金屬鎢。 最後在第12圖中，進行平坦化製程，以移除一部份 的導電層246，並曝露第二介電層232，以形成導電插塞 248，其中導電插塞248與基材200之基板204接觸，形 成立形連接結構254。並且在基材200的底面形成一導電 層250，例如鋁金屬層或是矽化金屬層，以連接導電插塞 248。較佳實施例中，平坦化製程包括化學機械研磨 (Chemical Mechanical Polishing, CMP)法或是回蚀 (Etching Back)法。 具體而言，本發明的高功率半導體元件進行操作時， 一部份的載子由源極區2 2 6經過通道區2 4 0及漂移區2 4 2 橫向地移動至汲極區2 2 8，接著載子利用導電插塞2 4 8移 9 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ............·裝.........訂.........» 〇請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 554466 A7 B7 五、發明説明（） 動至導電層250，而且另一部份的載子由源極區226經過 通道區240及漂移區242，藉由導電插塞248縱向地移動 至基材200的基板204,然後流向基材下方的導電層252。 由於導電插塞248穿入基材中，且與基板204接觸， 使來自源極區226的具有兩個流動方向，水平及垂直方 向，並且移動至基材200上方及下方的導電層25〇,252， 利用在源極區226與汲極區228之間形成橫形及立形的汲 極連接結構23 8,254 ,有效提高元件的電流流通性，增加 元件的操作效率。 更重要的是，本發明的高功率半導體元件係利用絕緣 層矽基材，其中基體區2 42位於絕緣層矽基材之緩衝氧化 層2 06上，使高功率半導體元件的pN接面電容值大為減 低。特定而言，源極區226與汲極區228間的橫形及立形 汲極連接結構238，254的低電阻值，以及低的pN接面電 容值，以有效提高元件的操作速度。 综上所述，本發明利用絕緣層矽基材上的高功率半導 體元件及製造方法，利用橫形及立形的汲極連接結構，使 載子在源極區與沒極區之間形成水平及垂直方向的電流 流動’以降低高功率半導體元件的電阻值。並且藉由絕緣 層碎基材的絕緣層，降低高功率半導體元件的接面電容 值’以提高半導體元件的汲極電流。因此，本發明之高功 率半導體元件具有高速切換、低電阻的優點。 本發明已揭示較佳實施例如上，僅用於幫助暸解本發 明之實施，非用以限定本發明之精神，而熟悉此領域技藝 10 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) .............·裝丨丨 (請先閲讀背面之注意事項再填、寫本頁} -、νΰ Φ 經濟部智慧財產局員工消費合作社印製 554466 A7 _B7 五、發明説明（） 者於領悟本發明之精神後，在不脫離本發明之精神範圍 内，當可作些許更動潤飾及等同之變化替換，其專利保護 範圍當視後附之申請專利範圍及其等同領域而定。 (，請先閲讀背面之注意事項再填寫本頁) 經濟部智慈財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)554466 V. Description of the invention () The contact window 236 forms a horizontal connection structure 238 in the drain region 228. The horizontal connection structure 238 includes a channel region 240 and a drift region 242. The channel region 240 is located in a part of the base region 224. The drift region 242 is located in the substrate 200 between the source region 226 and the drain region 228. Then, in FIG. 10, the silicon layer 208 and the buffer oxide layer 206 of the insulating silicon substrate 200 are etched by a lithographic etching process, and the substrate 204 of the insulating silicon substrate 200 is exposed to the drain region. 228 forms a second contact window 244. Next, in FIG. 11, a conductive layer 246 is formed on the second dielectric layer 232 to fill the first contact window 236 and the second contact window 244. The conductive layer 246 is higher than the first contact window 244. Two dielectric layers 232. The material of the conductive layer 244 may be, for example, metal tungsten (W), and the thickness of the conductive layer 246 is in the range of Angstroms to 10 μm. The metal tungsten is formed by low pressure chemical vapor deposition (LPCVD). Finally, in FIG. 12, a planarization process is performed to remove a part of the conductive layer 246 and expose the second dielectric layer 232 to form a conductive plug 248, wherein the conductive plug 248 and the substrate of the substrate 200 are formed. 204 contacts to form a vertical connection structure 254. A conductive layer 250, such as an aluminum metal layer or a silicided metal layer, is formed on the bottom surface of the substrate 200 to connect the conductive plug 248. In a preferred embodiment, the planarization process includes a Chemical Mechanical Polishing (CMP) method or an Etching Back method. Specifically, during the operation of the high-power semiconductor device of the present invention, a part of the carriers move laterally from the source region 2 2 6 to the channel region 2 4 0 and the drift region 2 4 2 to the drain region 2 2 8 Then, the carrier uses conductive plugs 2 4 8 shift 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ............ installed ...... ... Order ......... »〇 Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 554466 A7 B7 V. Description of the invention () Move to the conductive layer 250, and the other part of the carrier moves from the source region 226 through the channel region 240 and the drift region 242, and moves longitudinally to the substrate 204 of the substrate 200 through the conductive plug 248, and then flows to the conductive layer 252 below the substrate . Since the conductive plug 248 penetrates into the substrate and is in contact with the substrate 204, it has two flow directions from the source region 226, horizontal and vertical, and moves to the conductive layer 25 above and below the substrate 200. 252, utilizing horizontal and vertical drain connection structures 23,254 formed between the source region 226 and the drain region 228 to effectively improve the current flow of the device and increase the operating efficiency of the device. More importantly, the high-power semiconductor element of the present invention uses an insulating silicon substrate, wherein the base region 2 42 is located on the buffer oxide layer 2 06 of the insulating silicon substrate, so that the pN junction capacitance value of the high-power semiconductor element is Greatly reduced. In particular, the low resistance values of the horizontal and vertical drain connection structures 238, 254 between the source region 226 and the drain region 228, and the low pN junction capacitance value, effectively improve the operation speed of the device. In summary, the present invention utilizes high-power semiconductor elements and manufacturing methods on a silicon substrate with an insulating layer, and uses horizontal and vertical drain connection structures to form carriers horizontally between the source region and the non-electrode region. And vertical current flow 'to reduce the resistance value of the high-power semiconductor element. In addition, the insulation layer of the base material is used to reduce the junction capacitance value of the high-power semiconductor element 'to increase the drain current of the semiconductor element. Therefore, the high-power semiconductor element of the present invention has the advantages of high-speed switching and low resistance. The above-mentioned preferred embodiments of the present invention have been disclosed. They are only used to help understand the implementation of the present invention. They are not intended to limit the spirit of the present invention. They are familiar with the art in this field. (Li) ............. Installation 丨 丨 (Please read the notes on the back before filling out and write this page}-, νΰ Φ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 554466 A7 _B7 V. Description of the invention () After understanding the spirit of the invention, those who do not depart from the spirit of the invention can make some minor modifications and equivalent changes. The scope of patent protection shall be regarded as the scope of the attached patent. It depends on its equivalent field. (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs This paper is sized for the Chinese National Standard (CNS) A4 (210X297 mm)