201112419 I 1 六、發明說明： 【發明所屬之技術領域】 本發明係關於金氧半電晶體及其製程方法，特別係關 於溝槽式（trench-type)功率金氧半電晶體（power MOS transistor)及其製程方法。 【先前技術】 功率金氧半電晶體係一種特殊的金氧半電晶體，專門 用以提供及切換電源給積體電路。據此，功率金氧半電晶 ® 體需具有在高電壓下工作之能力。一般功率金氧半電晶體 係以互補金氧半電晶體（CMOS )製程製作以達到大尺寸之 目的，使其能在高電壓下操作。另一方面，功率金氧半電 晶體又需能提供大輸出電流。因此，一般製作上多將數千 至數十萬個電晶體單元聚集成一功率金氧半電晶體，其中 每一電晶體單元可輸出一小電流，而該聚集成之功率金氧 半電晶體則可輸出一大電流。然而，依此製造方法製作之 I 功率金氧半電晶體將佔據過大面積而無法為業界所接受。 為降低功率金氧半電晶體之面積，業界出現了 一種垂 直擴散的金氧半（vertical diffused MOS，VDMOS )電晶體 。圖1顯示一 VDMOS電晶體之刳面示意圖。不同於傳統平 面的CMOS電晶體，電流係以垂直方向流經一 VDMOS電晶 體。如圖1所示，該VDMOS電晶體100之汲極區係位於該 VDMOS電晶體100之頂部，而該VDMOS電晶體100之源極 區係位於該VDMOS電晶體100之底部。圖1之結構使該 VDMOS電晶體100具有高崩潰電壓及高輸出電流。 201112419 圖2顯示另一種溝槽式的金氧半電晶體，即UM〇s電晶 體之剖面示意圖。如圖2所示’該UMOS電晶體2〇〇係得名自 其U型之閘氧化物。該UMOS電晶體2〇〇具有一溝槽式向下 延伸之閘極，而該UMOS電晶體200亦具有一垂直的電流方 向’且該UMOS電晶體200之沒極區係位於該umos電晶體 200之頂部’而該UMOS電晶體200之源極區係位於該uM〇s 電晶體200之底部。 然而’上述具有垂直式結構的金氧半電晶體無法和一 般以CMOS製程製作之積體電路整合於同一片晶片上，因而 增加製作上的複雜度及製作成本。據此，業界所需要的是 一種功率金氧半電晶體，其不僅具有高崩潰電壓、高輸出 電流及高操作速度，且具有水平結構，故能和一般以CM〇s 製程製作之積體電路整合於同一片晶片上。 【發明内容】 本發明之一實施例之溝槽式功率金氧半電晶體包含一 汲極區、一雙擴散滲雜區域、一溝槽式閘極區、一源極區 、一井區、一深井區和一基底區。該汲極區具有一第一導 電類型特性，並連接至一汲極電極。該雙擴散滲雜區域具 有該第一導電類型特性，並位於該汲極區下方。該溝槽式 閘極區延伸至該雙擴散滲雜區域，並具有一閘極導體及一 絕緣層以隔絕該閘極導體。該源極區具有該第一導電類型 特性，並連接至一源極電極。該井區具有一第二導電類型 特性，並位於該源極區下方。該深井區，具有該第一導電 類型特性並位於該雙擴散滲雜區域及該井區下方。該基底 201112419 區位於該深井區下方》該絕緣層係於該閘極導體和該井區 間形成一薄側壁區，於該閘極導體和該雙擴散滲雜區域形 成一厚側壁區，並於該閘極導體和該深井區間形成一厚底 區’且該汲極電極和該源極電極係位於該溝槽式功率金氧 半電晶體之上表面。 本發明之一實施例之溝槽式功率金氧半電晶體之製程 方法’包含下列步驟：形成一具有一第一導電類型特性之 深井區於一基底區上；形成一具有該第一導電類型特性之 一雙擴散滲雜區域之汲極區於該深井區上；於該雙擴散渗 雜區域之侧壁银刻出一溝渠區；填入絕緣材料於該溝渠區 ;於該絕緣材料相對於該雙擴散滲雜區域之外側蝕刻出一 閘極區，使該溝渠區於該閘極區和該雙擴散滲雜區域間具 有一填滿該絕緣材料之厚側壁區，及使該溝渠區於該閘極 區和該深井區間具有一填滿該絕緣材料之厚底區·，填入閘 極導體於該閘極區；形成一具有一第二導電類型特性之井 區於該閘極區旁及該深井區上；形成一具有該第一導電類 型特性之汲極區於該雙擴散滲雜區域上；以及形成一具有 該第一導電類型特性之源極區於該井區上。 【實施方式】 圖3顯示本發明之一實施例之溝槽式功率金氧半電晶 體之剖面示意圖。如圖3所示，該溝槽式功率金氧半電晶體 300包含一基底區302、一深井（deep well)區304 ' —雙擴 一源極區 散滲雜（double diffusion)區域 306、一井（Weu)區 3〇8 、一絕緣層310、一閘極導體312、一沒極區314、 201112419 t i 316、一本體區318、一金屬矽化物層32〇、一層間介電（1扒打 layer dielectric)層322、一第一層金屬層324、一金屬間介 電（inter metal dielectric )層 326及一頂層金屬層 328。 圖3所示之溝槽式功率金氧半電晶體3〇〇為一 n型電晶 體。然而，熟悉此項技術人士可輕易將其轉換為p型電晶體 ’而仍應為本發明所涵蓋。如圖3所示，該沒極區314具有 一N型導電類型特性，並連接至一汲極電極。該雙擴散滲雜 φ 區域306具有該N型導電類型特性，並位於該汲極區314下方 。較佳的，該雙擴散滲雜區域306於靠近該汲極區314之區 域較遠離該汲極區314之區域具有較高之離子濃度。該絕緣 層310係延伸至該雙擴散滲雜區域3〇6，以隔絕該閘極導體 3 12。該絕緣層310和該閘極導體3 12係形成一溝槽式開極區 ’且該溝槽式閘極區係以水平方向環繞該井區3〇8，且一閉 極電極係連接至相對於該汲極區314外侧之該閘極導體312 。該源極區316具有該N型導電類型特性，環繞該本體區318 鲁 ，並連接至一源極電極。該井區308具有一 P型導電類型特 性，並位於該源極區316下方。該深井區304具有該N型導電 類型特性，並位於該雙擴散滲雜區域3〇6及該井區308下方 。該基底區302具有一P型導電類型特性，並位於該深井區 304下方《該金屬矽化物層320係介於該汲極區3 14、該源極 區3 16和該本體區3 18及該等電極之間。該層間介電322係位 於該金屬石夕化物層32〇上方。該第一層金屬層324係用以連 接該等電極至該頂層金屬層328。該金屬間介電層3 26係介 於該第一層金屬層324和該頂層金屬層328之間。201112419 I 1 6. Description of the Invention: [Technical Field] The present invention relates to a gold-oxygen semiconductor and a method of manufacturing the same, and more particularly to a trench-type power MOS transistor ) and its process methods. [Prior Art] Power Golden Oxygen Semi-Crystal System A special metal oxide semi-transistor designed to supply and switch power to an integrated circuit. Accordingly, the power MOS semi-electric crystal body needs to have the ability to work at high voltage. The general power MOS semi-transistor is fabricated in a complementary MOS process to achieve large size, allowing it to operate at high voltages. On the other hand, power MOS transistors need to provide a large output current. Therefore, in general, thousands to hundreds of thousands of transistor units are aggregated into one power MOS semi-transistor, wherein each transistor unit can output a small current, and the integrated power MOS semi-transistor is Can output a large current. However, the I-power MOS semi-transistor fabricated by this manufacturing method will occupy an excessive area and cannot be accepted by the industry. In order to reduce the area of power MOS transistors, a vertical diffused MOS (VDMOS) transistor has appeared in the industry. Figure 1 shows a schematic view of a VDMOS transistor. Unlike conventional flat CMOS transistors, current flows through a VDMOS transistor in a vertical direction. As shown in FIG. 1, the drain region of the VDMOS transistor 100 is located at the top of the VDMOS transistor 100, and the source region of the VDMOS transistor 100 is located at the bottom of the VDMOS transistor 100. The structure of Fig. 1 causes the VDMOS transistor 100 to have a high breakdown voltage and a high output current. 201112419 Figure 2 shows a schematic cross-sectional view of another trench-type MOS transistor, UM〇s. As shown in Fig. 2, the UMOS transistor 2 is named from its U-type gate oxide. The UMOS transistor 2A has a trench-type downwardly extending gate, and the UMOS transistor 200 also has a vertical current direction 'and the north pole transistor of the UMOS transistor 200 is located in the UMos transistor 200. The top portion of the UMOS transistor 200 is located at the bottom of the uM〇s transistor 200. However, the above-mentioned metal oxide semi-transistor having a vertical structure cannot be integrated with the integrated circuit which is generally fabricated in a CMOS process on the same wafer, thereby increasing the complexity of fabrication and the manufacturing cost. Accordingly, what is needed in the industry is a power MOS transistor, which has not only a high breakdown voltage, a high output current, and a high operation speed, but also has a horizontal structure, so that it can be integrated with a general CM 〇 s process. Integrated on the same wafer. SUMMARY OF THE INVENTION A trench power MOS transistor of an embodiment of the present invention includes a drain region, a double diffusion doping region, a trench gate region, a source region, and a well region. A deep well area and a base area. The drain region has a first conductivity type characteristic and is connected to a drain electrode. The double diffusion doped region has the first conductivity type characteristic and is located below the drain region. The trench gate region extends to the double diffused doped region and has a gate conductor and an insulating layer to isolate the gate conductor. The source region has the first conductivity type characteristic and is connected to a source electrode. The well region has a second conductivity type characteristic and is located below the source region. The deep well region has the first conductivity type characteristic and is located in the double diffusion doped region and below the well region. The substrate 201112419 is located below the deep well area. The insulating layer forms a thin sidewall region between the gate conductor and the well region, and forms a thick sidewall region in the gate conductor and the double diffusion doped region. The gate conductor and the deep well region form a thick bottom region' and the drain electrode and the source electrode are located on the upper surface of the trench power MOS transistor. The method for manufacturing a trench power MOS transistor according to an embodiment of the present invention includes the steps of: forming a deep well region having a first conductivity type characteristic on a base region; forming a first conductivity type One of the characteristics of the double-diffusion doping region of the drain region is on the deep well region; a trench region is engraved in the sidewall of the double-diffusion doped region; the insulating material is filled in the trench region; and the insulating material is opposite to the insulating material A gate region is etched on the outer side of the double diffusion doped region, so that the trench region has a thick sidewall region filled with the insulating material between the gate region and the double diffusion doped region, and the trench region is The gate region and the deep well region have a thick bottom region filled with the insulating material, and the gate conductor is filled in the gate region; forming a well region having a second conductivity type characteristic beside the gate region and the Forming a drain region having the first conductivity type characteristic on the double diffusion doped region; and forming a source region having the first conductivity type characteristic on the well region. [Embodiment] Fig. 3 is a schematic cross-sectional view showing a trench type power MOS semiconductor according to an embodiment of the present invention. As shown in FIG. 3, the trench power MOS transistor 300 includes a base region 302, a deep well region 304' - a double-diffusion source region double diffusion region 306, and a Well (Weu) zone 3〇8, an insulating layer 310, a gate conductor 312, a non-polar region 314, 201112419 ti 316, a body region 318, a metal telluride layer 32〇, a layer of dielectric (1扒A layer dielectric layer 322, a first metal layer 324, an inter metal dielectric layer 326, and a top metal layer 328. The trench type power MOS transistor 3 shown in Fig. 3 is an n-type transistor. However, those skilled in the art can readily convert this to a p-type transistor' and should still be covered by the present invention. As shown in Fig. 3, the non-polar region 314 has an N-type conductivity type characteristic and is connected to a drain electrode. The double diffusion Φ region 306 has the N-type conductivity type characteristic and is located below the drain region 314. Preferably, the double diffusion doped region 306 has a higher ion concentration in a region closer to the drain region 314 than in the region away from the drain region 314. The insulating layer 310 extends to the double diffusion doped region 3〇6 to isolate the gate conductor 3 12 . The insulating layer 310 and the gate conductor 312 form a trench-type open region ′ and the trench-type gate region surrounds the well region 3〇8 in a horizontal direction, and a closed-electrode system is connected to the opposite The gate conductor 312 outside the drain region 314. The source region 316 has the N-type conductivity type characteristic, surrounds the body region 318 and is connected to a source electrode. The well region 308 has a P-type conductivity type characteristic and is located below the source region 316. The deep well region 304 has the N-type conductivity type characteristic and is located below the double diffusion doped region 3〇6 and the well region 308. The base region 302 has a P-type conductivity type characteristic and is located below the deep well region 304. The metal telluride layer 320 is interposed between the drain region 314, the source region 3 16 and the body region 3 18 and the Between the electrodes. The interlayer dielectric 322 is located above the metallurgical layer 32〇. The first metal layer 324 is used to connect the electrodes to the top metal layer 328. The intermetal dielectric layer 3 26 is interposed between the first metal layer 324 and the top metal layer 328.
-6 - 201112419-6 - 201112419
• I 如圖3所示，該絕緣層310係於該閘極導體312和該井區 3〇8間形成-薄側壁區，於該閘極導體312和該雙擴散渗雜 區域306形成一厚側壁區，並於該閘極導體312和該深井區 304間形成_厚底區。該汲極電極、該源極電極和該間極電 極係位於該溝槽式功率金氧半電晶體3〇〇之上表面。 圖4顯不圖3之溝槽式功率金氧半電晶體3〇〇之局部放 大圖。如圖4所示，當該溝槽式功率金氧半電晶體3〇〇導通 • 時，係於該汲極區314沿著該絕緣層310之外壁至該源極區 316形成一通道◊如圖4所示’該通道具有一很短之有效長 度Leff，其相當於該井區之深度，故能降低該通道之電阻值 。又，由於形成通道之該雙擴散滲雜區域具有較高之離子 滲雜濃度，故其電阻值亦較小。因此，該溝槽式功率金氧 半電晶體300具有一較低之導通電組，故能提供較高之輸出 電流。 另一方面’該絕緣層310於該閘極導體312和該雙擴散 • 滲雜區域306間之厚侧壁區之厚度可提高該溝槽式功率金 氧半電晶體300之崩潰電壓。該絕緣層31〇於該閘極導體312 和該深井區304間之厚底區之厚度亦可提高該溝槽式功率 金氧半電晶體300之崩潰電壓。因此，該溝槽式功率金氧半 電晶體300可提供一較高之崩潰電壓。在實作上，可藉由調 整該厚側壁區及該厚底區之厚度以達到所欲得到之崩潰電 壓。 較佳的’若欲得到小於1〇〇伏特的崩潰電壓，可將該絕 緣層310之深度A設定於小於2微米，將該絕緣層31〇之寬度 201112419 B没定於小於2微米，將該閘極導體312之深度c設定於丨至2 微米’將該厚底區之厚度D設定於〇.〇2至1微米，以及將該 厚侧壁區之厚度E設定於〇·2至1微米。較佳的，若欲得到大 於100伏特的崩潰電壓，可將該絕緣層310之深度Α設定於大 於2微米’將該絕緣層31〇之寬度b設定於大於3微米，將該 閘極導體312之深度C設定於大於1.6微米，將該厚底區之厚 度D設定於大於0.6微米，以及將該厚側壁區之厚度E設定於 大於1微米。 復參圖4，由於該溝槽式功率金氧半電晶體3〇〇之通道 有效長度相當短，故自本體區318至閘極導體312之有效電 容Cgb相當小。又，由於該絕緣層3 1〇於厚側壁區之厚度相 當寬，故自汲極區314至閘極導體312之有效電容Cgd亦相當 小。因此，該溝槽式功率金氧半電晶體3〇〇具有一較高之操 作速度。 圖5顯示該溝槽式功率金氧半電晶體3〇〇之佈局結構示 意圖。如圖5所示，該絕緣層310係包圍住該汲極區314。該 源極區316係包圍住該本體區318。該閘極導體312係隔開該 >及極區3 14和該源極區3 16。 圖6至圖30顯示本發明之一實施例之溝槽式功率金氧 半電晶體之製造流程。圖6至圖3〇所示之製造流程為一 ；^型 電晶體之製造流程。然而，熟悉此項技術人士可輕易將其 轉換為P型電晶體之製造流程，而仍應為本發明所涵蓋。 如圖6所示’首先於該p型基底3〇2上滲雜n型離子以形 成該深井區3 04。如圖7所示，於該基底3 〇2上形成一雙擴散 201112419 滲雜之圖案化遮罩700。如圖8所示，於未遮罩處進行雙擴 散滲雜驅入（driving)以形成該雙擴散滲雜區域3〇6，其中 該滲雜驅入之溫度約為900至1000度(：：。如圖9所示，將該圖 案化遮罩700移除，於作用區形成氧化矽墊層（pad 〇xide )/氮化矽墊層（pad nitride) 900，並於該氧化矽墊層/氮化 矽墊層900上形成硬光罩910,其中該硬光罩91〇可為滲硼玻 璃（BSG)。如圖1〇所示，於該雙擴散滲雜區域3〇6之側壁 蝕刻出溝渠區。如圖11所示，將該硬光罩910移除。如圖12 所示’沉積該絕緣層310於該溝渠區内，並以化學機械研磨 (chemical mechanical polishing，CMP)技術研磨該絕緣 層310’其中該絕緣材料可為氧化物。如圖13所示，於該雙 擴散滲雜區域306上方形成一閘極導體之圖案化遮罩13〇〇 。如圖14所示，於該絕緣層310處進行蝕刻以形成閘極區， 其中該钱刻係使該閘極區和該雙擴散滲雜區域3 〇 6間具有 填滿該絕緣層3 1 0之厚側壁區’及使該閘極區和該深井區 3 04間具有一填滿該絕緣層3 1 〇之厚底區。較佳的，該银刻 深度約為1至2微米。 如圖15所示，將該圖案化遮罩13〇〇移除，成長或沉積 閘極氧化或纟巴緣層於該溝渠區之側壁，並沉積該閘極導體 312於該閘極區，其中該閘極導體312可為多晶石夕（ poly-silicon)或金屬。如圖16所示，接著進行該閘極導體 312之蝕刻。如圖17所示，於該閘極導體312之蝕刻處沉積 該絕緣層310，並以化學機械研磨該絕緣層3 1 〇，其中該絕 緣材料可為氧化物。如圖18所示，移除該氧化矽墊層/氣化 201112419• As shown in FIG. 3, the insulating layer 310 forms a thin sidewall region between the gate conductor 312 and the well region 3〇8, and forms a thick layer between the gate conductor 312 and the double diffusion doped region 306. The sidewall region forms a thick-bottom region between the gate conductor 312 and the deep well region 304. The drain electrode, the source electrode, and the interpole electrode are located on a surface of the trench power MOS transistor 3A. Fig. 4 shows a partial enlarged view of the trench type power MOS transistor 3 of Fig. 3. As shown in FIG. 4, when the trench power MOS transistor 3 is turned on, a channel is formed in the drain region 314 along the outer wall of the insulating layer 310 to the source region 316. As shown in Fig. 4, the channel has a very short effective length Leff which is equivalent to the depth of the well region, so that the resistance value of the channel can be lowered. Moreover, since the double diffusion doped region forming the channel has a high ion doping concentration, the resistance value thereof is also small. Therefore, the trench power MOS transistor 300 has a lower conduction group, thereby providing a higher output current. On the other hand, the thickness of the thick sidewall region between the gate conductor 312 and the double diffused doped region 306 of the insulating layer 310 increases the breakdown voltage of the trench power MOS transistor 300. The thickness of the insulating layer 31 between the gate conductor 312 and the thick-bottom region between the deep well regions 304 can also increase the breakdown voltage of the trench power MOS transistor 300. Therefore, the trench power MOS transistor 300 can provide a higher breakdown voltage. In practice, the thickness of the thick sidewall region and the thickened region can be adjusted to achieve the desired collapse voltage. Preferably, if a breakdown voltage of less than 1 volt is desired, the depth A of the insulating layer 310 can be set to less than 2 micrometers, and the width of the insulating layer 31 2011 201112419 B is not less than 2 micrometers. The depth c of the gate conductor 312 is set to 丨 to 2 μm 'the thickness D of the thick bottom region is set to 〇. 2 to 1 μm, and the thickness E of the thick sidewall region is set to 〇·2 to 1 μm. Preferably, if a breakdown voltage greater than 100 volts is to be obtained, the depth Α of the insulating layer 310 can be set to be greater than 2 micrometers. The width b of the insulating layer 31 is set to be greater than 3 micrometers, and the gate conductor 312 is disposed. The depth C is set to be greater than 1.6 microns, the thickness D of the thick bottom region is set to be greater than 0.6 microns, and the thickness E of the thick sidewall region is set to greater than 1 micron. Referring to Fig. 4, since the effective length of the channel of the trench type power MOS transistor 3 is relatively short, the effective capacitance Cgb from the body region 318 to the gate conductor 312 is relatively small. Further, since the thickness of the insulating layer 31 is thicker in the thick sidewall region, the effective capacitance Cgd from the drain region 314 to the gate conductor 312 is also relatively small. Therefore, the trench type power MOS transistor 3 has a higher operating speed. Fig. 5 is a view showing the layout of the trench type power MOS transistor. As shown in FIG. 5, the insulating layer 310 surrounds the drain region 314. The source region 316 surrounds the body region 318. The gate conductor 312 is spaced apart from the > and the polar region 3 14 and the source region 3 16 . 6 to 30 show a manufacturing process of a trench type power MOS transistor according to an embodiment of the present invention. The manufacturing process shown in Fig. 6 to Fig. 3 is a manufacturing process of a transistor. However, those skilled in the art can readily convert this to a P-type transistor fabrication process and still should be covered by the present invention. As shown in Fig. 6, 'n-type ions are first doped on the p-type substrate 3〇2 to form the deep well region 3 04. As shown in FIG. 7, a double diffused 201112419 doped patterned mask 700 is formed on the substrate 3 〇2. As shown in FIG. 8, double diffusion doping is performed at the unmasked portion to form the double diffusion doped region 3〇6, wherein the temperature of the diffusion drive is about 900 to 1000 degrees (:: As shown in FIG. 9, the patterned mask 700 is removed, and a pad 〇xide/pad nitride 900 is formed in the active region, and the yttrium oxide pad layer/ A hard mask 910 is formed on the tantalum nitride layer 900, wherein the hard mask 91 can be a boronized glass (BSG). As shown in FIG. 1A, the sidewall of the double diffusion doped region 3〇6 is etched. Ditch region. As shown in FIG. 11, the hard mask 910 is removed. As shown in FIG. 12, the insulating layer 310 is deposited in the trench region and ground by chemical mechanical polishing (CMP) technology. The insulating layer 310' may be an oxide. As shown in FIG. 13, a patterned mask 13a of a gate conductor is formed over the double diffusion doped region 306. As shown in FIG. Etching at the insulating layer 310 to form a gate region, wherein the money engraving has between the gate region and the double diffusion doped region 3 〇 6 a thick sidewall region of the insulating layer 310 and a thick-bottom region between the gate region and the deep well region 304 filled with the insulating layer 3 1 。. Preferably, the silver engraving depth is about 1 Up to 2 microns. As shown in Figure 15, the patterned mask 13 is removed, a gate oxide or germanium edge layer is grown or deposited on the sidewall of the trench region, and the gate conductor 312 is deposited on the gate. a pole region, wherein the gate conductor 312 can be poly-silicon or metal. As shown in FIG. 16, etching of the gate conductor 312 is performed. As shown in FIG. 17, the gate conductor is The insulating layer 310 is deposited at an etch of 312, and the insulating layer 3 1 〇 is chemically mechanically polished, wherein the insulating material may be an oxide. As shown in FIG. 18, the yttrium oxide underlayer is removed/gasification 201112419
• J 石夕墊層900。如圖19所示’進行P型離子滲雜以形成該井區 308。如圖20所示，於源極及汲極處形成—源極/汲極之圖 案化遮罩2000，並進行N型離子滲雜以形成該汲極區314和 該源極區316。如圖21所示’移除該圖案化遮罩2〇〇〇,形成 一本體之圖案化遮罩2100，並進行離子滲雜以形成該本體 區318。如圖22所示，移除該圖案化遮罩21〇〇，進行接面回 火以形成該金屬矽化物層320，其中該回火溫度可為8〇〇至 φ 1000度C’而該金屬矽化物可為鈦或鈷之金屬矽化物。如圖 23所示，於該金屬矽化物層32〇上形成該層間介電層322， 並於該層間介電層322形成一接點（contact )之圖案化遮罩 2300 ’其中該層間介電層322之材料可為硼磷玻璃。 如圖24所示’進行接點蝕刻。如圖25所示，移除該圖 案化遮罩2300，並於接點蝕刻處沉積金屬鎢以形成源極、 及極和閘極之接點，並以化學機械研磨技術研磨該等接點 。如圖26所示，於該層間介電層322上沉積該第一層金屬層 Φ 324 ’並於該等接點處形成第一層金屬層之圖案化遮罩％⑽ 。如圖27所示，進行該第一層金屬層3 24之蝕刻，並移除該 圖案化遮罩2600。如圖28所示，於該第一層金屬層324及該 層間介電層322上沉積該金屬間介電層326，其中該金屬間 介電層326之材料可為硼，玻璃。如圖29所示，於該金屬間 介電層326上形成通孔（via)之圖案化遮罩。之後，進行 接點钱刻，移除該圖案化遮罩，並沉積金屬鎢以於該等接 點上形成通孔。如圖30所示，形成該頂層金屬層328於該金 屬間介電層326上，於該頂層金屬層328上形成圖案化遮罩 201112419 ，進行該頂層金屬層328之蝕刻，並移除該圖案化遮罩。 综上所述，本發明之溝槽式金氧半電晶體以其特殊之 溝槽式結構而具有高崩潰電壓、高輸出電流及高操作速度 之特點。又’因本發明之溝槽式金氧半電晶體具有水平結 構，故能和一般以CMOS製程製作之積體電路整合於同一片 晶片上，而可增加實用性及減少製作成本。• J Stone Mat 900. P-type ion doping is performed as shown in FIG. 19 to form the well region 308. As shown in Fig. 20, a source/drain patterned mask 2000 is formed at the source and drain electrodes, and N-type ion doping is performed to form the drain region 314 and the source region 316. The patterned mask 2 is removed as shown in Figure 21 to form a patterned mask 2100 of the body and ion permeable to form the body region 318. As shown in FIG. 22, the patterned mask 21 is removed, and junction tempering is performed to form the metal telluride layer 320, wherein the tempering temperature may be 8 〇〇 to φ 1000 ° C' and the metal The telluride can be a metal halide of titanium or cobalt. As shown in FIG. 23, the interlayer dielectric layer 322 is formed on the metal halide layer 32, and a contact mask 2300' is formed in the interlayer dielectric layer 322. The material of layer 322 can be borophosphosilicate glass. As shown in Fig. 24, contact etching is performed. As shown in Figure 25, the patterned mask 2300 is removed and metal tungsten is deposited at the contact etch to form the source, and the junction of the pole and the gate, and the contacts are ground by chemical mechanical polishing techniques. As shown in FIG. 26, the first metal layer Φ 324 ′ is deposited on the interlayer dielectric layer 322 and the patterned mask % (10) of the first metal layer is formed at the contacts. As shown in Figure 27, the first layer of metal layer 324 is etched and the patterned mask 2600 is removed. As shown in FIG. 28, the inter-metal dielectric layer 326 is deposited on the first metal layer 324 and the interlayer dielectric layer 322. The material of the inter-metal dielectric layer 326 may be boron or glass. As shown in Fig. 29, a patterned mask of vias is formed on the inter-metal dielectric layer 326. Thereafter, the contact is engraved, the patterned mask is removed, and metal tungsten is deposited to form via holes in the contacts. As shown in FIG. 30, the top metal layer 328 is formed on the inter-metal dielectric layer 326, a patterned mask 201112419 is formed on the top metal layer 328, the top metal layer 328 is etched, and the pattern is removed. Mask. In summary, the trench type MOS transistor of the present invention has a high breakdown voltage, a high output current, and a high operation speed due to its special trench structure. Further, since the trench type MOS transistor of the present invention has a horizontal structure, it can be integrated with the integrated circuit which is generally fabricated in a CMOS process on the same wafer, which can increase the usability and reduce the manufacturing cost.
本發明之技術内容及技術特點已揭示如上，然而熟杰 本項技術之人士仍可能基於本發明之教示及揭示而作種種 不背離本發明精神之替換及修飾。因此，本發明之保護範 圍應不限於實施例所揭示者，而應包括各種不背離本發明 之替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡要說明】 圖1顯示一 VDMOS電晶體之剖面示意圖； 圖2顯示一 UMOS電晶體之剖面示意圖； 圖3顯示本發明之一實施例之溝槽式功率金氧半電曰 體之剖面示意圖； 圖4顯示本發明之一實施例之溝槽式功率金氧半電曰 體之局部放大圖； 圖5顯示本發明之一實施例之溝槽式功率金氧半電曰 體之佈局結構示意圖；以及 Βθ 圖6至圖30顯示本發明之一實施例之溝槽式功率金 半電晶體之製造流程。 【主要元件符號說明】 100 VDMOS電晶體 -11- 201112419 200 UMOS電晶體 300 溝槽式功率金氧半電晶體 302 基底區 3 04 深井區 306 雙擴散滲雜區域 308 井區 310 絕緣層 312 閘極導體The technical contents and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention is not limited by the scope of the invention, and the invention is intended to cover various alternatives and modifications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a VDMOS transistor; FIG. 2 is a cross-sectional view showing a UMOS transistor; and FIG. 3 is a cross-sectional view showing a trench type power oxy-semiconductor body according to an embodiment of the present invention. FIG. 4 is a partial enlarged view of a trench type power oxy-electric semiconductor body according to an embodiment of the present invention; FIG. 5 is a view showing a layout structure of a trench type power oxy-electric semiconductor body according to an embodiment of the present invention; Schematic; and Βθ FIGS. 6 to 30 show a manufacturing flow of a trench type power gold semiconductor according to an embodiment of the present invention. [Main component symbol description] 100 VDMOS transistor-11- 201112419 200 UMOS transistor 300 trench power MOS semi-transistor 302 Base region 3 04 Deep well region 306 Double diffusion doped region 308 Well region 310 Insulation layer 312 Gate conductor
314 波極區 316 源極區 318 本體區 320 金屬矽化物層 322 層間介電層 324 第一層金屬層 326 金屬間介電層 328 頂層金屬層 700 圖案化遮罩 900 氧化矽墊層/氮化矽墊層 910 硬光罩 1300 圖案化遮罩 2100 圖案化遮罩 2300 圖案化遮罩 2600 圖案化遮罩 -12-314 Polar Region 316 Source Region 318 Body Region 320 Metal Telluride Layer 322 Interlayer Dielectric Layer 324 First Metal Layer 326 Intermetal Dielectric Layer 328 Top Metal Layer 700 Patterned Mask 900 Cerium Oxide Layer/Nitride Cushion 910 Hard Shield 1300 Patterned Mask 2100 Patterned Mask 2300 Patterned Mask 2600 Patterned Mask -12-