TW550820B - Active matrix substrate and method of manufacturing the same and active matrix liquid crystal display - Google Patents

Abstract

A method of manufacturing an active matrix substrate (1) comprising a row and column array of active elements (10) wherein each element (11) is associated with a TFT (13) having a gate electrode (306) connected to a corresponding row conductor (15) and source (320) and drain (321) electrodes connected to corresponding column conductors (14), and ESD protective circuitry (20) connected to at least one of the row conductors for protecting the TFTs against electrostatic discharge (ESD). The method comprising the steps of forming semiconductor regions of the TFTs (302) and the ESD protective circuitry (303); depositing gate electrodes (306) of the TFTs and corresponding row conductors (15); and depositing source (320) and drain (321) electrodes of the TFTs and corresponding column conductors (14), wherein the ESD protective circuitry (20) is operative to control ESD prior to deposition of the column conductors (14).

Description

550820 A7 B7 V. Description of the Invention and Summary of the Invention The present invention relates to a method for manufacturing an active matrix substrate. The substrate includes a horizontal and vertical array composed of a number of active elements, each of which is separately It is associated with a thin film transistor (TFT) with a switching function, and also includes an ESD protection circuit connected to each of the TFTs to protect the TFTs from damage caused by electrostatic discharge (ESD). The a is clear, but the intention of being exclusive is related to the method of manufacturing an active matrix substrate by complementary metal-oxide-semiconductor (CMOS) technology, such as manufacturing a TFT with a number of TFTs made by CMOS technology and lacking switching functions. Or it is related to the manufacturing method of the active matrix liquid crystal display (AMLCD) of the integrated horizontal tandem pusher circuit manufactured by CMOS technology. The following describes the method disclosed in the present invention by making AMLCD as an example, but the reader should understand that the present invention is not only applicable to the manufacture of AM LCD, but also applicable to various other large-area electronic devices, such as thin-film data storage devices or images. Manufacturing of sensors and other devices. As is well known, electrostatic potentials have a destructive effect on the thin film devices containing thin dielectric layers, especially the gate regions of the MOS TFTs which are easily damaged. In the case of AM LCD (active matrix liquid crystal display), the gate of each TFT is connected to the corresponding horizontal conductor, and the source and terminal of each TFT are connected to the corresponding vertical conductor. If you want to prevent the damaging force of electrostatic discharge, you can install a protection circuit to adjust the current flowing between the horizontal and vertical conductors during electrostatic discharge. For example, to achieve this purpose, each of the horizontal and vertical conductors may be connected to a ground ring via a pair of two diode parallel circuits arranged opposite each other and having partial resistance. This kind of circuit equipment _____- 4-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 550820 A7 ___B7 ___ 5. Description of the invention (2) The patent application was published by PCT wo 97 / 13 177 and US patents 5,585,949 and US 5,930,607. It is an object of the present invention to provide a method for manufacturing an active matrix substrate with improved ESD protection circuit performance as described above. According to the design of the present invention, a method for manufacturing an active matrix substrate is provided. The substrate includes an array composed of a plurality of horizontal and vertical active elements, each of which has a thin film transistor (TFT). The gates of each TFT are connected to a corresponding horizontal conductor, and the source and the non-polar are connected to the corresponding column conductors, respectively. An ESd protection circuit is connected to at least one horizontal conductor to protect each Tft from damage caused by electrostatic discharge (ESD) current. The method includes the steps of forming each tft semiconductor region and the ESD protection circuit; the steps of depositing and forming each TFT gate and the corresponding row of conductors; and the source and drain of each TFT and the hall of the corresponding column conductor Processes such as product formation steps, in which the ESD protection circuit should be in an operating state to control the ESD current before each column conductor is deposited and formed. Although the traditional ESD protection circuit can undoubtedly also provide various AMLCDs with protection from ESD damage during operation, the inventors of the present invention believe that if the ESD circuit can be operated early in the manufacturing process ( For example, it may be more desirable before the column conductors are formed by a deposition process. The ESD protection circuit can be brought into operation before starting to form the individual columns of conductors by deposition, especially after forming the rows of conductors by deposition. In order to achieve this purpose, 'can be used in a semiconductor area of the ESD protection circuit — · 5-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 public love) " "--550820 A7 ____B7 I 、 Description of the invention (3) '' Doping some impurities to provide a controlled conductive path, connected by the semiconductor region to a row of conductors, through the semiconductor region to the environment outside the substrate, and preventing current from flowing in the opposite direction Flow through the semiconductor region. Another way is to consume the negative charge built up on the substrate. Impurities can be added to a semiconductor region of the ESD protection circuit to provide a controlled conductive path from the environment outside the substrate through the semiconductor region. To the portion of the semiconductor region connected to a horizontal row of conductors and prevent current from flowing through the semiconductor region in the opposite direction. After the manufacture of the active matrix substrate is completed, the ESD protection circuit can be operated to control the esd in a method different from the method in which the ESD protection circuit controls the ESD before the deposition process to form the column conductors. For example, the ESD protection circuit can be operated to control the ESD current between the substrate and its external environment before the deposition process to form each column conductor, and can be operated to control the horizontal row after the active matrix substrate manufacturing process is completed. And ESD effects between tandem conductors. The ESD protection circuit may include a lateral diode in a general manner, or a TFT that is short-circuited to the gate between the horizontal and vertical conductors, and preferably has at least a pair of the aforementioned diodes or TFTs connected in parallel. The rear part is connected between the horizontal and vertical conductors. In particular, the active area may include two parts located on both sides of the active area in the diode or TFT. The first part is connected to the horizontal part. Conductors, and the area of a second part (on the other side of the active area) is at least twice or even more than ten times the area of the first part. The present invention also provides an active or matrix substrate manufactured in accordance with the principles of the present invention. The paper is designed according to any one of the 13th to 15th patent scope of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 550 820 A7 B7

An active matrix substrate is manufactured, and an active matrix liquid crystal display (AMLCD) including one of the active matrix substrates. The following is an example to illustrate the principle of the present invention with reference to the following drawings: FIG. 1 is a schematic circuit diagram of an AMLCD active matrix substrate manufactured according to the principle of the present invention and containing an ESD protection circuit. FIG. 2 is a detailed detailed current diagram of the eSD circuit included in the active matrix substrate shown in FIG. 1. 3A to 3E are schematic diagrams illustrating a manufacturing method of an active matrix substrate. 4A to 4C show another structural form of the esd circuit on the active matrix substrate. The reader should understand that the above drawings are schematic diagrams, and the cross-sectional diagrams and circuit layouts are shown for ease of explanation. Their sizes and shapes may be exaggerated or reduced. In different specific examples, the same or similar specific parts are marked with the same reference code. FIG. 1 shows an AMLCD 1 manufactured according to the method disclosed in the present invention, and includes a display area 10 on a display surface 18, the display area including ^ horizontal rows (丨 to ^) and η vertical columns. (1 to η) the same image element 11. To simplify the explanation, only a few of these image elements are shown in this figure, but in actual application, the total number of images (mXn) in the display area 10 may be as high as 200,000 or more. Each image element 11 has an image electrode 12 and a TFT 13 associated with the switching function and made according to the method disclosed in the present invention (as shown in FIGS. 3A to 3D). The TFT is used to control the application to the image. Data signal voltage of the electrode. These TFTs 13 with switching functions have common characteristics, and each TFT 13 is installed adjacent to its respective relevant image element. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

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550820 A7 _—__ B7 __ V. Description of the invention (5)

< upright 'with its drain connected to the picture element. The source of each of the TFTs 13 having a switching function associated with each column image element is respectively connected to a corresponding column conductor 14 of the group of parallel column conductors, and these are associated with each column The gates of the TFTs 13 related to the image elements are respectively connected to a corresponding one of the parallel horizontal conductors 15 in the group of parallel horizontal conductors 15. The operation of these TFTs is controlled by the gate control signal provided by the horizontal driving circuit 16 provided on the display surface 18 with CMOS as the substrate. Similarly, for each TFT related to the same column of image elements, the electrical waste of the data signals required for the image electrodes is performed by a column driving circuit 26 provided on the same display surface 18 with CMOS as the substrate. provide. Because the operating principles of the image elements in these amLCDs are well-known knowledge, I will not repeat them. On the AMLCD display surface 18, integrated ESD is provided at both ends of each of the horizontal conductors 15 and the vertical conductors 14. The protection circuit 20 is connected to each of the horizontal and vertical conductors via a common power trunk 19. FIG. 2 is a detailed diagram of the protection circuit 20. There are two pin-joined diodes 21 and 21 'connected in parallel in opposite directions in the figure. With this circuit design, the voltage across the horizontal and vertical columns can be controlled. The method is only allowed A current with a preset current value flows in the conducting direction of each diode. 3A to 3E illustrate a method for manufacturing the active matrix substrate shown in FIG. 1, including CMOS p-type (in region R1) and n-type (in region R1) required for each image element or each integrated horizontal and vertical driving circuit. A method for forming a transistor in the region R2 and a method for forming a pin diode (in the region R3) required for the above-mentioned ESD protection circuit. Referring to FIG. 3A, a multi-layered layer is formed on a glass substrate 301, and a paper size of -8-^ applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " a 550820

It is planned to form the shape of a semiconductor island region 302 302 for forming p-type and n-type transistors, and to form an extended polylithic region, including an active region of a ρ-ι-η diode, and Extends to the periphery of the display screen, and forms an electrical connection with the ground point outside the substrate. This electrical connection may be an electrical connection that is not specifically designed to connect to the external environment, such as using an electrical connection in the manufacturing process. A clip (not shown in the figure) used to stabilize the glass substrate, or a contact pad (not shown in the figure) formed in the extended polysilicon region 303 to be connected to the external electrical ground connector. Methods and materials, such as the steps of shielding treatment 306, 311 and doping of impurities, as shown in Figs. 3B and 3, c, to form each P-type doped region of P-1-P transistor R1 307, each n-type doped impurity region 313 of the ni-n transistor R2 includes each LDD region 314, and p-type and n-type doped impurity regions 309,312 of the pin diode R3. Then, as shown in FIG. As shown in 3D, a gate 315 is provided for each transistor ri, R2, and is connected to The thickness of the horizontal rows of conductors is doped with a layer of silicon or impurities, or the metal areas are integrated with the horizontal rows of conductors. Each horizontal row of conductors 15 is also processed by shoulder and product to form the gate electrodes and the above. The ρ-type region 309 in the P · ^ η diode R3 is connected. After the gate electrode 315 and the horizontal conductors 15 are formed by the deposition process, the charges accumulated at the gates of the TFTs can pass through the ρ__η diode The body / Xiao is scattered to the ground terminal 'as shown by arrow 317 in the figure. In the same way, the polarity of the junction of the diodes can protect each TFT from ESD current from external ring damage (for example, caused by processing the substrate). Thereafter, as shown in FIG. 3E, the source electrodes 3220 and the drain electrodes 321 of the transistors Ri and r2, the column conductors 322, and the horizontal and column conductors are connected to each other. Standard (CNS) A4 (210X 297 mm)

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550820 A7 B7 5. A grounding ring (not shown) in the description of the invention (7). After completing the formation steps of each tandem conductor, the ESD protection circuit can control the amount of current flowing between the tandem and tandem conductors, so that the charge on each TFT gate can be passed through the pin diode through the arrows in the figure The direction shown at 318 dissipates to the ground. The pin diode R3 is one of a pair of diodes of opposite polarity and partially resistive and connected in parallel with each other, and uses a current that allows only a predetermined amount of current to flow in the direction of the conductive polarity of the diode. Designed to limit the voltage across these horizontal and vertical conductors. 4A to 4C are schematic diagrams of other configurations of the ESD protection circuit. To be clear, the TFT structure of the n-i-n gate short circuit of FIG. 4A can also be operated in the same manner as the p-i-n diode R3 shown in FIGS. 3A to 3E. That is, the nin gate short-circuited TFT structure allows the charge to dissipate through the extended silicon region earlier in the manufacturing process, and controls the flow between the horizontal and vertical conductors after the formation of each column conductor deposition process is completed. Of charge. In the same way, the negative charge can be dissipated through a nip diode structure or a tft structure with a pip gate short circuit (as shown in FIGS. 4B and 4C) (actually, a current flows from the external environment to the substrate. The ESD The dual function of the protection circuit, that is, controlling the charge flow between the substrate and the external environment at the beginning of the manufacturing process, and controlling the horizontal and vertical conductors after the manufacturing steps of the deposition process to form the vertical conductors are completed The inter-charge flow may limit the geometric parameters of the E sd protection circuit to some extent. For example, in a pin structure shown in FIG. 3E, the n-type portion of the diode structure extending to the periphery of the substrate 312, its size and volume may be twice, five times larger than the volume of the p-shaped part in the diode structure, and even __-10-This paper size applies the Chinese National Standard (CMS) Α4 specification (210 X 297 mm) Love) ~ ----- 550820 A7

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Claims (1)

550820 "Zhengzheng / Geng iL / m% Patent Application No. 090127413 g Chinese Patent Application Scope Replacement (February 1992) C8 VI. Application Patent Scope 1. A method for manufacturing an active matrix substrate, the The substrate includes an array of horizontal and vertical active elements, each of which is associated with a thin film transistor (TFT), and the gate of each TFT is connected to a corresponding horizontal conductor, and The source and drain are connected to a corresponding column conductor; the substrate also includes an esd protection circuit connected to at least one horizontal conductor to protect the τ FT from electrostatic discharge (ESD). Damage, the method includes the following steps: forming each of the TFTs and each semiconductor region of the ESD protection circuit; forming the gates of the TFTs and the corresponding horizontal conductors by a transfer method; and The source and drain of the TF T and the corresponding tandem conductors are formed, and the ESD protection circuit can be operated to control the current of the ESD before the tandem conductor is formed by the Dianji process. 2. According to the method of claim 1 in the scope of patent application, the ESD protection circuit can start to control the discharge current of ESD between the substrate and its external environment before forming each of the column conductors by a deposition process. In the method of applying for the second item of the patent scope, before forming the tandem conductors by a deposition process, the ESD protection circuit can start operation to control the substrate and its external environment when the platoon conductors are formed by the deposition process. ESD current generated during the period of time 4. If the method of the scope of patent application No. 2 is applied, before forming the column conductors by a deposition process, that is, in a semiconductor region of the ESD protection circuit C8 D8 6. Doping with impurities within the scope of the patent application can provide a lightly conductive path from the semiconductor region to a row of conductors, pass through the semiconductor region to the clothing environment of the substrate, and block the current Flow through the semiconductor region in the opposite direction. 5. If the method in the second item of the patent application is applied, before depositing and forming the column conductors <, doping some impurities in a semiconductor region of the ESD protection circuit first, a lightly conductive material can be provided. The nature path passes from the environment outside the substrate through the semiconductor region to a portion of the semiconductor region connected to a horizontal row of conductors, and can prevent current from flowing through the semiconductor region in the opposite direction. 6. The method of claim 1, wherein the ESD protection circuit includes at least one lateral diode or a lateral short-circuited TFT connected between each row and column conductor. 7. The method according to item 6 of the patent application scope, wherein the ESD protection circuit includes at least a pair of TFTs with short-circuited laterally paralleled diodes or horizontally paralleled gates, which are short-circuited and connected to the horizontal and vertical conductors. between. 8. The method according to item 6 of the scope of patent application, wherein at least one semiconductor region of a TFT that is short-circuited by lateral diodes or lateral gates connected between each row and column conductor includes two parts respectively located in the foregoing On either side of the diode or TFT active region, a first portion of the diode or TFT is connected to the horizontal conductor, and the second portion on the other side of the active region has a volume at least twice that of the first portion . 9 · If the method of applying for the scope of the patent No.8, in which the volume of the second part, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Decoration 550820 A B c D 6. The scope of patent application is at least ten times larger than the volume of the first part. After applying the method of item 1, 2, 3, 4, 5, 6, 7, 8, or 9 of the scope of patent application, after completing the manufacturing process of the active matrix substrate, the way in which the ESD protection circuit controls the ESD discharge and the circuit The manner in which ESD discharge is controlled before each column conductor is deposited is different. U · As in the method of claim 10, the operation mode of the ESD protection circuit before the formation of each column conductor is to control the ESD effect between the substrate and its external environment; and on the active matrix substrate After the manufacturing is completed, the operation mode is to control the ESD effect between each horizontal conductor and each vertical conductor. 12. An active matrix substrate, including a row and a row array of active elements, each of which is associated with a thin film transistor (TFT), and the gate of each TFT is connected to a corresponding horizontal conductor The source and drain are respectively connected to their respective tandem conductors, and a £ 31) protection circuit is connected to at least one horizontal conductor to protect the TFTs from electrostatic discharge (ESD) Damage, the ESD protection circuit includes at least one lateral diode or lateral gate short circuit TJ7τ connected between the horizontal and vertical conductors; and at least one lateral diode or lateral gate short circuit TFT of the ESD protection circuit The semiconductor region contains two portions on either side of the diode or tft active region, of which the first portion is connected to the horizontal conductor and the volume of the second portion on the other side of the active region At least twice the volume of the first part. This paper size applies to China National Standard (CNS) A4 specifications (2l0x297). 550820 A8 B8 C8 D8 13. For example, the active matrix substrate of item 12 of the patent scope, wherein the volume of the second part is at least ten times larger than that of the first part. 14. The active matrix substrate according to item 12 of the patent application scope, wherein the ESD protection circuit includes at least a pair of lateral diodes or lateral diodes with opposite polarities connected in parallel and connected between each row and column conductor. Shorted TFT. 15. For example, the active matrix substrate of item 13 of the patent application scope, wherein the ESD protection circuit includes at least a pair of lateral diodes or horizontal poles with opposite polarities connected in parallel and connected between each row and column conductor. • Short-circuit the TFT to the gate. 16. —A type of active matrix liquid crystal display (AMLCD), including an active matrix substrate according to the scope of patent application No. 1 2, 1 3, 1 4 or 15 0 This paper size applies to Chinese National Standards (CNS) Α4 size (210 X 297 mm)