550742 五、發明說明⑴ 本發明係有關於一種動態隨機存取記憶體（Dynam i e Random Access Memory ; DRAM)之半導體製程，特別是有 關於一種形成瓶型溝槽（bottle-shaped trench)的方 法。 一般而言，目前廣泛使用之動態隨機存取記憶體 (Dynamic Random Access Memory； DRAM )中的電容器係 由兩導電層表面（即電極板）隔著一絕緣物質而構成，兮' 電容器儲存電荷之能力係由絕緣物質之厚度、電極板之^ 面積及絕緣物質的電氣性質所決定。隨著近年來半導體製 程設計皆朝著縮小半導體元件尺寸以提高密度之方向發衣 展，記憶體中記憶胞的基底面積必須不斷減少使積體電路 能容納大量記憶胞而提高密度，但同時，記憶胞電容之電 極板部分必須有足夠之表面積以儲存充足的電荷。 然而在尺寸持續地細微化的情況下，動態隨機存取記 憶體中的溝槽儲存結點電容（trench storage node capacitance)亦隨著縮小，因此必須設法增加儲存電容以 維持記憶體良好的操作性能。 目前已廣泛使用於增加DRAM之儲存電容的方法可舉例 如增加溝槽底部的寬度，因而提高表面積形成一瓶型電容 (bottle-shaped Capacitor)。上述方法係於一溝槽上半 邛以選擇性氧化（selective 〇xidati〇n)形成一環狀氧化 層保護溝槽之上半部後，對該溝槽之下半部進行濕蝕刻以 形成直徑大於上半部的瓶型溝槽。 詳而s之’傳統製程係在具有氧化層以及氮化層所構 550742 五、發明說明（2) 成之疊層的半導體基底上，以等向性乾蝕刻（is〇tr〇pic dry etching)形成一溝槽後，接著再依序順著該疊層以及 該溝槽形成氮化層、氧化層、複晶矽層以及氧化層；然而 上述製程繁雜，需要多次沈積步驟，不論是在製造成本或 時間上均不符經濟效益，因此需要一種製程簡化且高產能 的形成瓶形溝槽的方法。 有鑑於此，本發明之主要目的為提供一種製造步驟簡 化，且符合經濟效益之形成瓶形溝槽的方法。 為了達成上述目的，本發明主要係利用兩次氧化層之 沈積，再形成深溝槽中側壁上半部的側壁保護層後 濕蝕刻方式擴大深溝槽下半部的寬度而形成瓶型溝槽。 層發瓶型溝槽的方法，適用於表面形成-塾 層結構;且在既定位置上具有一溝槽的半導體基板，复 驟包括.a)沿著該墊層結構以及該溝槽之 ^ , 介電層；b)於該溝槽之下半 第一 該墊層結構上以及位於辟=層，C)移除位於 久仪〜β溝槽之側壁上半部的第一 d)移除該犧牲層’而保留位於該溝槽下半部侧壁 第-介電層’ e)沿著該墊層結構、該溝槽之；順 應性形成一第二介電層而將該第一介 = = 形成一保護層;g)回餘刻該保么= h)移除位於該溝槽底部之第二介電層而形成一開口H番 槽底部，！）以該側壁保護層為罩幕移除位 之第-介電層“及第二介電層而露出該溝槽；㈡：二部550742 V. Description of the Invention ⑴ The present invention relates to a semiconductor process for a dynamic random access memory (DRAM), and more particularly to a method for forming a bottle-shaped trench. Generally speaking, the capacitors in currently widely used dynamic random access memory (DRAM) are composed of two conductive layer surfaces (ie, electrode plates) with an insulating material interposed therebetween. The capacity is determined by the thickness of the insulating material, the area of the electrode plate, and the electrical properties of the insulating material. With the recent progress of semiconductor process design in the direction of reducing the size of semiconductor elements to increase the density, the base area of memory cells in memory must continue to decrease so that integrated circuits can accommodate a large number of memory cells to increase density, but at the same time, The electrode plate portion of the memory cell capacitor must have sufficient surface area to store sufficient charge. However, in the case of continuous miniaturization, the trench storage node capacitance in the dynamic random access memory also decreases, so it is necessary to find ways to increase the storage capacitance to maintain the good operating performance of the memory. . Methods that have been widely used to increase the storage capacitance of DRAMs include, for example, increasing the width of the bottom of the trench, thereby increasing the surface area to form a bottle-shaped capacitor. The above method is to selectively oxidize the upper half of a trench to form a ring-shaped oxide layer to protect the upper half of the trench, and then wet-etch the lower half of the trench to form a diameter. Larger bottle-shaped groove than the upper half. In detail, the traditional process is based on a layered semiconductor substrate with an oxide layer and a nitride layer. 550742 5. Description of the invention (2) A stacked semiconductor substrate with isotropic dry etching. After a trench is formed, a nitride layer, an oxide layer, a polycrystalline silicon layer, and an oxide layer are sequentially formed along the stack and the trench; however, the above-mentioned process is complicated and requires multiple deposition steps, whether in manufacturing Cost or time are not consistent with economic benefits, so a method for forming a bottle-shaped groove with a simplified process and high productivity is needed. In view of this, the main object of the present invention is to provide a method for forming a bottle-shaped groove with simplified manufacturing steps and economic benefits. In order to achieve the above object, the present invention mainly uses two depositions of an oxide layer, and then forms a sidewall protection layer on the upper half of the sidewall in the deep trench. The wet etching method expands the width of the lower half of the deep trench to form a bottle-shaped trench. The method of layering bottle-shaped grooves is suitable for the formation of a surface-layer structure; and a semiconductor substrate having a groove at a predetermined position, the steps include a) along the cushion structure and the groove ^, A dielectric layer; b) the first half of the pad structure below the trench and located on the bottom layer, C) the first half of the side wall of the Jiuyi ~ β trench is removed d) the The sacrificial layer 'is retained in the bottom half of the trench, and the first dielectric layer is left. E) Along the cushion structure and the trench; a second dielectric layer is formed conformably to the first dielectric layer. = Form a protective layer; g) Do you want to protect it in the rest of the time? H) Remove the second dielectric layer located at the bottom of the trench to form an open H bottom of the trench! ) The trench is exposed by using the sidewall protection layer as the first dielectric layer and the second dielectric layer of the mask removal position; ㈡: two
0548-8101TWF(N) ; 91025 : Phoebe .ptd 第7頁 550742 五、發明說明⑶ 二對幻冓槽下半部之側壁進行濕姓刻而形成下半 口IM廣大之瓿型溝：槽。 丁 及-半ίϊ基底上的墊層構造包括-氮化… 於兮笛一人層，。亥墊層係作為後續蝕刻步驟之硬罩幕。至 四二ϊ: m以及該第二介電層可使用介電材料，例如 mcvl f ΐ S)、次大氣壓化學氣相沈積氧化物0548-8101TWF (N); 91025: Phoebe.ptd Page 7 550742 V. Description of the invention ⑶ Secondly, the side wall of the lower part of the magical trough is engraved with a wet name to form a large ampoule-shaped groove in the lower part. The structure of the cushion layer on the substrate of Ding and -half ϊ includes -nitriding ... Yu Xidi one person layer. The underlayer serves as a hard mask for subsequent etching steps. To 422: m and the second dielectric layer may use a dielectric material such as mcvl f ΐ S), sub-atmospheric chemical vapor deposition oxide
oxide") ^X1 J 、電漿強化化學氣相沈積氧化物（PECVD )，盆ί姑二形成方法較佳為低壓化學氣相沈積（lpcvd 犧牲it二介電層之形成亦可使用高密度電漿。上述 光阻材料形成’而上述保護層較佳為擇自 氮化矽4之介電材料。 評曰 統移2 Lii發明用以移除介電層之步驟可藉由-般傳 氟酸（BHF)/、隹方法，例如以稀釋氫氧酸（DHF)或緩衝氫 )#進竹濕蝕刻，並無特定限制。 驟，t Ϊ t ί明之形成瓶型溝槽的方法，可大幅簡化步 用以：： 種符合經濟效益’節省製造時間及成本之 用以形成瓿型溝槽的方法。 < 下文發明之上述目的、特徵和優點更明顯易懂， =文特牛出較佺實施例，並配合所附圖示，作詳細說明如 實施例 其顯示本發明實施例之形成瓶型 請參閱第1Α〜1G圖 溝槽方法的製程剖面圖oxide ") ^ X1 J. Plasma-enhanced chemical vapor deposition oxide (PECVD). The method for forming the pot is preferably low-pressure chemical vapor deposition (lpcvd sacrifices the formation of the second dielectric layer. High-density electrical The above-mentioned photoresist material is formed, and the above-mentioned protective layer is preferably a dielectric material selected from silicon nitride 4. Commentary on the steps of the 2 Lii invention to remove the dielectric layer can be performed by -fluoric acid transfer (BHF) /, 隹 method, such as dilute hydroxide (DHF) or buffered hydrogen) # into bamboo wet etching, there are no specific restrictions. In this way, t 形成 t ming Ming ’s method for forming a bottle-shaped groove can greatly simplify the steps to: A method that is economical to save manufacturing time and cost and is used to form an ampoule-shaped groove. < The above-mentioned objects, features and advantages of the invention below are more obvious and easy to understand. Refer to Figures 1A to 1G.
550742 五、發明說明（4) 1 00 A依據主H圖’其顯示本發明之啟始步驟。其中基底 100,為一半導體材質，、例如由石夕材質組成，為方便說明起 麻1 ηη %此以一石夕基底為例。在提供一由石夕組成之半導體基 ； '，於該半導體基底1〇〇上形成一墊層構造（pad .layer)，例如以化學氣相沈積（Chemical Vapor Deposition，CVD)依序沈積氧化矽層1〇1於半 表及沈積-絕緣層如氮化石夕層103於氧化：：二 面，該氧化矽層101之厚度為2〇〇〜3〇〇〇A，而氮化矽層 103之厚度為20〜100 A »該墊層構造在此係做為用於^溝 槽蝕刻步驟之硬罩幕。 立v接著，在該墊疊層構造内形成一罩幕開口，以暴露出 部分半導體基底表面，例如可先利用光阻材料之塗佈及曝 光顯影等微景夕製程形成一光阻圖案於該墊疊層構造表面， 然後再利用反應性離子鍅刻（React ive i〇n Etching. RIE )或電漿蚀刻等蝕刻該墊疊層構造以形成一罩幕開口。 接下來，以電漿蝕刻該罩幕開口露出之半導體基底，因而 形成如第1A圖所示之溝槽丨〇2。上述形成溝槽的方法係包 括如反應離子餘刻法（Reactive l〇n Etching; RIE)以及 電漿银刻（Plasma Etching)等的非等向性乾餘刻 (Anisotropic Dry Etching) ° 然後，如第1B圖所示般，順應性沿著該氮化石夕層1〇3 以及該溝槽1 0 2之側壁形成一第一介電層1 〇 4後，再以例如 光阻材料填入該溝槽1 〇 2之下半部而形成一犧牲 (sacrificial )層106。該第一介電層104在本實施例係使550742 V. Description of the invention (4) 1 00 A shows the initial steps of the present invention according to the main H diagram. The substrate 100 is made of a semiconductor material, for example, composed of a material of Shi Xi. For convenience of description, the numbness is 1 ηη%. Here, a Shi Xi substrate is taken as an example. Provide a semiconductor substrate composed of Shi Xi; ', a pad .layer is formed on the semiconductor substrate 100, for example, silicon oxide is sequentially deposited by chemical vapor deposition (CVD) The layer 101 is on the half surface and the deposition-insulating layer such as the nitride nitride layer 103 is on the oxide :: two sides, the thickness of the silicon oxide layer 101 is 2000 ~ 3000A, and the thickness of the silicon nitride layer 103 is The thickness is 20 ~ 100 A »The underlayer structure is used here as a hard mask for the trench etching step.立 v Then, a mask opening is formed in the pad stack structure to expose part of the semiconductor substrate surface. For example, a photoresist pattern can be formed on the photoresist pattern by using a photoresist material coating and exposure development process. The surface of the pad stack structure is then etched by using reactive ion etching (RIE) or plasma etching to form a mask opening. Next, the semiconductor substrate exposed by the opening of the mask is etched with a plasma, thereby forming a trench ˜02 as shown in FIG. 1A. The method for forming the grooves described above includes anisotropic dry Etching such as Reactive lon Etching (RIE) and Plasma Etching. Then, such as As shown in FIG. 1B, after the compliance forms a first dielectric layer 104 along the sidewall of the nitrided layer 103 and the trench 102, the trench is then filled with, for example, a photoresist material. A sacrificial layer 106 is formed in the lower half of the groove 102. The first dielectric layer 104 is used in this embodiment.
〇548-8101TWF(N) ； 91025 ： Phoebe.ptd 第9頁 550742 五、發明說明（5) 用四乙基矽氧院（TE0S )，但不限於此，亦可使用其他介 電材料如次大氣壓化學氣相沈積氧化物（SACVD 〇xide)、 電毅強化化學氣相沈積氧化物（PECVD 〇xide)等。該第一 介電層之形成方法較佳係使用低壓化學氣相沈積（LPCVD )’而其厚度較佳為50〜600A。 接下來’以犧牲層1 〇 6為餘刻阻障，移除位於該氮化 石夕層1 03上以及該溝槽丨02上半部側壁的該第一介電層 1〇4 ’而保留如第lc圖所示之與該犧牲層1〇6相同高度的剩 餘第一介電層104，。 、接著，如第1D圖所示，去除該犧牲層1〇6後再次以CVD 方法順應性於該墊層以及該溝槽側壁形成一第，二介電層 107，例如電漿強化（plasma enhanced)PECVD 形成之te〇s 或厂般LPCVD形成之TE0S，並將該剩餘第一介電層1〇4，封 口後，再順應性形成一保護層1〇8於該第二介電層1〇7上 由於溝槽窄，第二介電層1〇7位於溝槽下;部易形 j有空隙105 (seam)，但在後續步驟將被移除，因此不 響元件性能。該保護層係以例如氮化石夕形成，但不限於 2矽，亦可使用其他材料，例如複晶矽（p〇ly siH⑶㈧氮 等，而該保濩層之沈積較佳係以低壓CVD進行。 然後，如第1E圖所示，移除位於該第二介電 該溝槽底部的該保護層108而保留位於該 側…層⑽，。此步驟移除該保 乾蝕刻（dry etching)進行。接著，糸乂 方法’例如使用稀釋氣氣酸(_)或緩衝= 二物等的對〇548-8101TWF (N); 91025: Phoebe.ptd Page 9 550742 V. Description of the invention (5) Tetraethylsiloxane (TE0S) is used, but it is not limited to this, other dielectric materials such as sub-atmospheric pressure can also be used Chemical vapor deposition oxide (SACVD oxide), electro-enhanced chemical vapor deposition oxide (PECVD oxide), etc. The method for forming the first dielectric layer preferably uses low pressure chemical vapor deposition (LPCVD) 'and its thickness is preferably 50 to 600A. Next, using the sacrificial layer 106 as a barrier, remove the first dielectric layer 104 on the nitrided stone layer 103 and the sidewall of the upper half of the trench 02 and leave it as The remaining first dielectric layer 104 ′ at the same height as the sacrificial layer 106 is shown in FIG. 1c. Then, as shown in FIG. 1D, after the sacrificial layer 106 is removed, the first and second dielectric layers 107 are formed on the cushion layer and the sidewall of the trench by CVD method, such as plasma enhanced (plasma enhanced). ) TECVD formed by PECVD or TEOS formed by factory-like LPCVD, and the remaining first dielectric layer 104 is sealed, and then a protective layer 108 is conformably formed on the second dielectric layer 10. Due to the narrow trench on 7, the second dielectric layer 107 is located under the trench; there is a gap 105 (seam) in the part shape j, but it will be removed in subsequent steps, so it does not affect the performance of the device. The protective layer is formed of, for example, nitride zirconia, but is not limited to 2 silicon, and other materials, such as polycrystalline silicon (polysilicon) nitrogen, etc., and the deposition of the protective layer is preferably performed by low pressure CVD. Then, as shown in FIG. 1E, the protective layer 108 at the bottom of the second dielectric trench is removed while remaining on the side ... layer ⑽. This step is performed by removing the dry etching. Next, the method 'e.g. using dilute gas acid (_) or buffer = two things, etc.
Η 0548-8101TWF(N) ： 91025 ； Phoebe.ptd 第10頁 550742 五、發明說明⑹ 位於該溝槽底部之 溝槽下半部的第一 示般露出該溝槽下 最後，針對該 槽下半部的寬度， 根據本發明之 習知技術更為簡化 符合經濟效益之用 雖然本發明已 限定本發明，任何 和範圍内，當可作 範圍當視後附之申 該第 介電層 半部之 溝槽下 而形成 形成瓶 ’而能 以形成 以較佳 熟習此 些許之 請專利 介電層進行開口，並移除位於該 以及第二介電層，而如第11?圖所 側壁1 2 0。 半部側壁1 20以濕蝕刻擴大該溝 如第1 G圖所示之瓶型溝槽1 2 0，。 型溝槽的方法，在製程步驟上比 提供一種節省製造時間及成本而 瓶型溝槽的方法。 實施例揭露如上，然其並非用以 技藝者，在不脫離本發明之精神 更動與潤飾，因此本發明之保護 範圍所界定者為準。 550742 圖式簡單說明 第1 A〜1 G圖係顯示根據本發明實施例之形成瓶型溝槽 的方法的製程剖面圖。 符號說明 1 0 0〜半導體^基底， 1 0 3〜氮化矽層； 104〜第一介電層； 1 0 7〜第二介電層； 1 08〜保護層； 1 2 0〜下半部側壁； 1 0 1〜氧化矽層； 102〜溝槽； 106〜犧牲（sacrificial)層； 104’〜剩餘第一介電層； 1 0 5空隙； 120’〜瓶型溝槽。Η 0548-8101TWF (N): 91025; Phoebe.ptd Page 10 550742 V. Description of the invention 的 The first illustration of the lower half of the groove at the bottom of the groove is exposed below the groove. Finally, for the lower half of the groove According to the conventional technology of the present invention, the width of the dielectric layer is more simplified and economically useful. Although the present invention has limited the present invention, within any and range, when it can be used as a range, the attached second dielectric layer half The formation of a bottle under the trench can be formed to better familiarize yourself with some of the patented dielectric layers for opening, and remove the and the second dielectric layer, as shown in Figure 11? Sidewall 1 2 0 . The half side wall 120 expands the groove by wet etching, such as the bottle-shaped groove 1220 shown in Fig. 1G. Compared with the method of forming grooves in the process steps, it provides a method of bottle grooves which saves manufacturing time and cost. The embodiment is disclosed as above, but it is not intended for a skilled person, and can be changed and retouched without departing from the spirit of the present invention. Therefore, what is defined by the protection scope of the present invention shall prevail. 550742 Brief Description of Drawings Figures 1A to 1G are cross-sectional views showing a process of forming a bottle-shaped groove according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 100 ~ Semiconductor substrate, 103 ~ Silicon nitride layer; 104 ~ First dielectric layer; 107 ~ Second dielectric layer; 08 ~ Protective layer; 120 ~ Lower half Side wall; 101 ~ silicon oxide layer; 102 ~ trench; 106 ~ sacrificial layer; 104 '~ residual first dielectric layer; 105 gap; 120' ~ bottle trench.
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