550606550606
圖4A顯示本發明第二實施例之LDO ; 圖4B顯示圖4A所用之Rm及Cm之分散組合之等值RC網 路 ； 圖4C為圖4A中電路之零及極之曲線； 圖5為圖4A中之LDO之相位邊際值作為電容性負載之函 數。 在全圖式中，相同參考號碼代表相似或對應之特性或功 能。 較佳實施例之詳細說明 圖2A顯示本發明第一實施例之LDO 30。LDO 30包括一具 有增益gm之放大器32, 一 PMOS電晶體Ml，IU，R2，R3及Rm， 及一米勒補償電容器Cm。作業放大器32有一負端點連接 至參考電壓Vref，一正端點連接至電阻器R1及R2之間，一 輸出端點連接至電晶體Μ 1之閘極端點。電阻器R3連接在 電晶體Ml(其亦為LDO 30之輸入）之源極端與電晶體Ml之 閘極端點之間《電容器Cm及電阻器Rm彼此串聯於電晶體 Ml之閘極端點與電晶體Ml之汲極端點之間。電容器Cm及 電阻器Rm增加一零於根軌跡圖中。電阻器R1及R2彼此串 連於電晶體Ml汲極端點與地位準之間。LD0 30之輸出連接 至負載20。 圖2B為一圖形顯示在圖2A之電路之不同負載之條件下 之零點及極點，其中Rm不等於零。 圖3顯示一實線及一虛線。實線顯示圖2A中之LDO 30之 相位邊際0作為Cl之函數，其中Rm=0 Ω。相位邊際圖為 550606Figure 4A shows the LDO of the second embodiment of the present invention; Figure 4B shows the equivalent RC network of the dispersed combination of Rm and Cm used in Figure 4A; Figure 4C is the zero and pole curve of the circuit in Figure 4A; Figure 5 is a graph The phase margin of the LDO in 4A is a function of the capacitive load. In the full drawings, the same reference numbers represent similar or corresponding features or functions. Detailed Description of the Preferred Embodiment FIG. 2A shows an LDO 30 according to a first embodiment of the present invention. The LDO 30 includes an amplifier 32 having a gain gm, a PMOS transistor M1, IU, R2, R3, and Rm, and a Miller compensation capacitor Cm. The operational amplifier 32 has a negative terminal connected to the reference voltage Vref, a positive terminal connected between the resistors R1 and R2, and an output terminal connected to the gate terminal of the transistor M1. The resistor R3 is connected between the source terminal of the transistor M1 (which is also the input of the LDO 30) and the gate terminal of the transistor M1. The capacitor Cm and the resistor Rm are connected in series to the gate terminal of the transistor M1 and the transistor. Between Ml's drain extremes. The capacitor Cm and the resistor Rm are increased by zero in the root locus map. The resistors R1 and R2 are connected in series with each other between the drain terminal of the transistor M1 and the standard. The output of LD0 30 is connected to load 20. Figure 2B is a graph showing the zeros and poles under different load conditions of the circuit of Figure 2A, where Rm is not equal to zero. Figure 3 shows a solid line and a dotted line. The solid line shows the phase margin 0 of LDO 30 in FIG. 2A as a function of Cl, where Rm = 0 Ω. Phase margin plot is 550606
LDO中故大器之開路迴路。放大器之閉路迴路之相位邊際 為零。圖3中，正相位邊際表示穩定，而負值表示振堡。 大多數LDO應用需要40度或更多之相位邊際，以在一穩 定條件中操作。在Rm=0 Ω，實線顯示相位邊際0僅在c L 之最大及最小值時為正。參考”一無條件穩定二級CMOS 放大器”，固態電路之IEEE雜誌，1955年5月卷30，No.5 , 由 Richard J· Reay及 Gregory Τ·Α· Kovacs所著，以參考方式併 入此間。Rm之值可選擇為使相位邊際在CL範圍之中部獲 得改進，即，當Rm=0.5*R3。 圖3中，虛線顯示LDO 30之相位邊際0作為CL之函數， 其中Rm妾0及Rm=0.5*R3 ^虛線上，當相位邊際0為最大值 時，（^=(§ιη)*(Ι13)*((：Γη)。虛線顯示LDO 30將在CL所有值穩 定，因為所有相位邊際大於零。當，CL之某些值時，相 位邊際可為接近零，其在某應用時可能不理想。 圖4A顯示本發明第二實施例之LDO 40，及Rm與Cm之分 散組合。此實施例與圖2A之實施例相似，但其利用Rm及 Cm除外。圖4B顯示一圖4A之Rm及Cm組合之等值RC網路 60。RC網路60包括η個電阻器，各有一（l/n)(Rm)值，及η個 電容H，各有（l/n)(Cm)值。η電阻器之和為Rm，η電容器之 和為Cm。再者，RC網路之總尺寸保留不變，與Rm及Cm之 組合-樣。 本發明之第二實施例有一優點，即零與對應之極分散於 某一範圍，如圖4C所示之CL之不同值。零之數目較極之 數目多一個。圖4C中，大對應圖2B中之極，出現於圖 550606 (5) 4 C僅為比較目的。 分散零與對應極之優點在圖5中甚為明顯，其顯示第二 實施例之LDO 40之相位邊際值覆蓋圖3之圖形。如圖5所 示，LDO 40之相位邊際，Cl之全部範圍目前至少為45度。 此舉使LDO 40適於任何電容性負載。 由於本發明可提供所有電容性負載之穩定LDOs，ESR不 再影響ESR及CL組合之等值。因此，本發明有效的移除負 載上ESR限制。 應注意，雖然一 PMOS電晶體Ml顯示於上圖中，一 pnp雙 極電晶體亦可使用。 本發明已與特殊實施例敘述如上，許多修改及變化對精 於此技藝人士甚為明顯。準此，擬將合乎本申請專利範圍 之精神與範疇，之所有修改及變化包含在内。 圖式元件符號說明 10 低 電 壓 降 調 整 器 12 故 大 器 20 負 載 30 低 電 壓 降 調 整 器 32 故 大 器 40 低 電 壓 降 調 整 器 60 等 效 RC網路 cm 米 勒 補 償 電 容 器 CL 電 容 性 負 載 Ml 電 晶 體 -11 - 550606 (6) R1 電阻 R2 電阻 R3 電阻Open circuit of an old LDO. The phase margin of the closed loop of the amplifier is zero. In Figure 3, the positive phase margin indicates stability, while the negative value indicates Zhenbao. Most LDO applications require a phase margin of 40 degrees or more to operate in a stable condition. At Rm = 0 Ω, the solid line shows that the phase margin 0 is positive only at the maximum and minimum values of c L. Refer to "An Unconditionally Stable Secondary CMOS Amplifier", IEEE Journal of Solid-State Circuits, Volume 30, No. 5, May 1955, by Richard J. Reay and Gregory T. A. Kovacs, incorporated herein by reference. The value of Rm can be selected so that the phase margin is improved in the middle of the CL range, that is, when Rm = 0.5 * R3. In Figure 3, the dotted line shows the phase margin 0 of LDO 30 as a function of CL, where Rm 妾 0 and Rm = 0.5 * R3 ^ On the dotted line, when the phase margin 0 is the maximum, (^ = (§ιη) * (Ι13 ) * ((: Γη). The dashed line shows that LDO 30 will be stable at all values of CL, because all phase margins are greater than zero. When certain values of CL, the phase margin may be close to zero, which may not be ideal in some applications. Figure 4A shows the second embodiment of the present invention LDO 40, and the dispersed combination of Rm and Cm. This embodiment is similar to the embodiment of Figure 2A, except that it uses Rm and Cm. Figure 4B shows a Rm and Cm combination equivalent RC network 60. RC network 60 includes n resistors, each having a value of (l / n) (Rm), and n capacitors H each having a value of (l / n) (Cm). The sum of the η resistors is Rm, and the sum of the η capacitors is Cm. Furthermore, the total size of the RC network remains unchanged, and is the same as the combination of Rm and Cm. The second embodiment of the present invention has an advantage, that is, zero and The corresponding poles are scattered in a certain range, as shown in the different values of CL shown in Figure 4C. The number of zeros is one more than the number of poles. In Figure 4C, the large corresponding poles in Figure 2B appear in Figure 550606 (5) 4C is for comparison purposes only. The advantage of scattered zeros and corresponding poles is evident in Figure 5, which shows that the phase margin of the LDO 40 of the second embodiment covers the graph of Figure 3. As shown in Figure 5, the phase of the LDO 40 Margin, the full range of Cl is currently at least 45 degrees. This makes LDO 40 suitable for any capacitive load. Since the present invention can provide stable LDOs for all capacitive loads, ESR no longer affects the equivalent value of ESR and CL combination. Therefore The invention effectively removes the ESR limitation on the load. It should be noted that although a PMOS transistor M1 is shown in the figure above, a pnp bipolar transistor can also be used. The invention has been described above with special embodiments, many modifications and Changes are obvious to those skilled in this art. Therefore, it is intended to include all modifications and changes that are in line with the spirit and scope of the patent scope of this application. Symbol description of the diagram elements 10 Low voltage regulator 12 20 Load 30 Low voltage drop regulator 32 So big 40 Low voltage drop regulator 60 Equivalent RC network cm Miller compensation capacitor CL Capacitive load Ml transistor -11-550606 (6) R1 resistor R2 resistor R3 resistor
Rl 電阻性負載Rl resistive load
Rm 電阻器Rm resistor
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