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五、 發明說明（ 本發明係有關一種如申請專利範圍第丨項之整合蜇邏輯電 路。 可転式規劃之邏輯電路也稱做為「fpga單元」，該邏.輯 電路之衣以目的係為了生產具有高功能的快速記憶體電路 此等邈輯電路例如由其中儲存程式之所謂的「sRAM單 元」或*閃單元」驅動，如WO 99/34515 A1所述。 所明之丨夬閃單兀」比較邏輯電路，特別用於寫入及抹 消，需要顯著較高的操作電壓來操作。當二電路截面整合 :二片丁捋別卩思著微縮化程度的提高，結果於記憶單 元之南程式規劃電塵盘丨羅輕垂 〇〇 〃 k輯電路之低操作電壓間的隔離呈 現嚴重問題。特別此虚塑音 ^ ^ 白吊使用之场效電晶體所用閘極 :化物之崩潰電麼各自不同’而於此處無法匹配。若邏輯 兒路之場效電晶體閘極氧化物配接至快閃記憶體單元之閉 圣氧化物’則雖，然整體配置可運作，但操作性質受損。 如此本發明係基於下述目的，本發、 整合型邏輯電路，其中使用簡 、’丁、θ供-種 平亍奴讓彳呆作性質维括如 信度。Ρ使私路几件设計成不同操作電麼仍然維持操作的可 此項目的根據本廣明可利用申請專利範圍第4 施達成。由於配接電路設置於記憶單元之、」二的措 與邏輯切換電路輸入端間，邏輯切換元件盘=:輪出端 不同操作電壓操作，容易隔離操作電壓。 〜早兀可依 本發明之有利細節更進—步界定於申 項。由於！己憶單元可以第—摔作 、圍之附屬 永作'⑹呆作，邏輯切換電路 本紙張尺度適用中^^^CNS) A4規格(2101 297公釐） 裝 訂 線 -5 - 550574 五、發明說明（2 可以第二操作電壓操作 ，且第一操作電壓係高 又南於第二操作電麗， 離。 配接I路可以第三操作電壓操作 於第三操作電麼，m第三操作電m 因此可有利地確保操作電壓間的隔 二：有利地應用於快閃記憶體單元做為記憶單元。 本於明之:附體實施例說明本發明1®顯示根據 / 1合型邏輯電路之基本組成。設置邏輯切換電路 _^具體實施例中，邏輯切換電路係以場效電晶體T1 ,X %阳連接至第二操作電壓’該第二操作電壓係 由電位SP3及SP4組成。反相器階段β之輪出連接至電晶體 T1之閘極端’其表示邏輯切換元件以之輸入端4。反相器階 串連連接至場效電晶體T3及T4，而電晶體T3及 T4之共通輸出節點表示反相器階段is之輸出端3。反相器階 4又收由第—▲作電壓操作，第三操作電壓係由電位奶及 SP6組成。 電曰曰 1體T3及T4之二開極端彼此連接且表示反相器階段之 輸入％ 2反相益階段IS之輸入端2連接至習知快閃記憶體 單元FS之輸出端丨。快閃記憶體單元以又連接至第一操作電 壓’其係由電位SP1及SP2組成。 今日快閃吕己憶體單元之維度要求採用高電壓。如此，反 相器階段之維度設計用於第三操作電壓，其設計方式讓由 快閃a己憶體單7〇經由輸出端i到達的信號藉反相器階段1§之 輸入纟而2接收，且經轉換而二電晶體丁3及丁4未受損。如此， 反相ι§階段之維度設計為快閃記憶體單元FS之反相後信號 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱) 550574 A7 B7 五、發明説明（3 ) ，存在於輸出端3，可被饋至邏輯切換電路LS之輸入端4， 而電晶體T 1未受損。 所示配置允許快閃記憶體單元FS進行可靠程式規劃操作 ，而過程中邏輯切換元件LS未受危害，該元件可同時操作 ，調整配合第二操作電壓，操作性質不受限制。 裝 特別，FPGA單元之程式規劃可以獨特方式用於前述發明 。此種情況下，可免除額外反相器階段需要占用積體電路 晶片面積的缺點，FPGA單元的操作性質得以維持，FPGA 單元之操作性質不因技術調整配合快閃記憶體單元而受損 ，換言之，由於使用高電介質強度的電晶體而造成FPGA單 元不當地變慢。 訂V. Description of the invention (The present invention relates to an integrated logic circuit such as the one in the scope of patent application. The logic circuit that can be planned is also called an "fpga unit". The purpose of the logic circuit is to The production of such high-speed flash memory circuits is driven, for example, by so-called "sRAM units" or flash units, which store programs therein, as described in WO 99/34515 A1. What is known is "flash unit" Comparing logic circuits, especially for writing and erasing, requires significantly higher operating voltages to operate. When the two circuit sections are integrated: the two pieces of Ding Ding do n’t think about the increase in the degree of miniaturization, and the result is planned in the south of the memory unit. Electrostatic dust disk 丨 Luo Qingping 〇〇〃 The isolation between the low operating voltage of k series circuits presents a serious problem. In particular, this virtual plastic sound ^ ^ The gate used by the field effect transistor used by Bai Hang: the breakdown of the compounds are different. 'And there is no match here. If the field-effect transistor gate oxide of the logic circuit is connected to the sacred oxide of the flash memory unit', although the overall configuration can work, but the operating nature Therefore, the present invention is based on the following purposes, the present invention, an integrated logic circuit, in which the use of Jane, Ding, θ-a kind of flat nuisance to keep the nature of the work such as reliability. P to make a few private roads Designed to operate with different operating power and still maintain operation, this project can be achieved according to the fourth application of the patent application scope. Because the matching circuit is provided between the memory unit and the second switch and the input of the logic switching circuit, Logic switching element disk =: Different operating voltages at the output of the wheel, easy to isolate the operating voltage. ~ Early, you can go further according to the advantageous details of the present invention-the step is defined in the application. Because! Subsidiary Yong Zuo's dumb work, logic switching circuit This paper size is applicable ^^^ CNS) A4 size (2101 297 mm) Gutter -5-550574 5. Description of the invention (2 can be operated with the second operating voltage, and the An operating voltage is higher and lower than the second operating voltage. Can the third operating voltage be connected to the third operating voltage when the I channel is connected? M The third operating voltage m can thus advantageously ensure that the operating voltage is separated by two. :advantageous It is applied to the flash memory unit as the memory unit. The present invention describes the basic composition of the 1® display logic circuit according to the embodiment of the present invention. Set the logic switching circuit. ^ In the specific embodiment, the logic switching The circuit is connected to the second operating voltage with a field effect transistor T1, X% positive. This second operating voltage is composed of potentials SP3 and SP4. The phase out of the inverter phase β is connected to the gate terminal of transistor T1. Represents the logic switching element with its input terminal 4. The inverter stages are connected in series to the field effect transistors T3 and T4, and the common output node of the transistors T3 and T4 represents the output terminal 3 of the inverter stage is. Inverter Stage 4 receives voltage operation from the first-▲, the third operation voltage is composed of potential milk and SP6. The two open ends of the body T3 and T4 are connected to each other and indicate the input of the inverter phase. 2 The input terminal 2 of the inverter phase IS is connected to the output terminal of the conventional flash memory unit FS. The flash memory unit is connected to the first operating voltage ', which is composed of potentials SP1 and SP2. The dimensions of today's flash Lu Jiyi body units require high voltages. In this way, the dimension of the inverter stage is designed for the third operating voltage, and the design method is such that the signal reached by the flash a memory module 70 via the output terminal i is received by the input 纟 of the inverter stage 1 and 2 , And the two transistors Ding 3 and Ding 4 were not damaged. In this way, the dimension of the inverse phase is designed as the inverted signal of the flash memory unit FS-6-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 public love) 550574 A7 B7 V. Description of the invention ( 3), exists at the output terminal 3, and can be fed to the input terminal 4 of the logic switching circuit LS, and the transistor T1 is not damaged. The configuration shown allows the flash memory unit FS to perform reliable program planning operations, while the logic switching element LS is not harmed during the process, the elements can be operated simultaneously, and the second operating voltage can be adjusted to cooperate, and the operation nature is not limited. In particular, the programming of FPGA units can be used in a unique way for the aforementioned inventions. In this case, the disadvantages of occupying the integrated circuit chip area in the additional inverter stage can be avoided, and the operating properties of the FPGA unit are maintained. The operating properties of the FPGA unit are not damaged due to technical adjustments and flash memory units, in other words Due to the use of high-dielectric-strength transistors, the FPGA unit is unduly slowed down. Order
本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 550574 Α7 ^ Β7 五、發明説明（4 ) 參考符號表 FS 記憶體單元 IS 配接電路，反相器電路 LS 邏輯切換元件 SP卜 SP2 第一操作電壓 SP3，SP4 第二操作電壓 SP5，SP6 1 第三操作電壓 記憶體单元輸出端 2 3 反相器電壓輸入端 反相器電壓輸出端 4 邏輯切換單元輸入端 T1 場效電晶體 A7 B7 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐)This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 550574 Α7 ^ Β7 V. Description of the invention (4) Reference symbol table FS Memory unit IS Adapter circuit, inverter circuit LS logic switching element SP SP2 First operating voltage SP3, SP4 Second operating voltage SP5, SP6 1 Third operating voltage memory unit output 2 3 Inverter voltage input Inverter voltage output 4 Logic switching unit input T1 Field effect transistor A7 B7 -8- This paper size applies to Chinese National Standard (CNS) A4 (210 x 297 mm)