TWI285375B - Voltage level converting circuit for use in flash memory - Google Patents

Abstract

This invention provides a voltage level converting circuit for use in flash memory. A voltage level detector is employed to provide a reference voltage level, and there are two pairs of coupled PMOS transistors each connected to the voltage level detector, wherein one pair is connected to a first voltage and the other pair determines the gate bias using the voltage level detector. There are two pairs of coupled NMOS transistors, wherein on end thereof is connected to the second voltage and an input end respectively. One of the two pairs is connected to one pair of PMOS transistors, and the other end thereof is connected to an output end. The other pair is connected by means of an inverting amplifier and is further connected to ground. The voltage level converting circuit of this invention allows high-voltage level to pass through and is provided with a wide voltage range for the working power source.

Description

1285375

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage circuit applied to a flash memory, and more particularly to a voltage level conversion circuit having a wide operating power supply voltage range = flash memory. j application [prior art] Figure 1 shows the internal circuit block of the current flash memory. The flash memory 1 includes a bit address decoder/encoder 丨0, a connection bit address 2 encoder Η voltage level conversion The circuit 12, a charging pump 14 and a / / device 己 兀 16 16 are respectively connected to the voltage level conversion circuit 12, in the fast, two body 10 requires a voltage level conversion circuit 12 to transfer the high voltage Vpp to < fast Flash_Gate or Gate of memory element 16 to complete functions such as program writing or data erasing (Erase). However, due to the fact that there is no high-voltage metal-oxide-semiconductor (M0S) device in the semiconductor process of standard logic components, high-voltage circuit design is produced for flash memory devices using such a process. Troubled. 2 is a detailed circuit diagram of a voltage level conversion circuit 12 in the prior art, and please refer to the operation timing diagram of FIG. 3, when the input terminal In %Logic Hi (Vcc voltage level), N-channel metal oxide The semiconductor (N-channel Metal-Oxide Semi Conductor; NM0S) M4 is in a closed state, and the P-channel Metal-Oxide Semi Conductor (PM0S) M2 is in an on state, and the output terminal Out voltage level is Vpp. The other output terminal Out2 is d because NMOS M3 is in the on state:

Page 5 1285375 V. Description of invention (2) Grounding level, where Vpp > Vcc, at this time, the gate of PM0S % is subjected to Vpp, the higher the Vpp, the greater the damage to PMOS M2, the higher the damage The output Out of the level may cause the NMOS Μ* 汲 extreme junction to collapse (juncti〇rl break down) 〇" When the input terminal 111 is [〇21(: Low), NM〇sa is at In the on state, the voltage level of the output terminal Out is the grounding level, and the other output ^Out:2 is in the off state due to the NMOS Ms, and the pmos & is in the on state, and is Vpp, at this time the gate of the PMOS Mi is subjected to The level is Vpp. The higher the Vpp is, the greater the damage to the reliability of the PMOS. The high-level output can collapse the 汲 extreme junction of Lu Cheng NMOS M3 (juncti〇n break d〇wn). Another detailed circuit diagram of the voltage level conversion circuit 12 in the prior art, and please refer to the operation program diagram of FIG. 3, when the input terminal h is Logic Hi (voltage level is Vcc), NM〇s M?, The heart is in the off state. Since the PMOS Ms and M4 are in the on state, the power source Vpp charges the output terminal Out via pM〇s and Μ4. The output terminal 0ut is Vpp level, n〇de ^ is also VPP level; the other output terminal 〇^2 is grounded by Ms and Me of 0, and the level of node W12 is Vcc +丨vtp Bu vtp is the starting potential of pM〇s Μ or M4. When the input terminal In is Logic Low, it is the zero-conducting center, and the output terminal Out is discharged to the grounding level via the NMOS MT. The other output terminal Out2 is charged to the vpp level by *PM0S Mi, M2, n〇de w is the VPP level, and the level of node %4 is Vcc +丨ηρ丨, this technique, the kiosk PMOS M2 And the gate bias of A is at a fixed level Vcc, and the reliability is because the bias voltage of each element is less than Vpp-,

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Vcc. But its biggest disadvantage is that the operating voltage range is between Vcc + 2Vtp and Vpp. 'Fake Vpp is supplied by the internal charge pump (charge pUmp). When it appears a downward glitch due to the instantaneous high current load, it may make this The circuit does not work properly (refer to the dotted line shown in Figure 3). In view of the above, the present invention is directed to the above-mentioned problems, and proposes a voltage level conversion circuit for applying a flash memory to improve the above-mentioned deficiency. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flash memory CMOS voltage level conversion circuit, which utilizes a transistor component device under a general logic semiconductor process to design a high voltage level. A voltage level conversion circuit with a wide operating supply voltage range. Another object of the present invention is to provide a voltage level conversion circuit for a flash memory, which can determine a gate bias of a portion of a pM〇s transistor, when the reference voltage level is less than a predetermined value. The gate bias of the pM〇s transistor is a grounding level, and when the reference voltage level is greater than a preset value, the gate bias of the PMOS transistor is equal to or greater than the second voltage Re. In order to achieve the above object, the present invention provides a voltage level conversion circuit applied to a flash memory device, including a voltage level detector, which has a reference voltage level and is coupled to two pairs. The pM〇s transistors respectively go to the voltage level detector, and one pair of pM〇s transistors is connected to a first voltage phase, and the other pair uses a voltage level detector to determine the gate bias, and another one One end of the coupled 0S transistor is respectively connected to a first voltage and an input terminal' and a pair of os transistors are connected to a pair

1285375

PMOS transistor, and the other end is connected to a crystal system by using an inverting amplifier, and then: connected: another:: ^ ^ < cut to a ground. The purpose and technical content of the present invention can be easily understood by the specific embodiment of the present invention by means of a specific embodiment. W point and its achieved work [Embodiment] The present invention provides a voltage level applied to the flash memory ^=5 is the internal circuit block of the flash memory proposed by the present invention: flashing The memory 2 includes an address decoder/encoder connected to Vcc, a voltage level conversion circuit 22, a ^VPP/VCC switching circuit 24 and a flash memory element 26 connected to the address decoding/encoder 20 are respectively connected to ' = level conversion circuit 22, and a charging pump 28 is connected to the cc switching circuit 24. The present invention is designed to utilize a voltage level conversion circuit 22 to design a high voltage level and a wide operating power supply voltage range. The seventh diagram is a detailed circuit diagram of an embodiment of the voltage level conversion circuit 22 of the present invention. The voltage level conversion circuit 2 2 includes a voltage level detector 3 〇 for providing a reference voltage level, and has two pairs of coupled PM 〇s transistors 32, 34, which are connected to the voltage The level detector 3〇, and a pair of PM〇s transistors 32 are connected to the first voltage Vpp/Vcc, and the first voltage Vpp/Vcc can be switched by Vpp/Vcc switching circuit 24 for Vpp or Vcc. The other pair of pmos transistors 34 use the voltage level detector 30 to determine the gate bias voltage Vbias, and have two pairs of phase-coupled NM0S transistors 36, 38, one end of which is connected to one

Page 8 9 1285375 V. Description of the Invention (5) The second voltage Vcc and an input terminal In, and wherein a pair of NMOS transistors 36 are connected to a pair of PMOS transistors 34, and the other end is connected to an output terminal 〇ut, The other pair of NMOS transistors 38 are connected by an inverting amplifier 40 and connected to a ground terminal VSS. ... In the beginning, the voltage level is preset to the second voltage, vcc 'when the setting of the input level is completed, the voltage level is switched to the first voltage Vpp/Vcc; the voltage level detector 3〇 The reference voltage Vbias level is provided according to the first voltage Vpp/Vcc level, which may be the second voltage Vcc and the grounding level, or a third voltage and grounding level, and the third voltage is higher than the sinusoidal voltage Vcc is lower than the first voltage 仏{)/^(:(:: level; in other words, when the first voltage level is less than a predetermined value, that is, two to three times the second voltage Vcc, the PMOS transistor 34 The gate bias voltage is a grounding level, and when the first voltage level is greater than a preset value, the gate bias voltage of the PMOS transistor 34 is equal to or greater than the second voltage Vcc. The voltage level conversion circuit 22 includes a voltage level. The bit detector 3A further includes a first p-channel metal oxide semiconductor M1 having a source (s〇urce) connected to a second voltage Vpp/Vcc and a second p-channel metal oxide semiconductor having a gate ( Gate), the source is connected to the reference voltage "1 & 5 level and 2 - p channel metal oxide semiconductor Μι's Drain, and the t-channel metal oxide semiconductor Μι is infinite, and has a first N-channel gold m _, 彡 gate and source are respectively connected to the - input terminal 1η and -:, VSS, and No.: Nii channel metal oxidized half, its drain, Ray If, respectively, is connected to the second-channel metal oxide semiconductor M3, the first-electrode MVcc and the -N-channel metal oxide semiconductor A, and 1285375 V. INSTRUCTIONS (6) " - The first P-channel metal oxide semiconductor trench, the gate and the source of which are respectively connected to the drain of the p-channel metal oxide semiconductor and the first voltage, and the fourth P-channel metal % of the oxidized semiconductor, the gate and the source are respectively connected to the reference voltage Vbias level and the drain of the third p-channel metal oxide semiconductor ,, and the substrate is connected to the drain of the third p-channel metal oxide semiconductor ,, and one The third N-channel metal oxide semiconductor has its gate and source respectively connected to an inverting discharge, the output end of the device 40 and the ground terminal Vss, and further includes a fourth N-channel metal oxide, a semiconductor Ms, and a drain thereof. The gate and the source are respectively connected to the fourth p-channel metal oxide semiconductor Me The pole, the second voltage Vcc and the third N-channel metal & the semiconductor M7 of the drain. Figure 7 is another internal detailed circuit diagram of the voltage level conversion circuit of the present invention, the voltage level conversion circuit 22 includes a voltage The level detector 30 is configured to provide a reference voltage level Vbias and has a first p-channel metal oxide semiconductor Mg whose source is connected to the first voltage Vpp/Vcc and a second P-channel metal oxide semiconductor 4 G, the gate and the source are respectively connected to the reference voltage Vbias level and the first P-channel metal oxide semiconductor ^, and the substrate is connected to the first P-channel metal oxide semiconductor germanium, and a first n The channel metal oxide semiconductor Mu has a gate and a source respectively connected to an input terminal ^ and a ground terminal Vss, and a second N-channel metal oxide semiconductor I, the Lu, the gate and the source are respectively connected to the second The P-channel metal oxide semiconductor 2 body ^, the second voltage Vcc and the first N-channel metal oxide semiconductor Mu and the pole, there is a third P-channel metal oxide semiconductor Mu, the source is connected to the first Voltage Vpp/Vcc, and a fourth P channel metal Oxidized semiconductor I, whose light, gate and source are respectively connected to the first P-channel metal oxide semiconducting body

1285375 Reference electric MVbias level and third p-channel metal oxide semiconductor Mi3 5, invention description (7)

汲=A, and the substrate is connected to the drain of the third p-channel metal oxide semiconductor m13 and a third N-channel metal oxide semiconductor I, the gate and the source thereof are respectively connected to one, the phase amplifier 4 is turned out and grounded The terminal Vss has a fourth N-channel metal oxide semiconductor, and the drain, the gate and the source thereof are respectively connected to the drain of the fourth P-channel metal oxide semiconductor Mu, the second voltage Vcc and the third N-channel metal oxide semiconductor. M15 is not very good. FIG. 8 is another internal detailed circuit diagram of the voltage level conversion circuit of the present invention. The voltage level conversion circuit 22 includes a voltage level detection unit </ RTI> for providing a reference voltage level. 3, and a first p metal oxide semiconductor 1, the source of which is connected to the first voltage Vpp / Vcc; a ~ P channel metal oxide semiconductor, the gate and source are respectively connected to the reference voltage Vbias level and the first The drain of the p-channel metal oxide semiconductor I, the substrate is connected to the drain of the first P-channel metal oxide semiconductor Mn; the first-channel metal oxide semiconductor Mlg, the gate and the source thereof are respectively connected to an input and a ground a second N-channel metal oxide semiconductor I, wherein the n-pole, the gate, and the source are respectively connected to the second P-channel metal oxide half 2Q conductor and the second voltage Vcc and the first N-channel metal oxide Semiconductor i, g; - third P-channel metal oxide semiconductor', whose gate and source are divided into the second P-channel metal oxide semiconductor's drain and the first voltage scraper Vpp/Vcc, · a fourth P channel The metal oxide semiconductor M22 has its gate connected to the reference voltage Vbias level and the third p-channel metal oxide half-pole M?1, and the substrate is connected to the third p-channel metal oxide semiconductor 乂Zhaoji; The third N-channel metal oxide semiconductor I, its gate and source = ^ 1285375 V. Description of the invention (8) Receive an inverting amplifier 40 output and ground 'Vss; and a fourth N-channel metal oxide semiconductor I, the drain, gate and source are respectively connected to the fourth P channel The metal oxidizes the drain of the semiconductor I, the second voltage Vcc, and the drain of the third N-channel metal oxide semiconductor M23. Μ"Source (node w 3 4 ) voltages M6, Mn, M12, M19, M2G turn off the voltage of M18 source PM0S Μ!, Μ9, Μ17 in the on state, pm〇s Μ2, M1Q pole (node wl2) The level is pushed up to Vpp; PM〇s Μι Among them, the second P-channel metal oxide semiconductor dock of the sixth, seventh, and eighth diagrams, M10, Mls, and the fourth p-channel metal oxide semiconductor Μβ, I, 屯 gate The bias voltage is determined by the voltage level detector 30. When the first voltage level is less than a predetermined value, that is, one to two times the second voltage VCC, the gate bias is the ground level, and when the first When the voltage level is greater than the preset value, the gate bias is equal to or equal to the second voltage Vcc, and the operation timing is as shown in FIG. 9. When the input terminal In is IL〇w(0v), NM0S m7, m8 , Mi5, Μΐβ, m23, m24 in the on-state 2 output terminal Out and the voltage levels of the NMOS M?, M15, Mu 汲 are pulled down to 〇V (grounding level), pm 〇s M6, M14 bits are Vbias+ 丨Vtp I ; NMOS Μ state M17, Μ u power! Push 到 to V pp ; PMOS %, M2, M9, the gate is subjected to the level of Vpp-Vbias-|Vtp| Reliability, vtp is the threshold voltage of PM0S m2, Miq, ^jM22; input terminal 匕 is .18 voltage level), NMOS M5, M6, Mn, M12, M19, M2. In the on state, The voltage levels of the node Out2 and the NMOS Ms, Mn, and Mlg 拉 are pulled down to 0 V (grounding level), and the voltage levels of the PMOS M2, M10, and M18 sources (node w 1 2 ) are Vbias+lVtpl. ;NM0S M7, M8, M15, M16, M23, M24 are off, PMOS is on, output 〇ut and pM〇s Page 12 V. Invention Description (9) 虬Μί4 ^Source (node w34) The voltage level is pushed up to Vpp, · pM〇s ίΛ, Af 1/ \r — the level of the interpole is Vpp-Vbias

Ml7, M

[18 Μι, M2, M9, Mj

Ihpl large &amp; amplitude improves the reliability of component devices. Road n:: ϋ A voltage level conversion power applied to the flash memory..^ The transistor component device under the general logic semiconductor process, and uses the voltage level to detect, f丨丨 cry, also—such as 'package The daily version of the 1st dry table is set, and the gate bias of the s-, _, 疋邛/knife transistor components is designed to rush out through the two-press level and have a level conversion circuit. There is a voltage for the dry voltage of the power supply voltage = the above description is based on the characteristics of the present invention, and those skilled in the art can understand the invention, the patent scope of the invention, and therefore the other is not detached; : The equivalent modification or modification completed shall still be included in the scope of the fine patent. r Application 1285375 Brief description of the diagram w [Simple description of the drawing] Fig. 1 is a schematic diagram of the internal circuit block of the conventional flash memory. Figure 2 is a detailed circuit diagram of a conventional voltage level conversion circuit. Figure 3 is a diagram showing the operation of a conventional voltage level conversion circuit. Fig. 4 is a schematic diagram showing another detailed circuit of a conventional voltage level conversion circuit. • Fig. 5 is a block diagram showing the internal circuit of the flash memory of the present invention. Figure 6 is a detailed circuit diagram of one of the voltage level conversion circuits of the present invention. The Φ 7 diagram is another detailed circuit diagram of the voltage level conversion circuit of the present invention. Figure 8 is a further detailed circuit diagram of the voltage level conversion circuit of the present invention. Figure 9 is a diagram showing the operation of the voltage level conversion circuit of the present invention. [Main component symbol description] 1 flash memory 10 address decoding / encoder 1 2 voltage level conversion circuit • charging pump 1 6 flash memory component 2 - flash memory 20 address decoding / encoder 22 voltage Level conversion circuit

m Page 14 8 1285375 Schematic description of the '24 Vpp/Vcc switching circuit 2 6 flash memory component 28 charging pump 30 voltage level detector _ 32, 34 PMOS transistor 36, 38 NMOS transistor &lt; 40 Inverting amplifier

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Claims (1)

1285375 VI. Patent Application Range 1 · A voltage level conversion circuit applied to flash memory, which includes: '..., voltage level detector for providing a reference voltage level ·, two pairs of phase coupling Connected to the PMOS transistor, which is respectively connected to the voltage level detector, wherein a pair of the PM〇s transistors are connected to a first voltage, and the other uses the voltage level for the PMOS crystal system The bit detector determines a gate bias voltage; and two pairs of phase coupled NMOS transistors, one end of which is respectively connected to a second voltage and an input terminal, and wherein a pair of the NMOS transistors are connected to a pair of the NMOS transistors The MOS transistor has the other end connected to an output terminal, and the other is connected to the ground terminal by an inverting amplifier. The voltage level conversion circuit applied to the flash memory according to the first aspect of the invention, wherein the voltage level detector provides the reference voltage level according to the first voltage level. The voltage level conversion circuit applied to the flash memory according to the first aspect of the invention, wherein the reference voltage level is the second voltage or ground level. The voltage level conversion circuit applied to the flash memory according to the first aspect of the invention, wherein the reference voltage level is a third voltage or a ground level, and the third voltage is high. And the second voltage is lower than the first voltage level. 5. The voltage level conversion circuit applied to the flash memory according to the first aspect of the patent application, wherein the reference voltage level is less than a predetermined value, the gate bias of the PMOS transistor Is the grounding level, and when the reference voltage Page 16 8 1285375 VI. Patent Application Range * When the level is greater than the preset value, the gate bias of the PMOS transistor is equal to or greater than the second voltage. 6. The voltage level conversion circuit applied to the flash memory according to claim 5, wherein the preset value is two to three times the second voltage. 7. The voltage level-level conversion circuit applied to the flash memory according to claim 1 of the patent application, wherein the voltage level is preset to the second voltage, and when the input level is set, the voltage is applied. The level is switched to the first voltage. Page 17 8