DE10114611A1 - Integrated logic circuit - Google Patents

Abstract

A logic circuit is provided with at least one logic switching element, at the input of which an output signal from the memory cell output can be fed to a memory cell. A matching circuit is provided between the input of the logic switching element and the output of the memory cell.

Description

The invention relates to an integrated logic circuit according to Claim 1.

For the production of fast integrated circuits with high Functionality become programmable logic circuits that also known as "FPGA cells". In these logic circuits are controlled, for example, from this called "SRAN cells" or "flash cells", in which the Program is stored, such as this in WO 99/34515 A1 is described.

These so-called "flash cells" require operation in Comparison to a logic circuit especially for descriptive purposes a much higher operating voltage. This leads to the integration of both circuit parts on one Chip to raise especially with increasing miniaturization problems with the separation of the high programming chip voltage for the memory cell from the low operating voltage the logic circuit. The below in particular fit different breakdown voltages of the gate Oxides, the usual field effect transistors together. If the gate oxide of the field effect transistors of the Lo The gik circuit is adapted to that of the flash memory cell the overall arrangement is operable, the operating property however, are deteriorating.

The invention is therefore based on the object, an inte grated logic circuit to provide in the simple with with the same operating characteristics safety is retained, even if circuit elements for different operating voltages are designed.  

This object is achieved with the in claim 1 specified measures solved. The fact that between the Memory cell output of the memory cell and the input of the Logic switching element a matching circuit is provided the logic circuit element and the memory cell with under different operating voltages can be operated and a separation the operating voltages are easily possible.

Further advantageous embodiments of the invention are in specified in the subclaims. Disconnecting the company chip is particularly advantageously ensured that the memory cell with a first operating voltage, the Logic circuit element with a second operating voltage and the adapter circuit with a third operating voltage be are drivable, the first operating voltage being greater than the third operating voltage and the third operating voltage is greater than the second operating voltage.

The invention is particularly useful when using a flash Memory cell advantageously usable as a memory cell.

The invention is described below with reference to the figure using an exemplary embodiment. The figure shows the basic structure of the integrated logic circuit according to the invention. A logic circuit element LS is provided, which in the exemplary embodiment shown is implemented by a field effect transistor T1. This applies to a third operating voltage, which is composed of the voltage potentials SP3 and SP4. At the gate circuit of the transistor T1, which represents the input 4 of the logic scarf element LS, the output of an inverter stage IS is connected. The inverter stage IS consists of the two field effect transistors T3 and T4 connected in series, the common output node of the two transistors T3 and T4 representing output 3 of the inverter stage IS. The inverter stage IS is operated at a third operating voltage, which is composed of the voltage potential SP5 and SP6.

The two gate connections of the transistors T3 and T4 are connected to one another and represent the input 2 of the inverter stage IS. The input 2 of the inverter stage IS is connected to the output 1 of a conventional flash memory cell FS. The flash memory cell FS is in turn connected to a first operating voltage, which is composed of the potentials SP1 and SP2.

The flash memory cell is now dimensioned for the high voltage required for this. Correspondingly, the inverter stage is dimensioned for the third operating voltage and laid out in such a way that the signal coming from the flash memory cell FS via output 1 is received and implemented by input 2 of the inverter stage IS without damaging the two transistors T3 and T4 , Accordingly, the inverter stage is dimensioned such that the inverted signal of the flash memory cell FS present at the output 3 can be fed to the input 4 of the logic switching element LS without damaging the transistor T1.

With the arrangement shown is a safe programming operation of the flash memory cell FS possible without doing that Logic switching element LS at risk, the same time, ange fits the second operating voltage with unrestricted loading drive properties is operable.

With the invention described above, in particular Programming of FPGA cells is extremely applicable. there the disadvantage is that for the additional inverter stage Chip area of the integrated circuit is required, thereby canceled that the operating characteristics of the FPGA cell he persists and not through technological adjustments the flash memory cell, d. H. through the use of tension-free ster and therefore unsuitable slow transistors in their Operating characteristics deteriorated.  

LIST OF REFERENCE NUMBERS

FS memory cell
IS adapter circuit, inverter circuit
LS logic switching element
SP1, SP2 first operating voltage
SP3, SP4 second operating voltage
SP5, SP6 third operating voltage

1

Memory cell output

2

Inverter circuit input

3

Output inverter circuit

4

Input logic switching element
T1 field effect transistor

Claims (6)

1. Integrated logic circuit with at least one logic scarf element (LS), the input ( 4 ) of which an output signal of a memory cell (FS) can be guided from a memory cell output ( 1 ), characterized in that between the memory cell output ( 1 ) of the memory cell (FS) and the input ( 4 ) of the logic switching element (LS) a matching circuit (IS) is arranged. 2. Integrated logic circuit according to claim 1, characterized in that the memory cell (FS) with a first operating voltage (SP1, SP2) and the logic switching element (LS) with a second Operating voltage (SP3, SP4) is operable, and the adaptation circuit (IS) with a third operating voltage (SP5, SP6) is operable. 3. Integrated circuit arrangement according to claim 2, characterized in that the first operating voltage is greater than the third operating voltage and the third operating voltage is greater than that second operating voltage is. 4. Integrated logic circuit according to claim 1, 2 or 3, characterized in that the memory cell (FS) is a flash memory cell. 5. Integrated logic circuit according to claim 1, 2, 3, 4 or 5, characterized in that the logic switching element (LS) a field effect transistor (T1) is. 6. Integrated logic circuit according to claim 1, 2, 3, 4 or 5,  characterized in that the circuit (IS) is an inverter circuit.