543292 五、發明說明（1) [發明領域] 本發明係關於 (output buffer)， 及方法。 :指?二了::二 [發明背景] 現今的積體電路設計愈來愈緊密，因 求也愈來愈嚴格，然而提升積體電路之卫 f的要 訊之間很難取得平衡。以輸出緩衝電路為例肐二=雜 缓衝電路時，ϋ常會針對負載的大小來定出上升：間：： 降時間的規格；當輸出缓衝電路必須推動較大的負載^卜 為了確保上升時間與下降時間不致太長，二貝把輸出：衝 電路的面積加大以提高推動能力，然而大面積的輸出緩衝 電路通常會產生較大的雜訊，進而會影響整個晶片的穩定 度，因此發展出一種低雜訊的輸出緩衝電路是非常必要 的。 由於電晶體由關閉（OFF)至導通（ON)的轉換瞬間會有 電流導通，故在電晶體轉換瞬間會有很大的電流變化率 (即△ 1/ △ t报大）。根據電感效應：感應電壓差為引線 電感值與電流變化率的乘積（即VL = L dl/ dt ;其中VL為 烕應電壓差，L為引線電感值，約10 nH ，dl/ dt則為電 流變化率）。因此，電晶體在狀態轉換瞬間會在接地端感543292 V. Description of the invention (1) [Field of the invention] The present invention relates to (output buffer) and method. : Refer to the second :: II [Background of the Invention] Today's integrated circuit designs are becoming more and more tight, and the requirements are becoming more and more stringent. However, it is difficult to achieve a balance between the requirements for improving the f of the integrated circuit. Take the output buffer circuit as an example. When the second buffer circuit is miscellaneous, the rise time is usually determined according to the size of the load: time: the fall time specification; when the output buffer circuit must push a larger load, in order to ensure an increase The time and the fall time are not too long. Erbei increased the area of the output: punch circuit to improve the driving ability. However, the large area of the output buffer circuit usually generates large noise, which will affect the stability of the entire chip. It is necessary to develop a low noise output buffer circuit. Because the transistor will be turned on instantly when the transistor is switched from OFF to ON, there will be a large current change rate at the moment when the transistor is switched (that is, △ 1 / △ t is reported as large). According to the inductance effect: the induced voltage difference is the product of the lead inductance value and the current change rate (that is, VL = L dl / dt; where VL is the response voltage difference, L is the lead inductance value, about 10 nH, and dl / dt is the current Rate of change). Therefore, the transistor will sense the ground at the moment of state transition.
543292 五、發明說明（2) 應一個瞬間電壓差（VL)，該瞬間電壓差係正比於電流變 化率’且可感應至晶片其它部份，此即為雜訊的來源之 圖一為根據先前技藝配置在一積體電路内之既有輸出 緩衝電路，在積體電路内產生的輸入信號IN經由一由p M 0S 電晶體Ml與NMOS電晶體M2所組成的CMOS反相器緩衝後，供 應到NPN電晶體Q1的基極，該NPN電晶體Q1的集極接一電阻 R2連接到電源供應電壓VCC，而該NPN電晶體Q1的射極一方 面接一電阻R1連接到接地端，另一方面連接到NPN電晶體 Q2的基極，該NPN電晶體Q2的射極直接連到接地端，而其 集極則連接到一輸出端子〇 U T，且由此端子連接到外a ^ 載。 1 圖二是圖一輸出緩衝電路之輸出電流曲線，該圖《、 OrCAD PSpice模擬取得之曲線圖。當輸入信號IN由高=， 下降至低位準後，由於NPN電晶體Q2是在主動區内工^作立準 因此流經該NPN電晶體Q2的集極電流（即輸出電流）約二 於NPN電晶體Q1的基極電流和hFE ( hFE代表NPNt晶體等 流放大因數）平方之乘積，此過大的輸出電流將會造$電 地位準之浮動，並從而產生雜訊，而這些都是先^ ^接 待克服的問題。 晏有 有鑑於此’本發明之主要目的係提出一種新架構 出緩衝電路及方法’其不但能降低輸出緩衝電路上升輸 流經之輸出電流的大小，並且也能降低輪出緩衝電路，所 543292 五、發明說明（3) 時所流經輸出電流的電流變化率，同時亦能藉此而有效防 止接地電壓位準浮動和雜訊的發生。 [發明簡述] 根據上述之目的，本發明提出一種新架構之輸出緩衝 電路及方法，該輸出緩衝電路係包括：一 c M 〇 s反相器，其 係由第一PMOS電晶體Ml以及第—NMOS電晶體M2所組成，並 用以將一輸入信號I N反相；一第—NPN電晶體Q1，其基極 端連接至該CMOS反相器之輸出，並具有一集極端以及一射 極端；一第二NPN電晶體Q2，其基極端連接至該第—NPN電 晶體Q1之射極端，其集極端連接至輸出端子〇υτ，而其射 極端則接地；以及一控制電路1，其係連接於CM〇s反相器 之輸出與接地之間。該控制電路1更包括··一第二腫〇3電 晶體M3，其沒極與閘極連接在一起，並共同連接至該CM〇s 反相器之輸出；一第三NM0S電晶體M4，其汲極連接至第二 NM0S電晶體M3之源極，而其源極則接地；以及一延遲電路 11 ’其連接於輸入信號IN與第三NM0S電晶體“之閘極之 間。 而該降低輸出緩衝電路雜訊的方法之技術特徵為：當 輸入信號IN由高位準變為低位準，且在CM〇s反相，器中之第 -PM0S電晶體Ml導通時，該控制電路1能導通一段預定之 時間，俾藉此以吸走第—PM〇s電晶體Ml之部份汲極電流， 並使得第一 NPN電晶體qi的基極電流減少，從而減少瞬間 543292 五、發明說明（4) 流經第二NPN電晶體Q2之集極電流（即輪出電流）。 [較佳實施例之說明] 本發明所提出輸出緩衝電路之較佳實施例顯示於第三 圖中，其包括：一 CMOS反相器，其係由第—PMOS電晶體Ml 以及第一NM0S電晶體M2所組成，並用以將一輸入信號IN反 相；一第一 NPN電晶體Q1，其基極端連接至該CMOS反相器 之輸出，並具有一集極端以及一射極端；一第二NPN電晶 體Q2，其基極端連接至該第一NPN電晶體qi之射極端，其 集極端連接至輸出端子0 U T，而其射極端則接地；一第一 電阻R1’連接於該第一NP N電晶體Q1之射極端與接地之 間；一第二電阻R2，連接於該第一 NPN電晶體Q1之集極端 與電源供應電壓VCC之間；以及一控制電路1，其係連接於 CMOS反相器之輸出與接地之間，且在CMOS反相器中之第— PM0S電晶體Ml導通時，該控制電路1能導通一段預定之時 間，俾藉此以吸走第一PM0S電晶體Ml之部份汲極電流，並 因而降低第二NPN電晶體Q2於轉換瞬間之集極電流大小及 其電流變化率。 該控制電路1更包括：一第二NM0S電晶體M3，其汲極 與閘極連接在一起，並共同連接至該CM〇S反相器之輸出； 一第三NM0S電晶體M4，其汲極連接至第二NM0S電晶體们之 源極’而其源極則接地；以及一延遲電路1丨，其連接於輸 入信號I N與第三NM0S電晶體M4之閘極之間，且於此較佳實543292 V. Description of the invention (2) There should be an instantaneous voltage difference (VL), which is proportional to the current change rate and can be sensed to other parts of the chip. This is the source of the noise. Figure 1 is based on the previous The technology is equipped with an existing output buffer circuit in a integrated circuit. The input signal IN generated in the integrated circuit is buffered by a CMOS inverter composed of p M 0S transistor M1 and NMOS transistor M2, and then supplied. To the base of the NPN transistor Q1, the collector of the NPN transistor Q1 is connected to a resistor R2 to the power supply voltage VCC, and the emitter of the NPN transistor Q1 is connected to a resistor R1 to the ground and the other The aspect is connected to the base of the NPN transistor Q2, the emitter of the NPN transistor Q2 is directly connected to the ground, and its collector is connected to an output terminal OUT, and thus the terminal is connected to the external load. 1 Figure 2 is the output current curve of the output buffer circuit of Figure 1, which is a curve obtained by OrCAD PSpice simulation. When the input signal IN goes from high = to low level, since the NPN transistor Q2 operates in the active region, the collector current (ie, output current) flowing through the NPN transistor Q2 is about two times that of NPN. The product of the base current of transistor Q1 and the square of hFE (hFE stands for equal current amplification factor of NPNt crystal). This excessive output current will cause the electrical level to float and generate noise. These are the first ^ ^ Reception overcoming problems. In view of this, Yan Youyou's "the main purpose of the present invention is to propose a new structure of a buffer circuit and method", which can not only reduce the output current flowing through the output buffer circuit ascending input, but also reduce the output buffer circuit, so 543292 V. Description of the invention (3) The current change rate of the output current flowing in (3) can also effectively prevent the ground voltage level from floating and noise from occurring at the same time. [Brief description of the invention] According to the above purpose, the present invention proposes a new architecture output buffer circuit and method. The output buffer circuit includes: a c M 0s inverter, which is composed of a first PMOS transistor M1 and a first -An NMOS transistor M2, which is used to invert an input signal IN; a first-NPN transistor Q1, whose base terminal is connected to the output of the CMOS inverter and has a set terminal and an emitter terminal; The second NPN transistor Q2 has a base terminal connected to the emitter terminal of the first NPN transistor Q1, a collector terminal connected to the output terminal υτ and its emitter terminal to ground; and a control circuit 1, which is connected to Between the output of CMos inverter and ground. The control circuit 1 further includes a second swollen transistor M3, whose pole and gate are connected together and connected to the output of the CMOS inverter; a third NMOS transistor M4, Its drain is connected to the source of the second NMOS transistor M3, and its source is grounded; and a delay circuit 11 'is connected between the input signal IN and the gate of the third NMOS transistor. " The technical characteristics of the method of outputting noise from the buffer circuit are: when the input signal IN changes from a high level to a low level, and is inverted at CM0s, and the -PM0S transistor M1 in the device is turned on, the control circuit 1 can be turned on. For a predetermined period of time, I will use this to draw away part of the drain current of the -PM0s transistor M1, and reduce the base current of the first NPN transistor qi, thereby reducing the instant 543292 V. Description of the invention (4 ) The collector current (ie the wheel current) flowing through the second NPN transistor Q2. [Explanation of the preferred embodiment] The preferred embodiment of the output buffer circuit proposed by the present invention is shown in the third figure, which includes: A CMOS inverter composed of a first PMOS transistor M1 and a first NMOS transistor It consists of a body M2 and is used to invert an input signal IN; a first NPN transistor Q1 whose base terminal is connected to the output of the CMOS inverter and has a set terminal and an emitter terminal; a second NPN Transistor Q2, whose base terminal is connected to the emitter terminal of the first NPN transistor qi, whose collector terminal is connected to the output terminal 0 UT, and its emitter terminal is grounded; a first resistor R1 ′ is connected to the first NP N Between the emitter terminal of transistor Q1 and ground; a second resistor R2 connected between the collector terminal of the first NPN transistor Q1 and the power supply voltage VCC; and a control circuit 1 connected to the CMOS inverter Between the output of the inverter and the ground, and when the first PM0S transistor M1 in the CMOS inverter is turned on, the control circuit 1 can be turned on for a predetermined time, thereby taking away the part of the first PM0S transistor Ml. The control circuit 1 further includes a second NMOS transistor M3, the drain of which is connected to the gate. Together and commonly connected to the output of the CMOS inverter A third NMOS transistor M4 whose drain is connected to the source of the second NMOS transistor and its source is grounded; and a delay circuit 1 丨 which is connected to the input signal IN and the third NMOS transistor Between the gates of M4, and better here
第8頁 ^S292 、發明說明（5) 施 電 選 ::反由4個反相器所組成。但組成延遲 擇其數目並不局限於4個，可視電路之需求， 晶 反 體Ml關^路^當輸入信號1Ν在高位準時，第—PM〇S電 f Ml關閉，而第—NM〇s電晶體 =Page 8 ^ S292, description of the invention (5) Power selection :: Inverter is composed of 4 inverters. However, the number of component delays is not limited to four. Depending on the requirements of the circuit, the transistor M1 is turned off. When the input signal 1N is at a high level, the -PM0S power f M1 is turned off, and the -NM0s Transistor =
相器之輸出拉低至接舳雷仞 等逋於疋』將该CMOS NM0S# « ^ mq战接地電位，此接地電位遂使得第二 MUS電日日體M3、第—NPN電晶體Q 一 ^ ^ 關aa壯能丨本^ 及第一評晶體Q2呈 :閉狀“此時第三酬鴻晶體二呈 由此可4 導通狀& )因此輪出端呈高位準狀態。 由此可知’當輸入信號〗N呈高位 闰-斛+从干 m - ^ ^ ^ 1卡時，圖二所不的電路和 Ώ 所不的傳統電路動作都相同，玟氽θ抓舛靳結仏山/ 衝電路時所必要滿足的條件之_ Λ也疋^十新穎輸出緩 曰體ΠίΙΝ由高位準變為低位準•，第二_電 :二Q導疋在主動區内操作。如果在這時候第-s電晶體Ml之沒極電流，直接成為第_ NPN電晶體_ 基極電流，則第_ NPN電晶體Q1的射極電流扣抵流過第一 電阻R1的微小電流後，亦直接成為第二NpN電晶體Q2的基 極電流，於是如傳統電路般，第二NM電晶體Q2的集極^ 流（即輸出電流）將會約略等於第—NPN電晶體Q1的基極電 流和hFE平方的乘積，此過大的輸出電流將會造成接地位 準之浮動，並從而產生雜訊。 然而，在本發明中，當輸入信號I N由高位準變為低位 準時，CMOS反相器中之第一 PM0S電晶體Ml導通，而第— NM0S電晶體M2關閉，並使得第一NPN電晶體Q1的基極電壓The output of the phaser is pulled down to connect to 舳 雷 仞 等 逋 逋 ”This CMOS NM0S #« ^ mq and ground potential, this ground potential then makes the second MUS electric solar body M3, the first-NPN transistor Q a ^ ^ Guan aa Zhuangneng 丨 This ^ and the first evaluation of crystal Q2 are: closed. "At this time, the third remuneration of the second crystal is 4 can be turned on &) Therefore, the wheel exit is at a high level. From this we can know that ' When the input signal N is high 闰-D + + m-^ ^ ^ 1 card, the circuit shown in Figure 2 and the traditional circuit shown in Figure 2 have the same actions. The conditions that must be met when _ Λ 也 疋 ^ 10 novel output slow body body ΠίΙΝ changed from high level to low level •, the second _ electric: two Q guides operate in the active area. If at this time the -s The non-polar current of the transistor M1 directly becomes the __NPN transistor_ base current, and the emitter current of the __NPN transistor Q1 deducts the small current flowing through the first resistor R1 and also directly becomes the second NpN. The base current of transistor Q2 is like a conventional circuit, so the collector current (ie output current) of the second NM transistor Q2 will be approximately equal to the -N The product of the base current of the PN transistor Q1 and the square of hFE. This excessive output current will cause the ground level to float and cause noise. However, in the present invention, when the input signal IN changes from a high level to a high level, At the low level, the first PM0S transistor M1 in the CMOS inverter is turned on, and the —NM0S transistor M2 is turned off, and the base voltage of the first NPN transistor Q1 is turned on.
543292 五、發明說明（6) 開始由低位準變兔古 閉狀態轉變為ί ί : ί 於是第二NM〇s電晶體M3將由關 三NMOS電晶體，值此時由於延遲電路之作用’第 體Μ 4仍會導通—段车間德才合關閉，於兮筮一 NMOS電晶體M4 W間後才曰關㈣弟二543292 V. Description of the invention (6) Began to change from a low-level quasi-rabbit rabbit to a closed state ί: ί So the second NM〇s transistor M3 will be turned off by the third NMOS transistor, at this time due to the role of the delay circuit Μ 4 will still be on-Duancai Decaihe shuts down, and Yu Xiyi, NMOS transistor M4 W, said it later
電晶體Ml之沒極^ ΐ通^怒期間，可吸走部份的第一 PM〇S 流將減少，從， 第一NPN電晶體Q1的基極電 晶體Q2的集極；；”:：第〜刪晶體_及第二NPN電 電流（即輸出電’流過第二NPN電晶體Q2之集極 NPN電晶體Q2< 上升變得較適中，且流過該第二 ^ ^ ΛV! ^ ^ ^ ^ ^ ^ ^ 圖四是太Ϊ電路輸出電流的電流最大值還小。 線亦是由〇rCA二較佳^施例電路之輸出電流曲線，該曲 本發明所提出 而得.由該曲線的結果，：曰實 騁Ω分隹k㊉輸出緩衝電路確實可使流過第二NPN電晶 NPN電晶體流的電流上升率變得較緩和，且流過該第二 還小。Μ _之集極電流的電流最大值變得比先前技藝者 么宇 F 戶斤、十、 #添二# ^ ΐ %本發明於CM0S反相器之輸出與接地之間藉 G之ΐ =:丄的，路架構’確實可有效缓和輸出 量，故本發明4 ί i 可有效抑制輸出電流之過電流 的發生。 了有效防止接地電壓位準浮動以及避免雜訊 [發明功效]During the period of the transistor M1, the first PMOS current that can be sucked away will be reduced, from the collector of the base transistor Q2 of the first NPN transistor Q1; ":: The first ~ deleted crystal_ and the second NPN electric current (that is, the output electric current flows through the collector NPN transistor Q2 of the second NPN transistor Q2 < rise becomes more moderate, and flows through the second ^ ^ V! ^ ^ ^ ^ ^ ^ ^ Figure 4 shows that the maximum current value of the output current of the Taiyuan circuit is still small. The line is also the output current curve of the circuit of the second preferred embodiment of 0rCA, which is derived from the present invention. From this curve As a result, the actual 骋 Ω 骋 k 隹 output buffer circuit can indeed make the current rise rate of the current flowing through the second NPN transistor NPN transistor to be relatively gentle, and the second through the second NPN transistor is small. M _ 集集The maximum current value of the polar current becomes larger than that of the previous artist Mo Yu F 斤, 十, # 添 二 # ^ 本% The present invention borrows G between the output of the CM0S inverter and the ground 丄 =: ，, the way The 'framework' can indeed effectively mitigate the output, so the invention 4 ί i can effectively suppress the occurrence of overcurrent in the output current. It effectively prevents the ground voltage level from floating. And to avoid noise [Effect invention]
第10頁 五、發明說明^ ' --〜---一 較於月所提出之具低雜訊之輸出緩衝電路及方法，相 技藝，具有如下優點： 電路結構簡單：本發明所提出之輸出緩衝電路，僅 糸在習知輸出緩衝電路之CM〇s反相器的輸出與接地 之間’增添一含有用以提供一預定延遲時間之延遲 電路U的^制電路i，因此電路結構簡單； ^雜訊及高穩定度：由於本發明於CMOS反相器中之 弟二PM0S電晶體Ml導通時，控制電路1能導通一段 預义之時間，因此可吸走第一PM0S電晶體Ml之部份 〆極電流’並使得第—NPN電晶體Q1的基極電流滅 ^ 從而減少瞬間流經第二NPN電晶體Q2之集極電 即輸出電流），結果，輸出電流的電流變化率變 得較緩和，並且輸出電流的最大值變得較小，故’ 不但可有效抑制接地端所感應之瞬間電位差，旅且 可避免接地電壓位準的浮動以及雜訊的發生，同時 亦可提升整個晶片之穩定度。 以上所揭示者，乃較佳實施例之展示，舉凡局部之變 更或修飾而源於本案之技術思想，而為熟習該項技藝之人 士所易於推知者，俱不脫本案之專權範疇。 細上所陳’本案無論就目的、手段或功效，在在顯禾 符合發明之專利要件，祈早日賜予專利，俾嘉惠社會，實 感德便。 543292 五、發明說明（8) 1111111 第12頁 543292 圖式簡單說明 第一圖係顯示習知輸出緩衝電路之電路圖； 第二圖係習知輸出緩衝電路之Or CAD PSp ice模擬取得之 輸出電流曲線圖； 第三圖係顯示本發明實施例之輸出緩衝電路的電路圖； 第四圖係本發明輸出緩衝電路之OrCAD PSpice模擬取得 之輸出電流曲線圖。 [元件符號說明] VCC 電源 Ml 第一 M2 第一 M3 第二 M4 第三 R1 第一 R2 第二 Q1 第一 Q2 第二 OUT 輸出 1 控制 11 延遲 Ic(Q2) 第二 供應電壓 PM0S電晶體 NM0S電晶體 NM0S電晶體 NM0S電晶體 電阻器 電阻器 NPN電晶體 NPN電晶體 端子 電路 電路 NPN電晶體之集極 電流（即輸出電流）Page 10 V. Description of the invention ^ '-~ --- Compared with the monthly output buffer circuit and method with low noise, the phase technology has the following advantages: Simple circuit structure: the output proposed by the present invention The buffer circuit merely adds a control circuit i containing a delay circuit U for providing a predetermined delay time between the output of the CMOS inverter of the conventional output buffer circuit and ground, so the circuit structure is simple; ^ Noise and high stability: Since the second PM0S transistor M1 in the CMOS inverter of the present invention is turned on, the control circuit 1 can be turned on for a predetermined time, so the part of the first PM0S transistor Ml can be sucked away. This reduces the base current of the first NPN transistor Q1 ^, thereby reducing the instantaneous current flowing through the collector of the second NPN transistor Q2 (ie, the output current). As a result, the current change rate of the output current becomes smaller than Mitigation, and the maximum value of the output current becomes smaller, so 'not only can effectively suppress the instantaneous potential difference induced by the ground terminal, but also can avoid the floating of the ground voltage level and the occurrence of noise, and can also improve the overall chip. stability. What has been disclosed above is a demonstration of the preferred embodiment. All local changes or modifications are derived from the technical ideas of the case, and those who are familiar with the technology are easy to infer, and they do not depart from the exclusive scope of the case. As mentioned in detail, this case, no matter in terms of purpose, means or effect, meets the patent requirements of the invention in Xianhe, and hopes to grant the patent at an early date, so as to benefit the society and feel its virtue. 543292 V. Description of the invention (8) 1111111 Page 12 543292 The diagram is briefly explained. The first diagram is a circuit diagram showing a conventional output buffer circuit. The second diagram is an output current curve obtained by Or CAD PSp ice simulation of a conventional output buffer circuit. The third diagram is a circuit diagram of an output buffer circuit according to an embodiment of the present invention. The fourth diagram is an output current curve obtained by OrCAD PSpice simulation of the output buffer circuit of the present invention. [Description of component symbols] VCC power supply M1 first M2 first M3 second M4 third R1 first R2 second Q1 first Q2 second OUT output 1 control 11 delay Ic (Q2) second supply voltage PM0S transistor NM0S electricity Crystal NM0S transistor NM0S transistor resistor resistor NPN transistor NPN transistor terminal circuit circuit collector current of NPN transistor (ie output current)
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