TW543194B - Structure of a flash memory device and fabrication method of the same - Google Patents

Abstract

A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.

Description

543194

9133twf.ptd Page 5 543194 V. Description of the Invention (2) The 128 layer. The deep n-type well region 102 is located in the p-type substrate 100. The stacked gate structure 106 is located on a p-type substrate 100. The source region 丨 and the drain region 110 are located in the p-type substrate 100 on both sides of the stacked gate structure 106. The partition wall 112 is located on the side wall of the stacked gate structure 106. The p-type well region 104 is located in the deep n-type well region 102, and extends from the drain region 110 to below the stacked gate structure 106. The inner dielectric layer 114 is located on the p-type substrate 100. The contact window 116 passes through the inner dielectric layer 114 and the p-type substrate 100 to short-circuit the drain region 110 and the p-type well region 104. The conductive line 118 is located on the inner dielectric layer 114 and is electrically connected to the contact window 116. / In the manufacturing process of the flash memory shown in FIG. 1 above, the formation step of the p-type well region 104 is formed on the entire P-type substrate 100 after the stacked gate structure is formed. Layer of mask layer (not shown), and the mask layer exposes a region intended to form a drain region. Then, an inclined angle (0 ° to 180 °) implantation step is performed, and the stacked gate structure 106 and the cover curtain layer are = curtain 2 on the p-type substrate near the drain region on the side of the stack gate structure 106 The dopant is implanted in the ice 2 well-type area 100 of 100, and then a metamorphic displacement is performed under the formula ΓΓΓ to extend the 13-type well area 104 to the stacked gate structure. The gate surname Mona remained on the side wall of the floating gate, and the combination of the gate dielectric layer was removed in order to stop the gate dielectric layer completely. &Amp; & When the field oxide layer is engraved with excessive money to form a trench, the P-type well region 104 covered by the interlayer electrode is formed at an inclination angle away from ff, and the above steps are used to form electron volts to 50 仟 electron volts) 仟 丨4 dendrites will penetrate the field oxygen

^ 133twf.ptd Page 6 V. Description of the invention (3) Leakage current on the drain side due to the formation layer / membrane cell, causing isolation failure between the bit line (Bit line) and the bit line problem. In fact, in order to form a local p-type well (Local pwell), the subsequent doping driving process is performed at a temperature of 900 t in an oxygen-containing environment, which will cause floating Place the gate 丨 2 2 tunneling oxide layer at the edge 丨 2 〇 thicken, the thickness of the gate dielectric layer 124 (silicon oxide / silicon nitride / silicon oxide) at the edges becomes thicker, and the driving diffusion of the P-type well area The length is difficult to control, which causes problems such as poor component performance and reduced yield. In addition, the source regions of the aforementioned flash memory are connected together using deep n-type well regions to form source lines. Due to the high resistance of the deep 11 well area, which will affect the element operation rate, in order to improve the element operation rate, Xi Chi's: every 16 memory cells in the active area (that is, 16 bit linear mPlckup) to reduce ㉝ The cell array I of the well area (source line) is produced in the active area and forming the source line connection line will reduce the ratio of the memory car, but cannot increase the degree of component integration. The disc P-type beautiful outer sole 2 forms the contact window 116. The temple requires money to etch the inner dielectric layer 114. The contact window earth door-oral to form a deep production through the inner dielectric layer 1 M and the drain region 110. # 贝 (silicon oxide and silicon), so it is necessary to control the process of the contact window opening section because of the difficulty of the ::: process. In addition, the contact windows and the contact windows of the peripheral circuit area must be separated in the future. Therefore, the complexity of the subsequent process will be increased. One of the components of the device structure and the dragon == is to provide a flash memory structure and a manufacturing method thereof, without the need to form an additional source line connection 543194. 5. Description of the invention (4), and can increase the reliability of the component, 醢2. You have to solve the problem of leakage current between adjacent bit lines, and raise the problem of connection of memory elements + line flow 'and improve the accumulated sound of memory elements β 1 ΐ: Another purpose The point is to provide-the structure of the flash memory device can reduce the number of process steps, increase the process margin, and save the cost and time of manufacturing. In view of this, the present invention provides a shirt M α _ This flash memory device has a structure having a memory element, which is a stack gate disposed on a first conductive substrate and a first conductive substrate in a first conductive substrate. The source region in the pole junction is located in the second room: the first: the conductive type substrate 1 drain region, and the second: the 3 type substrate in the stack gate is connected to the interface I of the first well region; The second well area is connected to the second electrical type second well area and the conditioning, and isolates the impurities of the trenches in the first conductive substrate = electrical contact, and fills the first conductive-conductive second well area. The electrode region is connected with the source region of the present invention called a contact window and is electrically short-circuited. The side wall of the trench and the bottom are replaced by ^ = placed in the substrate below the gap wall and connected to the well area for subsequent formation 'The charm region 3 is connected. This doped region can isolate the P-type connection. Moreover, the contact window does not short-circuit the source region and the P-type well region. Source line) connection can reduce the resistance value of the source line, no need for another 9133twf.ptd Page 8 543194 V. Invention (5) 2 ^ forming source line connecting lines on the active area, which can improve the collection of components. In addition, the present invention uses a trench to cut off the p-type well area between the source areas of two adjacent memory cells. Second, the implanted dopant will penetrate the field oxide layer // oxygen: r: thickened, so it can be maintained. Β $ $ W Tian & contact window system directly forms a conductive layer on the substrate, and then uses the back Etching process or chemical machine = bulk layer until the closed cap layer is exposed. As no time is needed =: electrical = P 孓 substrate to form a dielectric layer through the inner layer and / / port, so the margin of the contact window process can be improved The t-contact invention provides a flash memory cell according to the present invention, the following steps: providing a second conductive region of a second conductivity type and a stacked gate structure in order; a structure in the stack interpole; Formed in the substrate on both sides-the source region forms a gap wall on the side wall of the stacked gate structure. Then, a first patterned photoresist layer is formed on the two j and the first patterned sound is patterned with f one. Photoresist layer and having a spacer wall; No .: The second well region of the conductive type After the interface, move; "^" to form a second patterned photoresist layer on the substrate, and this second 1 133twf.ptd page 9 543194 5. Description of the invention (6) The patterned photoresist layer has% The substrate of the stack of spacers. The second patterned photoresist layer and the second conductive type are used as a mask, and the substrate for etching the source region has been implanted. Trench. Then, an ion-doped region is performed, and a dopant is implanted in the substrate of the heart wall and the bottom to form a -first-conductor layer 1C resist layer. Then, a gap on the substrate is removed. Eighty-one body layers fill the contact windows between the stacked gate structures and the first; the body [forms on the source region-the first-the middle-the contact window. The source region: the well region-the second conductor Layer, its second conductor layer to form one or two electrical contacts. Next, ® is connected to the first conductivity type 笫 _ | ®, and the second contact window forms an internal short-circuit connection to the drain region. After that, a wire is electrically connected to the substrate. The second contact window is formed on the inner dielectric layer. The present invention is based on the substrate of the Φ + polar region, so that the subsequent formation is connected. Area, and etch the junction of the well area and short-circuited to form a trench in a pattern that is only between the source regions of two adjacent memory cells.鈇 A makes the P-type well area process on the side wall of the trench and the bottom of the trench. I ion implantation is performed. 0: 1 A. A contact window (tungsten: polar line) is formed in the trench to connect the memory cells. Source area, so the resistance value of the line does not need to form a source line connection on the active area: 9133twf.ptd Page 10 543194

Moreover, the inclination angle of the source of the trench and the cell can be improved (0 step to form the edge ratio of the field oxidation line and the bit line structure. 0) the degree of integration of the device. A trench is formed in a deep n-type well to cut off the P-type well, so that the p-type well is only located between two adjacent areas. Because the P-type well of the present invention does not use the angle of inclination of 180 degrees from the conventional degree) ions The implantation step and the dopant drive it in. Therefore, the method of the present invention can avoid the problem that the implanted dopant layer will cause leakage current on the drain side of the memory cell, which will cause the isolation failure between the bits. An oxide will be formed on the stacked gates, which can maintain the performance and good quality of the memory cell element: =: forming a contact window · 'A layer is directly formed on the substrate and a V-body layer is formed, and then an etch-back process or chemical mechanical polishing is used. : Part of the conductor layer until the gate capping layer is exposed. Because it is engraved with the P-type substrate 'to form a contact opening in the inner dielectric layer and the drain region, the inner layer can increase the margin of the contact window process. In order to make the above-mentioned objects, features, and advantages of the present invention clearer and clearer, a special example is given, and in conjunction with the accompanying drawings, the detailed description of the symbols of the drawings: 100, 200, 300 : ρ-type bases 10 02, 202, 304: Deep η-type wells 104, 204, 306, 306a: ρ-type wells 1 06, 2 06, 31 8: Stacked gate structure 108, 208, 320, 320a : Source region 543194 V. Description of the invention (8) 110, 210, 322, 322a: Drain region 11 2, 2 1 2 a, 2 1 2 b, 3 2 4 ·· Partition walls 114, 218, 340: Inner layer Dielectric layers 116, 214, 216, 336, 338: Contact windows 118, 222, 344: # Line 120, 224: Tunneling oxide layers 122, 226Floating gate 1 2 4, 2 2 8: Gate dielectric Electrical layer 1 2 6, 2 3 0: Control gate 128, 232, 316: Gate top cover layer 2 2 0, 3 4 2 Plug 302 · Element isolation structure 308, 308a: Oxide layers 310, 310a, 314 : Conductor layer 312: Dielectric layers 326, 328: Patterned photoresist layer 330: Trenches 209, 332: Doped region embodiment Figure 2 illustrates the structure of the flash memory of the present invention. NOR gate type (Bi_) array flash memory For example, please refer to FIG. 2 of the flash memory of the present invention, I # I _ deep η-type well area 202, p-type well F9fU by P-type substrate 200, well 1 & 204, stacked gate structure 206, Source region

9133twf.ptd Page 12 543194 V. Description of the invention (9) 208, doped region 209, drain region 21, spacer 212a and spacer ϋ: contact window 214, contact window 216, inner dielectric layer 218 plug 220 = = ^ 222. Among them, the stacked gate structure 206 is formed by tunneling oxidation f f: / position gate 226, gate dielectric layer 228, control gate 130 and gate top layer 2 3 2. The P-type substrate 200 has a trench 234. The deep 11-type well area 202 is set on the mouth-shaped base 200. The partition wall 212a and the partition wall are disposed on the side wall of the stacked gate structure 206 in a convenient manner, and the partition wall 2123 is connected to the top of the trench 234. The source region 208 is disposed in the p-type substrate 2000 under the spacer 212a. The drain region is set to ^: in the p-type substrate 200 below the spacer 212b. The p-type well area 204 is disposed between the stacked gate structure 206 and the deep n-type well area 202, and the interface between the p-type well area 204 and the / n-type well area 202 is higher than the bottom of the trench 234 . The doped region 20g is disposed on the side wall and the bottom of the trench 234. This doped region 209 is connected to the source region 208 and isolates the P-type well region 204, so that the subsequently formed contact window 216 does not contact the p-type region. The well region 204 is short-circuited together, and the contact window 214 penetrates the drain region to connect the two wells 204 with each other by short-circuiting them. The contact window 216 fills the trench 234 in the P-type substrate and is in electrical contact with the source region 208. The inner layer; the electrical layer 218 is located on the p-type substrate 200. The plug 22 is disposed in the inner dielectric layer 218 and is in electrical contact with the contact window 214. The lead 222 is located on the inner dielectric layer 218 and is electrically connected to the plug 220. In the above embodiment of the present invention, the source region 2008 is disposed in the substrate 2000 below the gap wall 2 12a, and is connected to the doped region 209 on the sidewall and the bottom of the trench 234. This doped region 2 09 can isolate the p-type well region 204, so that the subsequently formed contact window 216 will not short-circuit the source region 20 and the p-type well region 204. Page 13 543194 V. Invention Instructions (ίο) together. In addition, the contact window 216 (tungsten metal source line) is used to memorize the source region m of the cell, so the power of the source line can be reduced = i = ϊ: the source line connection line is formed on the active area, which can improve the In addition, the trench 234 is used to cut off the p-well region 204, so that 204 is located only between the source regions 208 of two adjacent memory cells. Therefore, this method can prevent the implanted dopant from penetrating the field oxide layer and causing leakage current on the drain side of the cell, which causes the isolation failure between the bit line and the bit line. An oxide is formed on the edge of the stacked gate structure, which can maintain the memory cell device performance and yield. In addition, the contact window 214 and the contact window 216 form a conductor layer directly on the substrate 20 (), and then use an etch-back process or chemical mechanical polishing to remove part of the conductor layer until the gate cap layer is exposed. Since the inner dielectric layer and the P-type substrate are not required to be formed to form a contact window opening penetrating the inner dielectric layer and the drain region, the margin of the contact window process can be improved. Next, please refer to FIG. 3A to FIG. 3G for a perspective view of a manufacturing process of a flash memory of each preferred embodiment of the present invention, which is used to describe the manufacture of the flash memory of the present invention. method. First, please refer to FIG. 3A to provide a p-type substrate 300. This? The element-based substrate 300 has formed an element isolation structure 302, and the element isolation structure 300 is arranged in a zigzag shape and is used to define an active area. A method for forming the element isolation structure 302 is, for example, a local oxidation method (LOCOS) or a shallow trench isolation method (STI). Next, a deep n-type well region 304 is formed in the p-type substrate 300, and within this deep n-type well region 304 c) l33twf.ptd page 14 543194 Description of the invention (11) A P-type well region 3 06 is formed. The method of forming the p-type well region 306 is, for example, an ionization method, the implanted dopant is, for example, boron ion, and the implantation energy is about 50 Å electron volts. After that, an oxide layer 208 is formed on the surface of the p-type substrate 300 as a tunneling oxide layer. The method for forming the oxide layer 308 is, for example, 90 ° to 100 ° left. ° Oxidized by thermal oxidation for 30 days, the p-type well area 3 0 6 will be doped with drive-in.

Next, referring to FIG. 3B, a conductor layer (not shown) is formed on the oxide layer 308. The material is, for example, doped polycrystalline silicon. The method for forming the conductor layer is, for example, chemical vapor deposition. After an undoped polycrystalline silicon layer is formed, an ion implantation step is performed to form the conductive layer, and the thickness of the conductive layer is about 8000 angstroms. This conductor layer is then patterned so that it exposes the element isolation and the surface of 302 is formed to form a conductor layer 31 as shown in the figure.

^ Please refer to Figure 3C. A dielectric layer (not shown), a conductor layer (not shown), and a cap layer (not shown) are sequentially formed on the substrate 300. The cap layer and the conductor layer are patterned by using a mask. It is used to define the gate cap layer 3 1 6 and the conductor layer 3 丨 4 for controlling the gate. While defining the conductor layer 314, continue to define the dielectric layer and the conductor layer 310 with the same mask. ^ And the oxide layer 308 to form the dielectric layer 312 and the < body layer 31oa and the oxide layer 308a respectively, wherein the conductor layer 31oa is used as a floating gate. ^ That is, the flash memory The stacked gate structure 318 is composed of a gate top layer 316, a conductor layer (control gate) 314, a dielectric layer 312, a conductor layer (floating gate) 310a, and an oxide layer 308a (tunneling oxide layer) as shown in the figure. Stacked structure

543194 V. Description of the invention (12) The material of the dielectric layer 3 1 2 is, for example, oxide # and its thickness is, for example, about 60 angstroms / 70 angstroms / 60 angstroms = silicon / silicon oxide, and the method is, for example, low-pressure chemical vapor deposition. The material for forming the second dielectric layer 312 may also be a material of the conductive layer 314 of the dielectric layer 312, such as a stone oxide layer, a stone oxide / nitrogen VV /, and the like. If it is about 2000 angstroms, the formation method of the conductor layer 314 is ‘two’ f, and its thickness (In-Si tu) is used for doping ions. The material of the sub-emulsion deposition method to form the gate capping layer 316 is, for example, nitrided. The thickness is, for example, about 1 500 angstroms, the gate capping layer / siliconization, and its vapor deposition method is used. The method of θ ^ formation is, for example, a line map, with stacked gate structure 318 as a military curtain, implanted with dopants, 擗 a, and shielded the substrate 300 on both sides for seven days, forming a source region 320 and a drain Area 322. Implanted implants such as 疋 n + type dopants, including arsenic ions or implanted ^ Exemplary structure 318 side walls to form gaps ^ 2 'in the heap gate nitride ㈡ :: absolutely = (not shown) 'The material of this insulating layer is, for example, a layer, so that a part of the insulation is removed by an anisotropic etching method afterwards, and a side wall of the Fengfeng gate structure 318 forms a gap 324. After the photo-chemical parameters are formed, a-layer pattern is formed on the entire substrate 300, and the patterned photo-resist layer 3 2 6 is exposed to expose the drain region 3 2 2. Ran 324: an etching step, using the patterned photoresist layer 326 and the well structure with a gap wall 3 0 ^ gate structure 3 1 8 as a mask, etching the substrate 3 0 until the P-type surface is exposed to form a drain region 3 2 2 a, where the drain region 3 2 2 a is 9l33twf.pt (j page 16 543194 V. Description of the invention (13) Wall: 24, so the contact window formed later will run through the drain region /, P The interface between 3 and 3 in the 3L well area electrically connects the two in a short circuit, and then the patterned photoresist layer 326 is removed. 1 Please refer to the figure, and form a layer pattern on the entire substrate 300: The first resist layer 328, and the patterned photoresist layer 328 exposes the source region 32. Then, a "3 ^ 4 engraving step is performed to pattern the photoresist layer 328 and the trench 330 with a gap wall, and form the source region 32. a, and the source region 32 0a is located below the gap wall 324. In the middle, the sidewall of 330 has an obtuse angle θ, and the bottom of the trench 30 and the trench ^ ^ .30〇aa .3! 6: ΪΓΛΡ tt IT : ^ ^ Between the regions 320a. Then, perform the one-phase / two-phase source cell θ1 η ion implantation step to stack the gate electrode structure 318 and the patterned photoresist layer 32 8 is the mask, implanted with dopants in the base 300 of the ..., the side wall of the shape & ^ ## 木 33 () and the bottom ion "implanting energy is 6G 仟 electron volts" = Dopant is

1 015 atomic centimeter per square centimeter, the implantation dose is 1 X energy, and the electron μ ion 'is implanted at about a volt. The method of doping includes the method of mixing impurities. Implanting dopants with an inclination angle of 30 degrees to 30 degrees: Implantation method, for example, short-circuit connection with 15 area 306a. Second, source area 32〇a Remove the patterned photoresist layer 328 with P-type Wellman. 9133twf.ptd 543194 V. Description of the invention (14) Plane '------- Then refer to Figure 3G, the source between the gate structures 318 A contact window 336 (source line) is formed on the pole area 30a and a p-window between the gate structure 318 forms a contact window 338 °. The contact window 336 (source line) and the contact = 38 are, for example, a metal crane The method of forming the contact window 336 (source line) and the contact window 338_ is, for example, forming a conductor layer (not shown) on the substrate 300, and this conductor layer fills the gap between the gate structures 3 and 8 Then, a chemical mechanical polishing process or an etch-back process is performed until the gate cap layer 316 is exposed, and the source region 334 between the gate structures 318 is exposed. A contact window 336 (source line) is formed, and a conductive layer (not shown) is formed on the p-type well region 306 & between the gate structures 318. Then, a lithography etching step is performed to remove a portion The conductive layer forms an opening (not shown). This opening isolates adjacent memory cells to form a contact window 338, and the contact window 3 38 will penetrate between the drain region 32 ° 23 ^ and the p-type well region 3 0 6 The interface makes the two electrically short-circuited together. Then, an inner dielectric layer 34o is formed on the substrate 300, and the inner dielectric layer 340 fills the opening. The material of the inner dielectric layer 34o is, for example, stone. Phosphophosphite glass (BPSG) or phosphosilicate glass (PSG) is used to form the inner dielectric layer 34. For example, a chemical vapor deposition method is performed. Then, a chemical mechanical polishing process is performed to make the surface of the inner dielectric layer 340 flat. Referring to FIG. 3, a plug 342 electrically connected to the contact window 3 38 is formed in the inner dielectric layer 3 4 0. The material of the plug 342 is, for example, Yan metal. The plug 3 4 2 is formed. The method is, for example, forming an opening exposing the contact window 3 3 8 in the inner dielectric layer 3 4 0 ( (Illustrated), and then fill the opening with a conductive material to form it. Then, a conductive wire 3 4 4 (bit line) electrically connected to the plug 342 is formed on the inner dielectric layer 340. A conductive wire 3 4 4 is formed The method is for example

9133twf ptd Page 18 543194 V. Description of the invention (15) After a conductive layer (not shown) is formed on the substrate 300, a lithographic etching step is performed to form strip-shaped wires 344 (bit lines). The subsequent process of completing flash memory is well known to those skilled in the art, and will not be repeated here. The source region 320a of the present invention is formed in the substrate 300 under the spacer 324, and is connected to the side wall of the trench 3300 and the doped region 332 at the bottom. This doped region 3 3 2 can isolate the p-type well region 3 06 a, so that the contact window 336 formed later will not short-circuit the source region 32 0a and!)-Type well region 3 06a together. In addition, 'the contact window 3 3 6 (tungsten metal source line) is used to connect the source region 3 3 4 of each memory cell, so the resistance value of the source line can be reduced, and there is no need to form a source line connection on the active region. Line, which can improve the integration of components. Moreover, the present invention etches the substrate 300 to a deep n-type well area 300 to form a trench 330, and the trench 330 cuts off the p-type well area 306 to form a p-type well area 3 0 6 a 'such that the p-type well Region 3 06a is located only between the source regions 320a of two adjacent memory cells. Because the p-well region 3 06a of the present invention does not use the conventional inclination angle (inclination angle of 0 to 180 degrees), the ion implantation step and the dopant driving step are completed, so the method of the present invention It can prevent the implanted dopants from penetrating the% oxide layer and cause leakage current on the drain side of the memory cell, leading to the failure of the isolation between the bit lines and the gap, and it will not form on the edge of the stacked gate structure. Oxides can maintain device performance and yield. In addition, when the contact window 33 6 and the contact window 338 are formed in the present invention, the conductor 3 is straightened and formed into a conductor layer, and then a part of the conductor layer is removed by using an etch-back process or a mechanical polishing process until the gate top is exposed. The cap layer β does not need to etch the inner dielectric layer and the 13-type substrate to form a contact window opening π that penetrates the inner dielectric layer and the drain region, so the connection can be improved.

543194 V. Description of invention (16) Process margin. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

9133twf.ptd Page 20 543194

9133twf.ptd Page 21

Claims (1)

543194 6. Scope of patent application 1 · A structure of a flash memory device, the structure of the flash memory device includes: the second Γ = electric type substrate, the first conductive type substrate has a trench; π1 second electric type A first well region, the second conductivity type first well region is disposed in the first conductivity type substrate; a stacked gate structure, the stacked gate structure is disposed on the first conductivity type substrate; π Υ a ^ A first gap wall and a second gap wall, the first gap wall and the first: ί arranged on the side of the stacked gate structure, and the first gap wall is connected with the top of the trench; mf = ΐ ί, the source region is disposed in the Vth electric type substrate below the first gap wall; mol = Ξ ί, the drain region is disposed in the second power-receiving Sd storm not in the second gap wall In the bottom; Yu Xi: The second well type electric second well area, the first conductivity type second well area is provided with two degrees of conductivity ;: between the structure and the second conductivity type first well area, and the bottom of the first trench The interface between the first-well region and the second-conductivity-type well region is higher than the isolation of the first-conductivity-type second well Region 'the doping region is provided on the side wall and bottom of the trench' the doping & is connected to the source region, and a middle contact window, the first contact window fills the first conductivity type substrate And make electrical contact with the source region. 2. The knot of the flash memory device as described in item 1 of the scope of patent application Painting__1 Page 22 9133twf.ptd 543194 6. The scope of the patent application, wherein the first conductive substrate includes a p-type substrate. 3. The structure of the flash memory device according to item 1 of the scope of the patent application, wherein the first well region of the second conductivity type includes a deep n-type well region. 4. The structure of the flash memory device according to item 1 of the scope of the patent application, wherein the first conductive type second well region includes a p-type well region. 5. The structure of the flash memory device according to item 1 of the scope of patent application, wherein the source region and the drain region are doped with n-type ions. 6. The structure of the flash memory device according to item 1 of the scope of the patent application, wherein the drain region and the first conductive type second well region are connected together by an electrical short circuit. 7. The structure of the flash memory device according to item 7 of the scope of the patent application, wherein the electrical short circuit passes through the interface between the drain region and the first conductive type second well interval with a second contact window. . 8. The structure of the flash memory device according to item 1 of the scope of patent application, further comprising: an inner dielectric layer, the inner dielectric layer being disposed on the first conductive type substrate; a plug, the A plug is disposed in the inner dielectric layer and is in electrical contact with the second contact window; and a wire is disposed on the inner dielectric layer and is electrically connected to the plug. 9. The structure of the flash memory device according to item 1 of the scope of patent application, wherein the dopant of the doped region has the same conductivity type as that of the source region and the drain region. 9133twf.ptd Page 23, 543194 VI. Patent application scope 10 · —A method for manufacturing a flash memory device, the method includes the following steps: providing a substrate having a first conductivity type, the substrate has sequentially formed a second A first conductive type well region, a first conductive type well region, and a stacked gate structure; forming a source region and a drain region in the substrate on both sides of the stacked gate structure; in the stacked gate A sidewall of the electrode structure forms a gap wall; a first patterned photoresist layer is formed on the substrate; the first patterned photoresist layer exposes the substrate in the drain region; and the first patterned photoresist layer and The stacked gate structure with the gap wall is a mask, and the base of the non-polar region is etched until the interface between the drain region and the first conductive type second well region is removed; removing the first patterning A photoresist layer; forming a second patterned photoresist layer on the substrate, the second patterned photoresist layer exposing the substrate in the source region; using the second patterned photoresist layer and a spacer having the spacer The stacked gate structure is a mask, and the source region is etched The substrate until the second conductivity type first well region to form a trench; Performing an -ion implantation step 'implanting dopants into the substrate at the sidewall and the bottom of the trench to form a doped region; removing the second patterned photoresist layer; stacking the body layer, the conductor layer filling the 9133twf.ptd 543194 6. The scope of the patent application removes part of the first conductor layer to form a first contact window on the source region and a second conductor layer on the first conductive type second well region, wherein the first A contact window is in electrical contact with the source region and the doped region; the second conductor layer is patterned to form a second contact window, and the second contact window makes the drain region and the first conductive type second A short-circuit connection is formed in the well region, an inner dielectric layer is formed on the substrate, and a wire electrically connected to the second contact window is formed on the inner dielectric layer. 11. The method for manufacturing a flash memory device according to item 10 of the scope of patent application, wherein the ion implantation step includes a tilt angle ion implantation method. 1 2. The method for manufacturing a flash memory device as described in item 11 of the scope of patent application, wherein the tilt angle of the ion implantation step is 15 degrees to 30 degrees. 1 3. The method for manufacturing a flash memory device as described in item 10 of the scope of the patent application, wherein the bottom of the trench and the sidewall are at an obtuse angle Θ. 14 · The method for manufacturing a flash memory device as described in item 10 of the scope of the patent application, wherein the dopant implanted in the ion implantation step has the same dopant as that of the source region and the drain region. The same conductivity type. 15 · The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, further comprising forming a plug in the inner dielectric layer, the plug electrically connecting the wire to the second Contact window. 1 6 · The flash memory device as described in item 10 of the scope of patent application 9133twf.ptd Page 25 543194 6. Scope of Patent Application Manufacturing method, wherein the first conductive type substrate includes a P-type substrate. 1 7. The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, wherein the first conductive region of the second conductivity type includes a deep n-type well region. 1 8. The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, wherein the first conductive type second well region includes a P type well region. 19. The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, wherein a method of removing a portion of the first conductor layer includes an etch-back method. 20. The method of manufacturing a flash memory device as described in item 10 of the scope of patent application, wherein the method of removing a portion of the first conductor layer includes a chemical mechanical polishing method. 9133twf.ptd Page 26