經濟部智慧財產局員工消費合作社印製 541623 A7 ____B7 五、發明説明（） 發明領域： 本發明係與一種半導體製程有關，特別是有關於一種 於沈積之矽層中消除其内應力的製程方法。本發明中提供 一沈積後之回火製程處理，以消除矽層之内應力，減少晶 圓變形及所定義之結構斷裂或損壞之問題。 發明背景： 隨著半導體工業的發屐，積體電路晶片上元件的積集 度在過去過數十年中急速提昇，目前在單一晶片上已能容 納數百萬個、甚至是數千萬個以上的元件，隨著積集度的 增加，製程技術也需同時提昇，以期在良好的成本控制下， 增加產品的良率。半導體製程技術中最為重要的部分，例 如微影、蝕刻、沈積、及熱處理等，於近年來技術發展上 皆有快速而積極的成長，以達到高積集度的要求。 在半導體製程之中，沈積製程用以形成各種不同的材 質於基材上，並扮演製程中極重要的角色，在沈積製程中， 係希望能以預設的厚度、沈積特定的材質於指定的區域 上，並同時需維持良好的厚度均勻性及材質均勻性。以積 體電路晶片高積集度之製程整合的觀點而言，沈積的材質 層須具有良好的密度及晶粒排列，尤其是在如石夕層、金屬 層、及電容之電極間介電層等，對元件或電路操作特性具 有重要影響的沈積層而言，其需求更為殷切。 ^ ： 、玎 (請先閱讀背面之注意事項再填寫本頁) 2 541623 A7 ____ B7_ 五、發明说明（） (請先閱讀背面之注意事項再填寫本頁) 矽為半導體工業中極為重要的材料，在目前的半導體 製程之中，矽材質已被廣為應用作為基材、電晶體閘極、 字元線、位元線、以及電容之電極板等的材料，在大部分 的應用之中，皆利用矽層在經過植子植入或摻雜後所具有 的電性特性’以提供所需的電性及操作特性。目前最常使 用做為形成發層的方法為化學氣相沈積法，以於良好的製 程化學組成及參數的控制之下形成均勻度良好的矽層。在 對沈積層材質密度及特性要求曰益提高之下，低壓化學氣 相沈積法在矽層沈積上的應用也日益頻繁，以提供密度及 均勻度良好的石夕層。 然而’以沈積的矽層、尤其是以低壓化學氣相沈積法 所沈積的矽層，經常會在其密度較為緻密的材質特性影響 之下、產生因内部應力較高所導致的問題。參見第一 a圖 所示，半導體晶圓10上具有矽層12於其表面上，在許多 的化學氣相沈積製程之中，尤其是低壓化學氣相沈積製程 中，石夕層12是以完全覆蓋的方式，形成於晶圓1〇的全部 表面上’因此晶圓10的上、下、側方等表面皆有石夕層i 2 的覆蓋。 經濟部智慧財產局員工消費合作社印製 參見第lb圖所示，接著即對矽層12進行圖案化的製 程，以形成如字元線、位元線、閘極結構、及導線等的結 構’圖中的結構12a及12b即在圖案化製程之後定義於晶 圓1〇上，一般而言，在圖案化製程之後的製程之中，晶圓 10需接受高達800°c之高溫製程的處理，以調整所沈積之 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X297公釐)---- 541623 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 矽層1 2的電性特性。由於矽層1 2為一較緻密排列之材質， 即會在高溫製程的影響下，於矽層12及結構12a及12b内 產生内應力，而在各層間應力大小或膨脹係數的不同之 下，即會因此而產生如第一 c圖中所示的晶圓變形問題； 或是在微小的外部應力的觸發下、產生如第一 d圖中部分 的結構12a及12b因而斷裂等的問題，而使產品的可靠度 大為下降。 第二a圖至第二d圖顯示應力所導致之缺陷問題的另 一介紹例，參見第二a圖所示，半導體晶圓20上具有預先 定義的介電層或氧化層22，以定義之後形成之電容電極的 形狀；矽層24則形成於晶圓20及介電層22的表面，同樣 的，矽層24可完整的覆蓋於晶圓20及介電層22的上、下、 側方等之表面上。 經濟部智慧財產局員工消費合作社印製 參見第二b圖所示，接著即回蝕或研磨矽層 24的表 面，以曝露出介電層22，之後並去除介電層22，以留下如 第二c圖中的電容之電極結構24a及24b ; —般而言，在形 成電極結構24a及24b後的製程之中，晶圓20需接受高達 800°C之高溫製程的處理，以調整所沈積之矽材質及結構的 電性特性，同前所述，在高溫製程的影響下，矽層24及電 極結構24a及24b内會產生内應力，而導致如第二d圖中 所示的晶圓變形彎曲的問題；或是在微小的外部應力的觸 發下、產生如第二d圖中部分的電極結構24a及24b因而 斷裂等的問題，使產品的可靠度因高溫製程下内應力變化 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 541623 A7 經濟部智慧財產局員工消費合作社印製 B7五、發明説明（） 的影響而大為下降。 發明目的及概述： 本發明的目的為提供一種矽層沈積及定義的製程。 本發明的另一目的，為提出一種於沈積之矽層中消除 其内應力的製程方法。 本發明的另一目的為提出一種矽層沈積及定義的製 程，並加入沈積後之回火製程處理，以消除矽層之内應力， 減少晶圓變形、或是所定義之結構因外應力而斷裂或損壞 等問題。 本發明中於沈積及圖案化矽層於半導體晶圓上時，消 除内應力的製程，可包含以下步驟：首先沈積矽層於晶圓 之全部表面上；接著於沈積矽層步驟後，對矽層進行一熱 製程以消除矽層之内應力；並於内應力消除後，圖案化石夕 層。以較佳實施例而言，上述之熱製程可使用回火製程， 其溫度約為600°C至850°C之間。 圖式簡單說明： 第一 a圖 顯示傳統製程中晶圓及外圍之矽層的截面示意 圖。 第一 b圖 顯示傳統製程中圖案化矽層的截面示意圖。 第一 c圖 顯示傳統製程中晶圓彎曲變形的截面示意圖。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 541623 A7 _B7_ 五、發明說明（） 第一 d圖 顯示傳統製程中結構斷裂的截面示意圖。 第二a圖 顯示傳統製程中晶圓上具介電材質之結構及覆 蓋之矽層的截面示意圖。 第二b圖 顯示傳統製程中磨去上方部分矽層的截面示意 圖。 第二c圖 顯示傳統製程中去除介電材質結構後之截面示 意圖。 第二d圖 顯示傳統製程中晶圓彎曲變形及結構斷裂的截 面示意圖。 第三a圖 顯示本發明中晶圓及覆蓋於表面之矽層的截面 示意圖。 第三b圖 顯示本發明中之矽層進行熱製程後的截面示意 圖。 第三c圖 顯示本發明圖案化矽層、以定義結構的截面示 意圖。 第四a圖 顯示本發明中晶圓上具介電材質之結構、以及 覆蓋於表面上之矽層的截面示意圖。 第四b圖 顯示本發明中之矽層進行熱製程後的截面示意 圖。 ------.-----------------------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 圖 C 四 第 圖 d 四 第 除 去 被 層 矽 之 方 上 構 結 質 材 ο 入一II 中意 明示 發面 本截 示的 顯後 容 電 下 留 以 構 結 質 材 電 介。 除圖 去意 中示 明面 發截 本的 示極 顯電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 541623 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 發明謀細說明= 本發明中揭露一種於沈積之矽層中消除其内應力的製 程方法，藉由加入一沈積後的熱處理製程，可減低石夕層在 後續製程中所產生之内應力問題，以消除傳統製程中晶圓 彎曲變形及結構意外斷裂的缺點。沈積後的回火製程可緊 接著沈積製程進行，以重新排列晶粒結構，使内應力減至 最小，以避免後續製程、尤其是高溫製程中所產生的應力 缺陷問題。 在不限制本發明之精神及應用範圍之下，以下即以定 義導體結構及電容電極的兩個實施例，介紹本發明之實 施；熟悉此領域技藝者，在瞭解本發明之精神後，當可應 用此方法於各種不同的矽沈積製程中，來消除應力及缺陷 問題，本發明之應用當不僅限於以下所列之實施例。 本發明中於沈積及圖案化矽層於半導體晶圓上時，消 除其内應力的製程，其第一實施例可包含以下步驟：如第 三a圖所示，在半導體晶圓30上，首先沈積矽層32於晶 圓30上’在許多的化學氣相沈積製程之中，尤其是本例中 所使用的低壓化學氣相沈積製程中，矽層32是以完全覆蓋 的方式，形成於晶圓30的全部表面上，也就是如圖中所示 在晶圓30的上、下、側方等表面上，皆有石夕層32的覆蓋。 以佳較實施例而言，低壓化學氣相沈積法在矽層沈積時之 操作壓力約為1〇〇毫托及10,000毫托之間。若需提供石夕層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------^---------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 541623 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 之導電性，則可沈積多晶矽層。 參見第三b圖所示，接著即於沈積矽層 32的步驟之 後，對矽層3 2進行一熱製程，以消除矽層之内應力，本例 中之熱製程可使用回火（annealing)熱處理製程，其製程之溫 度約為 600°C至850°C之間，而較佳之溫度範圍可為 700°C 到 7 5 0 °C之間。此例中熱處理之時間可視矽層的厚度、特 性、以及溫度等諸多因素而調整，可短至1分鐘、亦可長 達24小時，以本例中之矽層32而言，在700 °C的回火製程 下，處理20至40分鐘，即足以消除矽層32的内應力。 在回火製程中，矽層3 2會在晶粒的重新排列及成長下 有體積的收縮，由於矽層3 2係完全的覆蓋於晶圓3 0之上， 其體積的收縮即會沿著垂直於晶圓3 0表面的方向收縮，不 同方向上的内應力即可相互平衡而消除，而不會產生缺陷 或應力的不同。在較佳實施例中，熱製程可在用以沈積矽 層的同一個反應室内進行，在沈積製程之後，即可藉由通 入氮氣至反應室以驅出反應氣體，停止沈積製程的進行， 並於氮氣環境中進行回火的處理。 在内應力消除之後，即可對矽層 3 2進行圖案化的步 驟，如第三c圖所示，一般而言，可進行習知的微影製程 及蝕刻製程，以圖案化晶圓3 0上表面的矽層3 2，而形成如 字元線、位元線、閘極結構、導線、或其組合等的結構， 圖中的結構32a及32b即在圖案化製程之後定義於晶圓30 上，由於矽層 3 2的内應力已經藉由前述製程的處理而消 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 541623 經濟部智慧財產局員工消費合作社印製 五、發明説明（ A7 B7 除，在後續的_ # v &潑32 I程之中，即使有高溫處理的製程，石夕禮 與結構32a及：β、时&傳統 3 2 b的内應力亦可減至最小，而可避免得 ’矛中曰曰圓彎曲變形及結構斷裂等的問題，同時提高結構 32a及32b等對外部應力的容忍值，而降低其因外部力量觸 發而斷裂的可能性。 八本發明中之另一實施即以定義電容電極的製程梦驟加 以介紹，々口第四a圖所示，在半導體晶BJ 40上具有用以定 義？極形狀的彳電層結構或氧化層Μ才冓42，並ί尤積矽層44 於a曰圓40上，同前所述，以本例中所使用的低壓化學氣相 沈積製程而s，矽層44是以完全覆蓋的方式，形成於晶圓 4〇的全部表面上，也就是如圖中所示在晶圓40及介電層餘 構42的上、下、側方等各個表面上，皆有矽層44的覆蓋。 以佳較實施例而言，低壓化學氣相沈積法在矽層沈積時之 操作壓力約為100毫托及10，〇〇〇毫托之間；若需提供矽層 之導電性’則可沈積多晶矽層。 參見第四b圖所示，接著即於沈積矽層44的步驟之 後’對石夕層44進行一熱製程，以消除矽層44之内應力， 本例中之熱製程可使用回火製程，製程之溫度可約為6〇〇 °C至8 50°C之間，較佳之溫度範圍為7〇(rc到75〇°c之間。同 樣的，此例中熱處理之時間可視矽層的厚度 '特性、以及 溫度4諸多因素而調整，可短至1分鐘、亦可長達24小時， 以本例中之矽層44而言，在700 °C的回火製程下，處理20 至40分鐘，即足以消除矽層44的内應力。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） (请先閱讀背面之注意事項存填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 541623 A7 ____B7 V. Description of the Invention () Field of the Invention: The present invention relates to a semiconductor process, and in particular to a process method for eliminating internal stress in a deposited silicon layer. The present invention provides a post-deposition tempering process to eliminate the internal stress of the silicon layer, reduce the problems of crystal circle deformation and the defined structure fracture or damage. Background of the Invention: With the development of the semiconductor industry, the degree of integration of components on integrated circuit wafers has increased rapidly in the past few decades. Currently, it can accommodate millions, even tens of millions, on a single chip. With the increase of the above components, the process technology also needs to be improved at the same time, in order to increase the yield of the product under good cost control. The most important parts of semiconductor process technology, such as lithography, etching, deposition, and heat treatment, have all grown rapidly and actively in recent years to achieve the requirements of high accumulation. In the semiconductor process, the deposition process is used to form a variety of materials on the substrate, and plays a very important role in the process. In the deposition process, it is hoped that a specific material can be deposited with a predetermined thickness on a specified thickness. Area, while maintaining good thickness uniformity and material uniformity. From the point of view of the integration of the integrated circuit wafer with a high degree of integration, the deposited material layer must have a good density and grain arrangement, especially in the dielectric layer between the electrodes such as the Shixi layer, the metal layer, and the capacitor. Etc., for deposited layers that have a significant impact on the operating characteristics of components or circuits, their demands are even greater. ^: 玎, (please read the notes on the back before filling this page) 2 541623 A7 ____ B7_ V. Description of the invention () (please read the notes on the back before filling this page) Silicon is a very important material in the semiconductor industry In the current semiconductor manufacturing process, silicon has been widely used as a material for substrates, transistor gates, word lines, bit lines, and capacitor electrode plates. In most applications, All use the electrical characteristics of the silicon layer after implantation or doping to provide the required electrical and operating characteristics. At present, the most commonly used method for forming a hair layer is a chemical vapor deposition method to form a silicon layer with good uniformity under the control of good process chemical composition and parameters. With the increasing requirements for the density and characteristics of sedimentary layers, the application of low-pressure chemical vapor deposition on silicon layer deposition has become more frequent in order to provide a stone layer with good density and uniformity. However, the silicon layer deposited, especially the silicon layer deposited by the low pressure chemical vapor deposition method, often causes problems due to high internal stress under the influence of its denser material characteristics. As shown in FIG. 1a, the semiconductor wafer 10 has a silicon layer 12 on its surface. In many chemical vapor deposition processes, especially in the low-pressure chemical vapor deposition process, the stone layer 12 is completely The covering method is formed on the entire surface of the wafer 10 '. Therefore, the upper, lower, and lateral surfaces of the wafer 10 are covered with the stone layer i 2. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown in Figure lb, and then patterning the silicon layer 12 to form structures such as word lines, bit lines, gate structures, and wires, etc. ' The structures 12a and 12b in the figure are defined on the wafer 10 after the patterning process. Generally speaking, in the process after the patterning process, the wafer 10 needs to be processed at a high temperature process up to 800 ° C. Adjust the size of the deposited paper to apply Chinese National Standard (CNS) A4 (210 X297 mm) ---- 541623 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Silicon Electrical characteristics of layer 12. Since the silicon layer 12 is a relatively densely arranged material, internal stress will be generated in the silicon layer 12 and the structures 12a and 12b under the influence of the high temperature process, and under the difference in the magnitude of the stress or the expansion coefficient between the layers, Therefore, the problem of wafer deformation as shown in the first c diagram is caused by this; or a small external stress is triggered, and problems such as the structure 12a and 12b of the part in the first d diagram are broken, and the like, and This greatly reduces the reliability of the product. Figures 2a to 2d show another example of the defect problem caused by stress. As shown in Figure 2a, the semiconductor wafer 20 has a pre-defined dielectric layer or oxide layer 22. The shape of the formed capacitor electrode; the silicon layer 24 is formed on the surface of the wafer 20 and the dielectric layer 22. Similarly, the silicon layer 24 can completely cover the top, bottom, and sides of the wafer 20 and the dielectric layer 22. Wait on the surface. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 2b, and then etch back or polish the surface of the silicon layer 24 to expose the dielectric layer 22, and then remove the dielectric layer 22 to leave as The electrode structure 24a and 24b of the capacitor in the second c diagram; in general, in the process after forming the electrode structure 24a and 24b, the wafer 20 needs to be processed at a high temperature process up to 800 ° C to adjust the temperature. The electrical characteristics of the deposited silicon material and structure are the same as described above. Under the influence of the high temperature process, internal stress will be generated in the silicon layer 24 and the electrode structures 24a and 24b, which will cause the crystal as shown in the second figure d. The problem of circular deformation or bending; or the occurrence of problems such as the electrode structure 24a and 24b in the second figure d being broken due to the slight external stress, which causes the reliability of the product to change due to the internal stress in the high temperature process. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 541623 A7 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Object and Summary of the Invention The object of the present invention is to provide a silicon layer deposition and definition process. Another object of the present invention is to provide a process method for eliminating internal stress in a deposited silicon layer. Another object of the present invention is to propose a silicon layer deposition and definition process, and add a tempering process after deposition to eliminate the internal stress of the silicon layer, reduce wafer deformation, or define the structure due to external stress. Breakage or damage. In the present invention, when depositing and patterning a silicon layer on a semiconductor wafer, the process of eliminating internal stress may include the following steps: firstly depositing a silicon layer on the entire surface of the wafer; The layer undergoes a thermal process to eliminate the internal stress of the silicon layer; and after the internal stress is eliminated, the fossil layer is patterned. In a preferred embodiment, the above-mentioned thermal process can use a tempering process, and its temperature is about 600 ° C to 850 ° C. The diagram is briefly explained: Figure 1a shows a schematic cross-sectional view of a silicon wafer and a peripheral silicon layer in a conventional process. Figure 1b shows a schematic cross-section of a patterned silicon layer in a conventional process. Fig. 1c shows a schematic cross-sectional view of the bending and deformation of a wafer in a conventional process. (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 541623 A7 _B7_ V. Description of the invention () The first d picture shows the structure fracture in the traditional process. Schematic cross-section. Figure 2a shows a schematic cross-section of a dielectric material structure and a covered silicon layer on a wafer in a traditional process. Figure 2b shows a schematic cross-sectional view of the silicon layer on the upper part of the conventional process. Figure 2c shows the schematic cross-section of the traditional process after removing the dielectric material structure. Figure d shows a cross-sectional view of the wafer bending and structural fracture in the traditional process. Fig. 3a is a schematic cross-sectional view of the wafer and the silicon layer covering the surface in the present invention. Fig. 3b is a schematic cross-sectional view of the silicon layer in the present invention after being thermally processed. Figure 3c shows a schematic cross-section of the patterned silicon layer of the present invention with a defined structure. Figure 4a is a schematic cross-sectional view showing the structure of the dielectric material on the wafer and the silicon layer covering the surface in the present invention. Fig. 4b is a schematic cross-sectional view of the silicon layer in the present invention after being thermally processed. ------.----------------------- ^ (Please read the notes on the back before filling out this page) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Consumption cooperative prints C, C, D, D, and D. Remove the structured material on the side of the layered silicon. Enter II, and expressly show that the cut-off capacitors shown in this section are reserved for the structured material dielectric. In addition to the drawings, the printed version of the display pole is shown in the original version. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 541623 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the invention (Inventive plan = In the present invention, a process method for eliminating the internal stress in the deposited silicon layer is disclosed. By adding a post-deposition heat treatment process, the Shi Xi layer can be reduced in subsequent processes. Stress problem to eliminate the disadvantages of wafer bending deformation and accidental fracture of the structure in the traditional process. The tempering process after deposition can be followed by the deposition process to rearrange the grain structure and minimize internal stress to avoid subsequent processes. In particular, the problem of stress defects generated in high temperature processes. Without limiting the spirit and scope of the present invention, the following describes the implementation of the present invention by defining two embodiments of a conductor structure and a capacitor electrode; familiar with this field After knowing the spirit of the present invention, the artist can apply this method to various silicon deposition processes to eliminate stress and defects. The problem is that the application of the present invention is not limited to the embodiments listed below. In the process of depositing and patterning a silicon layer on a semiconductor wafer in the present invention, the process of removing the internal stress may include the following steps: As shown in Figure 3a, on the semiconductor wafer 30, a silicon layer 32 is first deposited on the wafer 30. Among many chemical vapor deposition processes, especially the low pressure chemical vapor deposition used in this example In the manufacturing process, the silicon layer 32 is formed on the entire surface of the wafer 30 in a completely covered manner, that is, as shown in the figure, there are stone layers on the top, bottom, and side surfaces of the wafer 30. Coverage of 32. In a preferred embodiment, the operating pressure of the low pressure chemical vapor deposition method during the deposition of the silicon layer is between about 100 mTorr and 10,000 mTorr. If a Shi Xi layer is required, the paper size is applicable. China National Standard (CNS) A4 Specification (210 X 297 mm) ------ ^ --------------- Order --------- line (please (Please read the precautions on the back before filling this page) 541623 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention () Conductive, you can deposit a polycrystalline silicon layer. As shown in Figure 3b, immediately after the step of depositing the silicon layer 32, a thermal process is performed on the silicon layer 32 to eliminate the internal stress of the silicon layer. In this example, The thermal process can use an annealing heat treatment process. The temperature of the process is about 600 ° C to 850 ° C, and the preferred temperature range is 700 ° C to 750 ° C. In this example, The heat treatment time can be adjusted according to many factors such as the thickness, characteristics, and temperature of the silicon layer, which can be as short as 1 minute or as long as 24 hours. For the silicon layer 32 in this example, tempering at 700 ° C Under the process, the treatment for 20 to 40 minutes is enough to eliminate the internal stress of the silicon layer 32. During the tempering process, the silicon layer 32 will shrink in volume under the rearrangement and growth of the crystal grains. Since the silicon layer 32 completely covers the wafer 30, its volume shrinkage will follow The shrinkage in the direction perpendicular to the surface of the wafer 30 allows the internal stresses in different directions to be balanced with each other and eliminated, without causing defects or differences in stress. In a preferred embodiment, the thermal process can be performed in the same reaction chamber used to deposit the silicon layer. After the deposition process, the reaction process can be stopped by passing nitrogen into the reaction chamber to stop the deposition process. And tempered in a nitrogen environment. After the internal stress is removed, the silicon layer 32 can be patterned. As shown in Figure 3c, in general, the conventional lithography process and etching process can be performed to pattern the wafer 30. The silicon layer 32 on the upper surface forms a structure such as a word line, a bit line, a gate structure, a wire, or a combination thereof. The structures 32a and 32b in the figure are defined on the wafer 30 after the patterning process. As the internal stress of the silicon layer 32 has been eliminated by the aforementioned process (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 541623 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (except for A7 B7, in the subsequent _ # v & splash 32 I process, even if there is a high temperature process, Shi Xili and structure 32a and: β, The internal stress of the traditional & traditional 3 2 b can also be minimized, and the problems of circular bending deformation and structural fracture of the spear can be avoided. At the same time, the tolerance values of the external stress such as the structures 32a and 32b are improved, and Reduced its breakage due to external force trigger 8 Another implementation of the present invention is described by the process of defining a capacitor electrode. As shown in Figure 4a of the gate, a semiconductor layer BJ 40 has a structure of an electroluminescent layer for defining a pole shape. Or the oxide layer M is 42, and the silicon layer 44 is formed on a circle 40. As described above, the silicon layer 44 is completely covered by the low-pressure chemical vapor deposition process used in this example. The method is formed on the entire surface of the wafer 40, that is, as shown in the figure, the silicon layer 44 is formed on each surface of the wafer 40 and the dielectric layer structure 42 on the upper, lower and lateral sides. In a preferred embodiment, the operating pressure of the low-pressure chemical vapor deposition method during the deposition of the silicon layer is about 100 mTorr and 10,000 mTorr; if the conductivity of the silicon layer is required, then A polycrystalline silicon layer can be deposited. As shown in FIG. 4b, immediately after the step of depositing the silicon layer 44, a thermal process is performed on the stone layer 44 to eliminate the internal stress of the silicon layer 44. The thermal process in this example may be Using tempering process, the temperature of the process can be about 600 ° C to 8 50 ° C, and the preferred temperature range is 7 〇 (rc to 75 ° C. Similarly, the heat treatment time in this example can be adjusted depending on the thickness of the silicon layer and the temperature 4 factors, which can be as short as 1 minute or as long as 24 hours. For the silicon layer 44 in this example, in the tempering process at 700 ° C, processing for 20 to 40 minutes is sufficient to eliminate the internal stress of the silicon layer 44. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back and fill in this page)
，1T 541623 A7 B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 在回火製程中，矽層4 4會在晶粒的重新排列及成長下 有體積的收縮，由於矽層44係完全的覆蓋於晶圓40及介 電層結構4 2之上，其體積的收縮即會沿著垂直於晶圓4 0 各個表面的方向收縮，不同方向上的内應力即可相互平衡 而消除，而不會產生缺陷或是應力的差異。在較佳實施例 中，熱製程可在用以沈積矽層44的同一個反應室内進行， 在沈積製程之後，即可藉由通入氮氣至反應室以驅出反應 氣體，停止沈積製程的進行，並於氮氣環境中直接進行回 火的處理。 經濟部智慧財產局員工消費合作社印製 在内應力消除之後，即將矽層44回蝕或研磨至曝露出 介電層結構42為止，如第四c圖所示，一般而言，可使用 習知之化學機械研磨製程或其他的回蝕製程，去除位於介 電層結構42上方的矽層44。之後即如第四d圖所示，將介 電層結構42加以去除，即露出各個獨立的電容電極44a及 44b等，由於矽層44的内應力已經藉由前述製程的處理而 消除，在後續的製程之中，即使有高溫處理的製程，矽層 44與電容電極44a及44b的内應力亦可減至最小，而可避 免傳統製程中晶圓彎曲變形及結構斷裂等的問題，同時提 高電容電極44a及44b等結構對於外部應力的容忍限度， 而大幅降低其因外部力量觸發而斷裂的機率。 因此，藉由本發明中之方法，沈積之矽層内之應力即 可降至最低，傳統製程中之晶圓彎曲變形及結構斷裂等的 問題亦可因而消除，同時提昇各個結構對外界應力的抵抗 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 541623 A7 B7 五、發明説明（） 能力。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同領域而定。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）1T 541623 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) In the tempering process, the silicon layer 4 4 will shrink in volume under the rearrangement and growth of the crystal grains. The silicon layer 44 is completely covered on the wafer 40 and the dielectric layer structure 42. The shrinkage of the volume will shrink in the direction perpendicular to the various surfaces of the wafer 40. The internal stress in different directions can mutually Balance and eliminate without defects or differences in stress. In a preferred embodiment, the thermal process can be performed in the same reaction chamber used to deposit the silicon layer 44. After the deposition process, the reaction gas can be driven out by passing nitrogen into the reaction chamber to stop the deposition process. , And directly tempered in a nitrogen environment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs after the internal stress is removed, the silicon layer 44 is etched back or ground until the dielectric layer structure 42 is exposed. As shown in Figure 4c, in general, it can be used The chemical mechanical polishing process or other etch-back process removes the silicon layer 44 located above the dielectric layer structure 42. After that, as shown in the fourth figure d, the dielectric layer structure 42 is removed, that is, the individual capacitor electrodes 44a and 44b are exposed. Since the internal stress of the silicon layer 44 has been eliminated by the aforementioned process, In the manufacturing process, even if there is a high-temperature processing process, the internal stress of the silicon layer 44 and the capacitor electrodes 44a and 44b can be minimized, and problems such as wafer bending and structural fracture in the traditional process can be avoided, and the capacitance can be improved. The tolerance of the structures such as the electrodes 44a and 44b to external stress greatly reduces the probability that the structures will break due to external force. Therefore, with the method of the present invention, the stress in the deposited silicon layer can be minimized, and the problems of wafer bending and structural fracture in the traditional process can be eliminated, and the resistance of each structure to external stress can be improved. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 541623 A7 B7 V. Description of invention () Ability. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, and is not intended to limit the spirit of the present invention. Those skilled in the art will not depart from the present invention after understanding the spirit of the present invention. Within the scope of the spirit, when it can be modified and replaced with equivalent changes, the scope of patent protection shall depend on the scope of the attached patent application and its equivalent fields. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)