經濟部中央梯準局貝工消费合作社印製 Λ7五、發明説明（） 本發明係提供一種負載電阻的製造方法，尤 指一種用於半導體製程中負載電阻的製造方 法0 \ 5 現行半導體晶片製程中，常利用多晶矽 (Poly-Silicon)材料來形成高阻抗電P且 (resistor)，例如靜態隨機存取記憶體 (static random access memory，簡稱 SRAM) 的製程中，便常由多晶矽所形成的電阻來取代 10 當作負載（1 o a d ) 的電晶體，使 SRAM内電晶 體數量因這種負載電阻的取代而減少，進而達 到節省成本、提高積集度（integration)的目 的〇 15 請參考圖一及圖二，圖一及圖二為習知半導 體晶片1 0負載電阻的製造方法。半導體晶片1 0 表面包含有一麥基材 12，一無摻雜二氧化碎 (neutral silicate glass，簡稱 NSG)層 14 沉積於矽基材 12之上，用來作為隔離保護的 20 絕緣層，一線形的多晶碎（ρ ο 1 y s i 1 i c ο η )層 16均勻地沉積於NSG層 14之上，用來作為電 連接的導線。首先，如圖一所示，半導體晶片 10 表面進行坤（As)離子的離子植佈（ion 2 ---：--r----r -- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國圏家標準（CNS ) A4規格（210X297公#_ ) 經濟部中央梂準局貝工消费合作社印製 Λ7 B7 五、發明説明（） implantation)，對多晶碎層 16 作一初步性 的輕掺雜（lightly dopant)，用以破壞缺陷 並使整個多晶矽層1 6的電阻値均勻化。 5 接著，如圖二所示，利用微影 (photolithography)及蚀刻（etching)等製 程，在多晶矽層 16表面形成一光阻 18，用來 作為離子植佈製程的幕罩（mask)犧牲層 (sacrificial layer)，然後利用離子植佈 10 製程對半導體晶片1 0表面之多晶矽層1 6作一 磷（P )離子的摻雜，用以均勻地降低整個多晶 矽層16的電阻値，使多晶矽層16成為電的良 導體，並使光阻18所覆蓋的多晶矽區域20形· 成一相對高阻抗的負載電阻。 15 然而欲達到積體電路設計上之等高阻抗（一 般約幾百GQ以上），通常需要沉積相當長度及 相當面積的多晶矽材料，因此在0 . 2 5 # m以下 的半導體製程，這種多晶矽型負載電阻的製程， 20 會有高阻抗負載電阻元件佔據過多佈局空間， 以及半導體晶片積集度受到限制的缺點。 本紙张尺度適历中國國家標率（CNS ) Α4規格（210X297公廣） ---·--^----ί"-- (請先閱讀背面之注意事項再填寫本頁) -，1Τ 經濟部中央標準局貝工消费合作社印製 Λ7 B? 五、發明説明（） 所以本發明之主要目的在於提供一種用於半 導體製程中負載電阻的製造方法，不但可解決 上述問題，也可簡化習知負載電阻的製作程序。 5 圖示之簡單説明 圖一和圖二為習知半導體晶片之負載電阻的製 造方法。 圖三至圖五為本發明用於半導體製程中之負載 電阻製造方法。 10 圖六為本發明負載電阻製造方法的另一實施 例0 .圖式之符號説明 10、30半導體晶片 12、32矽基材 15 14、34NSG層 16 多晶矽層 18 光阻 2 0 多晶矽區域 3 6 摻雜多晶矽層 38 凹洞 4 0 粗糙多晶矽層 42 絕緣層 20 請參考圖三至圖五，圖三至圖五為本發明用 於半導體製程中之負載電阻的製造方法。半導 體晶片30表面包含有一矽基材32,以及一 NSG 層34沉積於矽基材32之上，作為保護隔離的 4 本紙張尺度適用中困S家梯準（CNS)A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央梂準局貞工消费合作社印製 Λ7 B7五、發明説明（） 絕緣層。首先，如圖三所示，於 NSG層 34上 沉積一線形的多晶矽層，並隨著沉積反應的進 行（in situ)將鱗離子掺入多晶梦層中，使NSG 層 34.的上方均勻地形成一線形的摻雜多晶矽 5 層3 6，用來作為電連接的導線。 接著，如圖四所示，利用微影及蝕刻等製程， 在線形的摻雜多晶矽層 36 表面挖出一凹洞 38，使凹洞38結構深入NSG層 34，以截斷作 10 為導線的摻雜多晶矽層 3 6。然後利用低壓化學 氣相沉積法(low pressure chemical vapor deposition，簡稱 LPCVD)在半導體晶片 30 表面沉積一粗糙多晶句 (rugged poly-silicon)層 40，使凹洞 38 表層均勻地覆蓋 15 一層薄薄的粗糙多晶矽層4 0。 然後，如圖五所示，利用化學機械研磨 (chemical mechanical polishing)之平 坦化製程或回蝕（etch back)製程，對半導體 20 晶片 3 0進行表面處理，以去除凹洞 3 8之外的 粗糙多晶矽層 4 0，但是粗糙多晶矽層 4 0仍連 接於摻雜多晶矽層 3 6導線的截斷處。最後再 於半導體晶片30表面形成於一層絕緣層42覆 (請先閲讀背面之注意事項再填寫本頁) 本紙张尺度適用中國國家標準（CNS ) A4規格（210X297公:ft ) y Λ7 B1 經濟部中央橾準局負工消费合作社印聚 五 、發明説明（ ) 1 | 蓋 於 摻 雜 多 晶 層 3 5以及粗链多 晶矽層 4 0 之 1 I 上 如 此 本 發 明 之 用 於 半 導 體 晶 片 上 的 負 載 電 1 | 阻 便 製 備 冗 成 5 而 凹 洞 3 8 '内與多 晶甘y 7層 2 6 導 /—S 1 1 ， 請 I 線 的 截 斷 處 所 覆 蓋 的 粗 糙 多 晶 矽 層 ,4 〇 便 是 本 先 閱 1 I 讀 1 I 5 發 明 方 法 所 形 成 的 負 載 電阻 〇 背 之 1 1 I 粗 糙 多 晶 矽 層 4 0 為 不 帶 由 電 子 之 不 良 導 /i 意 事 項 1 1 1 再 1 | 體 9 同 時 粗 糙 多 晶 矽 層 4 0 中 所 形 成 大 量 的 細 填 寫 本 小 晶 粒 造 成 其 内 晶 界 (g r a i η bo u n d a r y) 數 量 頁 1 I 10 大 幅 增 加 因 此 本 發 明 製 程 中 由 粗 糙 多 晶 矽 層 1 1 1 4 0 所形成的負 載電 阻， 其 電 阻 相 對 地 較 習 知 製 1 1 造 方 法 中 無 摻 雜多 晶珍所形成的 負 載 電 阻 為 1 訂 大 〇 換 句 話 説 對 於 相 同 的 電 阻 値 本 發 明 所 1 I 形 成 的 負 載 電 阻在 .半導體表， &伟 局 所 佔 的 面 1 1 1 15 積 ， 較 習 知 方 法 所 形 成 的 負 載 電 阻 所 佔 面 積 為 1 1 小 〇 同 時 凹 洞 的 立 體 結 構 設 計 更 能 有 效 地 縮 小 1 铲 負 載 電 阻 所 需 要 的平 面 面 積 0 而 且 本 發 明 之 製 |\ I 程 可 藉 由 控 制 L PC V D 的 沉 積 溫 度 來 控 制 粗 链 多 1 1 1 晶 矽 層 4 0 的 晶 粒 大 小 9 以 控 制 負 載 電 阻 的 電 1 1 20 阻 値 0 1 1 I 請 參 考 圖 六 5 圖 六 為 本 發 明 負 載 電 阻 製 造 方 1 1 1 法 的 另 實 施 例 〇 半 導 體 6 晶 片 5 0 如 圖 四 所 示 1 1 1 1 1 1 本紙伕尺度適用中囷囷家標率（CNS ) Λ4坭格（210X297公A ) 五、發明説明（ 方後 的之 法 直 Λ7 B7 層 矽 晶 多 雜 摻 蓋 覆 多來 糙 2 粗4 勺 δ 層 形緣 線絕 層層 一 一 積積 沉沉 在接 6 層 片碎 晶晶 3體多 層導雜 矽半摻 晶明於 層 矽 晶 多 糙 粗 及 以 4 發導、 本傳短 成於最 完由路 便。通 ，程走 製會 之流 阻 載 負 6 電 的 内 略 省 以 加 可 便 程 製 等 蚀 回 ，，或 徑留化 路保坦 的可平 小便之 最 ο 磨 4 力 研 阻層械 8 3 粗 的 外 之 中 程 製 五 圖 述 洞前 凹故 矽機 晶學 多化 糙， 之二 明中 發法 本方 ，知 法習 方卻 造省 製但 的不 阻， 電法 載方 負造 知製 習的 於阻 較電 相載 負 有面 匕匕 心 么月 AMH 且佔 而所 ， 局 序佈 程面 作表。 製體夂 化導集 簡半積 、在片 驟阻晶 步電體 的載導 佈負半 植小高 子縮提 離的， 次效積 (請先閲讀背面之注意事項再填寫本頁) 5 11 本皆 依， 凡飾 ，修 例與 施化 實變 佳等。 較均圍 之之範 明做蓋 發所涵 本圍之 為範利 僅利專 述專明 所請發 上申本 以明屬 發應 經濟部中央橾準局貝工消费合作社印製 本紙張尺度適用中國®家標率（CNS > A4規格（210X297公浼）Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Λ7. V. Description of the Invention The present invention provides a method for manufacturing a load resistor, especially a method for manufacturing a load resistor in a semiconductor process. Poly-Silicon materials are often used to form high-resistance resistors. For example, in the process of static random access memory (SRAM), the resistance formed by poly-silicon is often used. Instead of 10 as a load (1 oad) transistor, the number of transistors in the SRAM is reduced due to the replacement of this load resistance, thereby achieving the purpose of saving costs and improving integration. 15 Please refer to Figure 1 And FIG. 2, FIG. 1 and FIG. 2 are conventional methods for manufacturing a semiconductor chip 10 load resistor. The surface of the semiconductor wafer 10 includes a wheat substrate 12, and an undoped silicate glass (NSG) layer 14 is deposited on the silicon substrate 12 as a 20-layer insulation layer for isolation and protection. The polycrystalline broken (ρ ο 1 ysi 1 ic ο η) layer 16 is uniformly deposited on the NSG layer 14 and is used as a wire for electrical connection. First, as shown in Figure 1, the surface of the semiconductor wafer 10 is ion-implanted with ion (As) ions (ion 2 ---: --r ---- r-(Please read the precautions on the back before filling in this (Page) This paper size is in accordance with Chinese Standards (CNS) A4 (210X297 公 #_) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Λ7 B7 V. Description of the invention () implantation), for polycrystalline fragments 16 A preliminary lightly dopant is made to destroy defects and uniformize the resistance of the entire polycrystalline silicon layer 16. 5 Next, as shown in FIG. 2, a photoresist 18 is formed on the surface of the polycrystalline silicon layer 16 by using processes such as photolithography and etching, and the photoresist 18 is used as a mask sacrificial layer in the ion implantation process ( sacrificial layer), and then doping the polycrystalline silicon layer 16 on the surface of the semiconductor wafer 10 with an ion implanted cloth 10 to do a phosphorus (P) ion to uniformly reduce the resistance of the entire polycrystalline silicon layer 16 and make the polycrystalline silicon layer 16 Become a good conductor of electricity and shape the polycrystalline silicon region 20 covered by the photoresistor 18 into a relatively high impedance load resistance. 15 However, in order to achieve the same high impedance in integrated circuit design (usually about several hundred GQ or more), it is usually necessary to deposit polycrystalline silicon materials of considerable length and area. Therefore, in semiconductor processes below 0.25 m, such polycrystalline silicon In the process of the type load resistor, there are disadvantages that high-resistance load resistor elements occupy too much layout space, and the degree of semiconductor wafer accumulation is limited. The size of this paper is in accordance with China's National Standards (CNS) Α4 specification (210X297 public broadcasting) --- ·-^ ---- ί "-(Please read the precautions on the back before filling this page)-, 1Τ Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Λ7 B? 5. Description of the invention () Therefore, the main purpose of the present invention is to provide a method for manufacturing a load resistor in a semiconductor process, which can not only solve the above problems, but also simplify the study. Know the procedure for making the load resistor. 5 Brief description of the diagrams Figures 1 and 2 show the conventional method for manufacturing the load resistance of a semiconductor wafer. Figures 3 to 5 show the method for manufacturing a load resistor used in a semiconductor process according to the present invention. 10 FIG. 6 is another embodiment of the method for manufacturing a load resistor of the present invention. 0. Symbols of the drawings 10, 30 semiconductor wafer 12, 32 silicon substrate 15 14, 34 NSG layer 16 polycrystalline silicon layer 18 photoresistor 2 0 polycrystalline silicon region 3 6 Doped polycrystalline silicon layer 38, recess 40, rough polycrystalline silicon layer 42, insulating layer 20 Please refer to FIGS. 3 to 5. FIGS. 3 to 5 are methods for manufacturing a load resistor used in a semiconductor process according to the present invention. The surface of the semiconductor wafer 30 includes a silicon substrate 32, and an NSG layer 34 is deposited on the silicon substrate 32. As a protective isolation, the four paper sizes are applicable to the medium-sized SCS (CNS) A4 specification (210X297 mm). (Please read the precautions on the back before filling out this page.) Order Printed by the Central Ministry of Economic Affairs, Central Bureau of Standards, Zhengong Consumer Cooperative, Λ7 B7 V. Invention Description () Insulation. First, as shown in FIG. 3, a linear polycrystalline silicon layer is deposited on the NSG layer 34, and as the deposition reaction progresses (in situ), scale ions are doped into the polycrystalline dream layer, so that the top of the NSG layer 34 is uniform. The ground forms a linear doped polysilicon 5 layer 36, which is used as a wire for electrical connection. Next, as shown in FIG. 4, a recess 38 is dug out on the surface of the linearly doped polycrystalline silicon layer 36 by using processes such as photolithography and etching, so that the recess 38 structure penetrates the NSG layer 34, and the doping is performed as a lead 10 Heteropolycrystalline silicon layer 3 6. Then a low pressure chemical vapor deposition (LPCVD) method is used to deposit a rugged poly-silicon layer 40 on the surface of the semiconductor wafer 30, so that the surface layer of the cavity 38 is evenly covered by 15 thin layers. Of rough polycrystalline silicon layer 40. Then, as shown in FIG. 5, a surface treatment is performed on the semiconductor 20 wafer 30 using a chemical mechanical polishing planarization process or an etch back process to remove the roughness other than the recess 38 The polycrystalline silicon layer 40, but the rough polycrystalline silicon layer 40 is still connected to the cut-off point of the doped polycrystalline silicon layer 36 wire. Finally, an insulating layer 42 is formed on the surface of the semiconductor wafer 30 (please read the precautions on the back before filling this page) This paper size applies to Chinese National Standards (CNS) A4 specifications (210X297 male: ft) y Λ7 B1 Ministry of Economic Affairs Central Government Standards Bureau Consumer Work Cooperatives Co., Ltd. 5. Description of the invention () 1 | Covered on the doped polycrystalline layer 3 5 and the thick chain polycrystalline silicon layer 4 0 1 I so the load current of the present invention for semiconductor wafers 1 | resistance will be prepared into 5 and the cavity 3 8 'with polycrystalline y 7 layer 2 6 guide /-S 1 1, please cover the rough polycrystalline silicon layer of the I line cutoff, 4 〇 This is the first read 1 I read 1 I 5 Load resistance formed by the inventive method. 1 of the back 1 1 Rough polycrystalline silicon layer 4 0 is not conductive with electrons / i Note 1 1 1 again 1 | Body 9 Simultaneous rough polycrystalline silicon layer 4 0 A large number of fine-filled small grains formed in the The number of internal grain boundaries (grai η bo undary) is greatly increased. Therefore, the load resistance formed by the rough polycrystalline silicon layer 1 1 1 4 0 in the process of the present invention has a relatively lower resistance than in the conventional manufacturing method 1 1 The load resistance formed by non-doped polycrystalline silicon is set to be large. In other words, for the same resistance, the load resistance formed by the 1 I of the present invention is. Semiconductor table, & the area occupied by the great bureau 1 1 1 15 The area occupied by the load resistor is 1 1 smaller than the conventional method. At the same time, the three-dimensional structure design of the cavity can effectively reduce the plane area required for the load resistance of the shovel. 0 The thickness of the coarse chain can be controlled by controlling the deposition temperature of the L PC VD. 1 1 1 Crystal silicon layer 4 0 Grain size 9 to control the electrical resistance of the load resistance 1 1 20 Resistance 0 1 1 I Please refer to Figure 6 5 Figure 6 Negative for this invention Another example of the method of the resistor manufacturer 1 1 1 〇 Semiconductor 6 Wafer 5 0 As shown in Figure 1 1 1 1 1 1 1 The paper size is applicable to the Chinese standard rate (CNS) Λ 4 grid (210X297 male A) 5 、 Instructions of the invention (The method behind the method is straight Λ7 B7 layers of silicon crystals are mixed and covered with multiple layers to roughen 2 thick 4 spoons δ layered edge line insulation layer one by one accumulates and sinks in 6 layers of broken crystals 3 bodies The semi-doped semi-doped silicon with multi-layered doped silicon crystals shows the coarseness and coarseness of the layered silicon crystals, with a lead of 4 and a short pass at the end. Pass, the resistance of the process will load 6 electric power in the province to save a little electricity to etch back, etc., or the best way to urinate Lu Baotan to urinate 4 Grinding resistance research 8 3 The rough outer and middle distance system is five pictures, and the crystals of the silicon machine are roughened. The second method is to publish the method, but the knowledge method and the practice method are made by the province but not hindered. In the knowledge system, the electric phase is loaded with a surface dagger heart, AMH, and it is occupied, and the sequence layout is shown as a table. The system's inductive guide set is a semi-product, the on-chip resistance of the step-by-step resistance of the crystal stepping body is set to a negative half-planted small-strontium, the second product (please read the precautions on the back before filling this page) 5 11 This book is based on everything, such as decoration, modification and Shihua become better. Fan Ming, who is more than the equivalent, is covered by Fan Ming. This is Fan Li, and only the special description is specified. Please submit the application form to indicate that it is printed by the Ministry of Economic Affairs, Central Standards Bureau, Shellfish Consumer Cooperative. This paper is suitable for China. ® House Standard Rate (CNS > A4 size (210X297 cm)