TW539965B - Automated processor generation system for designing a configurable processor and method for the same - Google Patents

Automated processor generation system for designing a configurable processor and method for the same Download PDF

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Publication number
TW539965B
TW539965B TW089102150A TW89102150A TW539965B TW 539965 B TW539965 B TW 539965B TW 089102150 A TW089102150 A TW 089102150A TW 89102150 A TW89102150 A TW 89102150A TW 539965 B TW539965 B TW 539965B
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TW
Taiwan
Prior art keywords
user
processor
instructions
instruction
patent application
Prior art date
Application number
TW089102150A
Other languages
English (en)
Chinese (zh)
Inventor
Earl A Killian
Ricardo E Gonzulez
Ashish B Dixit
Monica Lam
Walter D Lichtenstein
Original Assignee
Tensilica Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/246,047 external-priority patent/US6477683B1/en
Priority claimed from US09/323,161 external-priority patent/US6701515B1/en
Priority claimed from US09/322,735 external-priority patent/US6477697B1/en
Application filed by Tensilica Inc filed Critical Tensilica Inc
Application granted granted Critical
Publication of TW539965B publication Critical patent/TW539965B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/37—Compiler construction; Parser generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
TW089102150A 1999-02-05 2000-03-10 Automated processor generation system for designing a configurable processor and method for the same TW539965B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/246,047 US6477683B1 (en) 1999-02-05 1999-02-05 Automated processor generation system for designing a configurable processor and method for the same
US09/323,161 US6701515B1 (en) 1999-05-27 1999-05-27 System and method for dynamically designing and evaluating configurable processor instructions
US09/322,735 US6477697B1 (en) 1999-02-05 1999-05-28 Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set

Publications (1)

Publication Number Publication Date
TW539965B true TW539965B (en) 2003-07-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW089102150A TW539965B (en) 1999-02-05 2000-03-10 Automated processor generation system for designing a configurable processor and method for the same

Country Status (6)

Country Link
EP (1) EP1159693A2 (ja)
JP (2) JP2003518280A (ja)
KR (2) KR100874738B1 (ja)
AU (1) AU3484100A (ja)
TW (1) TW539965B (ja)
WO (1) WO2000046704A2 (ja)

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US7784024B2 (en) 2003-08-20 2010-08-24 Japan Tobacco Inc. Program creating system, program creating program, and program creating module
TWI381309B (en) * 2006-11-21 2013-01-01 Nec Corp Instruction operation code generation system
TWI416302B (zh) * 2009-11-20 2013-11-21 Ind Tech Res Inst 具電源模式感知之時脈樹及其合成方法
TWI514266B (zh) * 2011-04-07 2015-12-21 Via Tech Inc 可執行ｘ８６指令集架構及ＡＲＭ指令集架構機器語言程式指令的微處理器及其運作方法與編碼於一計算機裝置的至少一非暫態電腦可使用媒體中的電腦程式產品

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GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
JP2002230065A (ja) 2001-02-02 2002-08-16 Toshiba Corp システムｌｓｉ開発装置およびシステムｌｓｉ開発方法
WO2002084538A1 (en) 2001-04-11 2002-10-24 Mentor Graphics Corporation Hdl preprocessor
DE10128339A1 (de) * 2001-06-12 2003-01-02 Systemonic Ag Verfahren zur Validierung eines Modells für eine datenverarbeitende Schaltungsanordung
US6941548B2 (en) 2001-10-16 2005-09-06 Tensilica, Inc. Automatic instruction set architecture generation
DE10205523A1 (de) * 2002-02-08 2003-08-28 Systemonic Ag Verfahren zum Bereitstellen einer Entwurfs-, Test- und Entwicklungsumgebung sowie ein System zur Ausführung des Verfahrens
US7200735B2 (en) 2002-04-10 2007-04-03 Tensilica, Inc. High-performance hybrid processor with configurable execution units
JP2003316838A (ja) 2002-04-19 2003-11-07 Nec Electronics Corp システムｌｓｉの設計方法及びこれを記憶した記録媒体
JP4202673B2 (ja) 2002-04-26 2008-12-24 株式会社東芝 システムｌｓｉ開発環境生成方法及びそのプログラム
US7346881B2 (en) 2002-05-13 2008-03-18 Tensilica, Inc. Method and apparatus for adding advanced instructions in an extensible processor architecture
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
US7278122B2 (en) * 2004-06-24 2007-10-02 Ftl Systems, Inc. Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization
KR100722428B1 (ko) * 2005-02-07 2007-05-29 재단법인서울대학교산학협력재단 리소스 공유 및 파이프 라이닝 구성을 갖는 재구성가능배열구조
US7757224B2 (en) * 2006-02-02 2010-07-13 Microsoft Corporation Software support for dynamically extensible processors
KR100793210B1 (ko) * 2006-06-01 2008-01-10 조용범 Ａｒｍ 프로세서에서의 메모리 접근 횟수를 줄인 디코더구현방법
KR100813662B1 (ko) 2006-11-17 2008-03-14 삼성전자주식회사 프로세서 구조 및 응용의 최적화를 위한 프로파일러
JP5217431B2 (ja) 2007-12-28 2013-06-19 富士通株式会社 演算処理装置及び演算処理装置の制御方法
WO2009084570A1 (ja) * 2007-12-28 2009-07-09 Nec Corporation コンパイラ組み込み関数追加装置
JP2010181942A (ja) * 2009-02-03 2010-08-19 Renesas Electronics Corp Ｐｌｄ／ｃｐｌｄからマイコンへの置換え見積の情報提供システム及び方法
US8775125B1 (en) 2009-09-10 2014-07-08 Jpmorgan Chase Bank, N.A. System and method for improved processing performance
KR101635397B1 (ko) * 2010-03-03 2016-07-04 삼성전자주식회사 재구성 가능한 프로세서 코어를 사용하는 멀티코어 시스템의 시뮬레이터 및 시뮬레이션 방법
US8989242B2 (en) 2011-02-10 2015-03-24 Nec Corporation Encoding/decoding processor and wireless communication apparatus
KR20130088285A (ko) 2012-01-31 2013-08-08 삼성전자주식회사 데이터 처리 시스템 및 그 시스템에서 데이터 시뮬레이션 방법
KR102025694B1 (ko) * 2012-09-07 2019-09-27 삼성전자 주식회사 재구성 가능한 프로세서의 검증 방법
US10558437B1 (en) * 2013-01-22 2020-02-11 Altera Corporation Method and apparatus for performing profile guided optimization for high-level synthesis
KR102122455B1 (ko) * 2013-10-08 2020-06-12 삼성전자주식회사 프로세서의 디코더 검증을 위한 테스트 벤치 생성 방법 및 이를 위한 장치
US10084456B2 (en) 2016-06-18 2018-09-25 Mohsen Tanzify Foomany Plurality voter circuit
RU2631989C1 (ru) * 2016-09-22 2017-09-29 ФЕДЕРАЛЬНОЕ ГОСУДАРСТВЕННОЕ КАЗЕННОЕ ВОЕННОЕ ОБРАЗОВАТЕЛЬНОЕ УЧРЕЖДЕНИЕ ВЫСШЕГО ОБРАЗОВАНИЯ "Военная академия Ракетных войск стратегического назначения имени Петра Великого" МИНИСТЕРСТВА ОБОРОНЫ РОССИЙСКОЙ ФЕДЕРАЦИИ Устройство для диагностического контроля выполнения проверок
US10426424B2 (en) 2017-11-21 2019-10-01 General Electric Company System and method for generating and performing imaging protocol simulations
KR102104198B1 (ko) * 2019-01-10 2020-05-29 한국과학기술원 느긋한 심볼화를 활용한 바이너리 재조립 기술의 정확도 향상 기술 및 도구
CN110096257B (zh) * 2019-04-10 2023-04-07 沈阳哲航信息科技有限公司 一种基于智能识别的设计图形自动化评判系统及方法
CN111831543A (zh) * 2019-04-18 2020-10-27 中科寒武纪科技股份有限公司 一种数据处理方法及相关产品
CN111400986B (zh) * 2020-02-19 2024-03-19 西安智多晶微电子有限公司 一种集成电路计算设备及计算处理系统
JP7461181B2 (ja) * 2020-03-16 2024-04-03 本田技研工業株式会社 制御装置、システム、プログラム、及び制御方法
CN114721982A (zh) * 2022-03-22 2022-07-08 潍柴动力股份有限公司 一种可配置存储数据类型的读写处理方法及系统
CN114492264B (zh) * 2022-03-31 2022-06-24 南昌大学 门级电路的转译方法、系统、存储介质及设备

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7784024B2 (en) 2003-08-20 2010-08-24 Japan Tobacco Inc. Program creating system, program creating program, and program creating module
TWI381309B (en) * 2006-11-21 2013-01-01 Nec Corp Instruction operation code generation system
US8935512B2 (en) 2006-11-21 2015-01-13 Nec Corporation Instruction operation code generation system
TWI416302B (zh) * 2009-11-20 2013-11-21 Ind Tech Res Inst 具電源模式感知之時脈樹及其合成方法
TWI514266B (zh) * 2011-04-07 2015-12-21 Via Tech Inc 可執行ｘ８６指令集架構及ＡＲＭ指令集架構機器語言程式指令的微處理器及其運作方法與編碼於一計算機裝置的至少一非暫態電腦可使用媒體中的電腦程式產品

Also Published As

Publication number Publication date
KR100874738B1 (ko) 2008-12-22
JP2007250010A (ja) 2007-09-27
KR100775547B1 (ko) 2007-11-09
AU3484100A (en) 2000-08-25
CN1382280A (zh) 2002-11-27
JP2003518280A (ja) 2003-06-03
KR20070088818A (ko) 2007-08-29
KR20020021081A (ko) 2002-03-18
EP1159693A2 (en) 2001-12-05
WO2000046704A3 (en) 2000-12-14
WO2000046704A2 (en) 2000-08-10

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