TW538529B - Thin film transistor structure and the manufacturing method thereof - Google Patents

Abstract

The present invention is a thin film transistor structure and the manufacturing method thereof, which includes the following steps: providing an insulative substrate; forming a source/drain layer, a main gate insulative layer, and a first conductor layer on the insulative substrate; conducting etching on the first conductor layer to define a main gate conductor structure; sequentially forming a sub-gate insulative layer and a second conductor layer on the main gate conductor structure; and, conducting etching on the second conductor layer and the sub-gate insulative layer to define a first sub-gate conductor structure, a second sub-gate conductor structure, a first sub-gate insulative layer, and a second sub-gate insulative layer.

Description

538529 Five__Case No. 9111574R Description of the invention (1) Field of invention = a thin film transistor structure and a method for manufacturing the same, especially-and; manufacturing 2: thin film transistor structure on the manufacture of crystalline liquid crystal displays τ. ·, Thin Film Transistor LCD Display (tft lcd) is the most popular information lσσ one, because it has the advantages of light, thin and short, easy to carry, working voltage: two, and no radiation, suitable for large Large-scale production, so gradually take the Cathode Ray Tube Display (Cathode Ray Tube Display), becoming the new favorite of computer screen panels. — For the structure of the thin film transistor liquid crystal display, the thin film transistor used on it is in operation, and has a higher electric field in the drain region, so that when the device is in the off state, there is still a high leakage. Current (〇ff-shte Leakage Current), which results in the application of thin film transistors is greatly limited. In order to improve the phenomenon that the thin film transistor has a relatively high off-leakage current, the currently used improvement methods include a lightly doped drain electrode, such as “ly doped dly rai”,, σ structure, and% induction and electrode ( Fieid induced Drain) structure. Please refer to the first figure, which is a schematic diagram of a non-polar structure that slightly improves the leakage current of a thin film transistor. The structure includes an insulating substrate 11 and a source / drain structure 1 2. A gate insulation layer 3 and a gate conductor structure 14 ′, wherein the source / drain structure 12 is composed of a drain 21, a low dopant

538529 μ Amendment No. 91115746 Said 5. Description of the invention (2) Hetero-drain I 2 I I, one channel I 2 2, one, shop & 1. π q 1 Pienius .r ^ source 123 and a low-doped source ㈣. It is used in the place where the original thin film is electrically close to the channel 122, and again, the area where μ, μ, and the drain 121 are low (ie, low V; the impurity / degree is lower than the original source electrode). The heterodyne drain structure will make: thin U: In addition, because of its lower doping level, the resistance is also: ^ makes the series resistance from the pole 121 to the source 123 "compared to Res 1 stance), leading to Du ’s increase in power consumption (Power Dissipation). Another method to improve the speed reduction and power is the field induction drain ^ Zengli factory mask, and because the mask lithography core whisker process time, it also indirectly affects: The more photolithographic etching processes used in the factory, the total is equal to ^ This is because (Mls-alignments and particulate pollution are likely to occur. The reason for the poor love is that the applicant has the following knowledge: :: And research, and persevere: out :: pancreatic electrical crystal structure and its manufacturing method. ”, Mao Ming issued this case,“ the invention is bound to summarize the main purpose of this case is to use re-sinking: in the drain region, making the drain region The electric field is obtained; The phenomenon of closed leakage current. Low cattle and then improve the film. Page 5 忑 _ Case No., description of the invention (3) Another purpose of amending the case is to provide a method, u, 1 ~, and a small hunger burns for a kind of step. The method includes providing an insulating substrate; forming a conductive layer on the substrate, a second gate electrode manufacturing layer, a main gate insulating layer, and a two-sided substrate for etching to define a main gate electrode, first Conductor layer: for the first: a pair of sub-gate insulation is sequentially formed :: =; two ~ h first-the conductor layer and the sub-gate insulation-said, the di-sub-gate conductor structure, a first -The second sub-layer is etched to define the inter-sub-electrode insulating layer, and-the second: the conductor structure of the dagger,-the--according to the above concept, wherein the insulating substrate is a two glass substrate. Wherein the source / drain layer is It is a highly doped semiconducting semiconductor layer according to the above conception. It is completed according to the above conception. Polycrystalline silicon. According to the above conception channel and a source structure, the local hetero semiconductor layer is highly doped with the source / drain layer. Contains a drain structure. 'Where the length of the channel is equal to the length of the main gate ::!, The thickness of the first sub-gate insulation layer, #second sub-gate,: ,,,,,', the thickness of the layer, the first sub-gate The sum of the length of the conductor structure and the length of the Le-sub-gate conductor structure. The fossil is based on the above conception, where the main interrogation insulating layer is selected from the group consisting of the following nitrogen fragments (SiNx), silicon oxide (Si0x), and nitrogen oxides. According to the above-mentioned concept, the first conductor layer is selected from the group consisting of silicon (siOxNy), tantalum oxide a ^ x), and alumina (A1〇χ) or any combination thereof. From the following chromium,

538529 -Si ^ _91115746 Revision V. Description of the invention (4) One or any combination of platinum, group, ytterbium, tungsten molybdenum, aluminum, aluminum silicide, and copper. According to the above-mentioned concept, the etching performed on the first conductor layer is a Reactive Ion Etch. According to the above concept, the sub-gate insulating layer is selected from the group consisting of the following nitrides (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), oxide buttons (TaOx), and aluminum oxide (Α1〇χ). And other insulation materials or any combination of them to complete. According to the above concept, the second conductor layer is completed by one or any combination of materials selected from the following chromium, molybdenum, group, molybdenum button, tungsten molybdenum, aluminum, aluminum silicide, or copper. According to the above-mentioned concept, the remaining engraving performed on the second conductor layer and the sub-gate insulating layer is a reactive ion engraving. Another object of this case is to provide a thin film transistor structure including an insulating substrate; a source / drain layer on the insulating substrate; a main gate insulating layer on the source / drain layer; The main gate conductor structure, a first sub-gate insulation layer, and a second sub-gate worm strand are located on the first gate insulation layer; And a first sub-gate conductor structure and a second sub-gate = the body junction is located on the first sub-gate insulation layer and the second sub-gate And a portion of the second layer is isolated from the main gate conductor structure. According to the above-mentioned concept, wherein the insulating substrate is a glass. According to the above-mentioned concept, the source / electrode extension layer. Highly doped semiconductor

Page 7 538529 _ Case No. 91115746_ Year Month Day Amend ____ V. Description of the invention (5) According to the above idea, the highly doped semiconductor layer is made of highly doped polycrystalline silicon. According to the above-mentioned concept, wherein the source / electrode layer includes an electrode structure, a channel, and a source structure. According to the above concept, the length of the channel is equal to the length of the main gate conductor structure, the thickness of the first sub-gate insulation layer, the thickness of the second sub-gate insulation layer, and the first sub-gate conductor structure. And the length of the second sub-gate conductor structure. According to the above concept, wherein the main gate insulating layer is selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), oxide group (TaOx), and oxide ILu (AlOx). One or any combination of insulating materials is used to accomplish this. According to the above concept, the sub-gate insulating layer is selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (siOxNy), oxide (TaOx), and aluminum oxide (A 1 Ox) and other insulating materials. Another object of this case is to provide a method for manufacturing a thin film transistor. The steps include providing an insulating substrate; forming a source / inverter layer and a main gate insulating layer on the insulating substrate; and insulating the main gate. A main gate conductor structure and a sub-gate insulation layer are formed on the layer; a sub-gate conductor structure is formed on the sub-gate insulation layer. According to the above-mentioned concept, wherein the distant edge substrate is a glass substrate. According to the above concept, the source / drain layer is a highly doped semiconductor layer.

Page 8 538529 Amendment No. 91115746 V. Description of the Invention (6) Concept, in which the highly doped semiconductor layer is completed with high doping for many days. According to the above concept, wherein the source / drain layer includes a drain structure, a pass transistor, and a source structure. According to the above concept, the length of the channel is equal to the sum of the length of the main closed conductor structure, the thickness of the sub-gate insulation layer, and the thickness of the sub-gate insulation layer. According to the above concept, the main gate insulating layer is selected from the following silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (sioxNy), oxide button (TaOx), and alumina (Ai〇). x) one of the insulating materials or any combination of ^ to complete. According to the above-mentioned concept, the sub-gate insulating layer is selected from the group consisting of the following gas oxide (SiNx), oxide oxide (Si0x), oxynitride (SiOxNy), tantalum oxide (TaOx), and alumina ( AlOx) or one of any combination of insulating materials. Another object of this case is to provide a thin-film transistor structure including an insulating substrate; a source / drain layer on the insulating substrate; a main gate insulating layer on the source / non-electrode layer; a The main inter-pole conductor structure and a sub-gate insulating layer are located on the first inter-pole insulating layer; and a sub-, Γ nose: on the sub-inter-pole insulating layer, which is through the second sub-pole insulating layer One part is isolated from the main gate conductor structure. : Gen = „, wherein the insulating substrate is a glass substrate. According to the above concept, the source / drain layer is a highly doped semiconductor layer.

Page 9 538529 --- ^^ 11115746 _ month q 倐 正 5. Description of the invention (7) '' According to the above concept, the highly doped semiconductor layer is made of highly doped polycrystalline silicon. According to the above concept, the source / drain layer includes a drain structure, a channel, and a source structure. According to the above concept, the length of the channel is equal to the sum of the length of the main gate conductor structure, the thickness of the sub-gate insulation layer, and the length of the sub-gate conductor structure. According to the above concept, the main gate insulating layer is selected from the group consisting of SiNx, SiOx, SiOxNy, TaOx, and AlOx. Such as one or any combination of insulating materials to complete. According to the above concept, the sub-gate insulating layer is selected from the following silicon nitride (SiNx), silicon oxide (si0x), silicon oxynitride (siOxNy), tantalum oxide (TaOx), and aluminum oxide (ΑίΟχ) Such as one or any combination of insulating materials to complete. Brief illustration of the first diagram: It is a schematic diagram of the structure of a lightly doped OLED and a lightly doped electrode that are conventionally used to improve the leakage current of a thin film transistor. The second figure (a) (b) (c) (d) is a schematic diagram of the steps of a thin film transistor completed by the method of the preferred embodiment of the present case. The third picture is the comparison chart of the electrical properties of the thin film transistor and the traditional thin film transistor.

Page 10 538529 Case No. 91115746 Amendment V. Description of the invention (8) Description of component symbols 1 1: Insulating substrate 1 2 1: > and electrode 1 2 2: channel ^ 1 2 3 1: low doped source electrode 1 4: Gate conductor structure 22: Source / drain layer 2 2 2: Channel 2 3 · Main gate insulation layer 2 5 1 · Diyizi gate insulation layer 2 6 · Second conductor layer 2 7 2: No. Two sub-gate conductor structure 29: Gate-to-source bias (VGS) 1 2: Source / > and pole structure 1 2 11: Low-doped drain 1 2 3: Source 1 3: Gate insulating layer 2 1: Insulating substrate 2 2 1: Non-polar structure 2 2 3: Source structure 2 4: Main gate conductor structure 2 5 2 · First inter-subpole insulation layer 2 7 1: First sub-gate conductor structure 2 8: Source bias (ν s) 210: Drain-source bias (VDS) For a description of the preferred embodiment, please refer to the second figure (a) (b) (c) (d), which is preferred in this case. The embodiment illustrates the steps of the completed thin film transistor. First, on an insulation plate 21, a source / drain layer 22, a main gate insulation layer 23, and a first to conductive layer 241 are formed, as shown in the second figure (a). Then, the first conductor layer 24 is etched to define a main gate conductor structure 24, as shown in the second figure (b). Then, a sub-pole insulating layer 25 and a second conductor layer 26 are sequentially formed on the main gate conductor structure 24, as shown in the third figure (c). The most f ′ is to etch the second conductor layer 26 and the sub-gate insulation layer 25 to determine and output the first sub-gate conductor structure 2 7 1 and a second sub-gate conductor structure.

538529 + Case No. 91115746_year_I 佟 Zhengwu, description of the invention (9) 272, a first sub-gate insulation layer 251, and-a second sub-gate insulation layer 2 5 2 as shown in the second figure (d ). As for the bias type of the thin film transistor, as shown in the second figure (e), it includes a source bias (v S) 28, a gate / source bias (VGS) 29, and a drain / Source bias (VDS) 210. The above-mentioned slab edge substrate 21 is a glass substrate, the source and electrode layer 22 is a highly doped semiconductor layer, the highly doped semiconductor layer is completed with highly doped polycrystalline silicon, and the source The / drain layer 2 2 includes a drain structure 2 2 1, a channel 222, and a source structure 223, wherein the length of the channel 222 is equal to the length of the main gate conductor structure 24 and the first sub-gate. Thickness of the electrode insulating layer 2 5 1, thickness of the second sub-gate insulating layer 2 5 2, length of the first sub-gate 'body structure 2 7 1, and the second sub-gate conductor structure 2 7 2 The sum of its length. The main gate insulating layer 23 and the sub-gate insulating layer 25 are selected from the following silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), hafnium oxide (TaOx), and One or any combination of insulating materials such as aluminum oxide (ΑΙΟχ). The first conductor layer 241 and the second conductor layer 26 are selected from one or more of the following materials selected from the group consisting of the following metals, molybdenum, group, tritium group, indium crane, Ming, Shi Xihua I Lu, and copper. Any combination of them. The etching performed on the first conductor layer 241 and the second conductor layer 26 and the sub-gate insulating layer 25 is a reactive ion etching (Reactive I on Etch). Please refer to the third figure, which is a comparison diagram of the electrical properties of the thin film transistor and the traditional thin film transistor in this case. Now, the operation is performed with the bias type of the second graph (e). The result is shown in the third graph. As can be seen from the graph, under the same conditions

Page 12 538529 Case No. 91115746 Amendment V. Description of the Invention (10) (VDS = 1 0V) 'Compared to the traditional thin film transistor, the present invention does have a lower leakage current. When VGS = 15V, the leakage of the present invention The current (1 × 10-0_9) is as much as 1000 times lower than that of the traditional thin-film transistor (1 × 丨 7—7 A). As mentioned above, the present invention utilizes the deposition of a thicker gate insulating layer region丄 The electric field in the non-polar region can be reduced, and further improvement of thin film brightness is not required. Compared to the conventional technology, the process of engraving and shadowing of the hair mask is completely different from the traditional four-way technique. Therefore, it has industry; good knowledge and know-how. 3 hinder and then achieve the goal of the development of this case. This case can be modified by familiar with this technology as well as by the second application of patent application. To protect.

538529 Case No. 91115746 Modification Brief Description of the Drawings First Figure: It is a schematic diagram of a lightly doped drain (1 ^ 0) structure that is conventionally used to improve the off-leakage current of a thin film transistor. The second diagram (a) (b) (c) (d) (e): It is a schematic diagram of the steps of a thin film transistor completed by the method of the preferred embodiment of the present invention. The third picture: it is a comparison chart of the electrical properties of the thin film transistor and the traditional thin film transistor in this case.

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Claims (1)

538529 _ sickle 91115746 _ year, month, and day of revision _ 6. Patent application scope 7 · The manufacturing method described in item 1 of the patent application scope, wherein the main gate insulating layer is selected from the following silicon nitride (SiNx), oxide One or any combination of insulating materials such as silicon (si0x), oxynitride (SiOxNy), oxide button (Ta0x), and aluminum oxide (Alox). 8. The manufacturing method according to item 1 of the scope of patent application, wherein the first conductor layer is selected from the group consisting of chromium, molybdenum, molybdenum, molybdenum group, tungsten molybdenum, aluminum, Shixihuaming, copper, etc. One or any combination of materials. 9. The manufacturing method according to item 1 of the scope of patent application, wherein the etching of the first conductor layer is a reactive ion etching (React ive I on Etch) 〇 1 0 The manufacturing method according to the item, wherein the sub-gate insulating layer is selected from the group consisting of the following silicon nitride (si Νχ), silicon oxide (s 丨 〇χ), oxynitride (SiOxNy), hafnium oxide (Ta〇x ), And one or any combination of insulating materials such as alumina (Α1χ). 1 1 · The manufacturing method as described in item 1 of the scope of patent application, wherein the second conductor layer is made of a material selected from the group consisting of the following chromium, molybdenum, tantalum, molybdenum button, tungsten molybdenum, aluminum, silicon carbide, or copper One or any combination of them. 1 2 The manufacturing method as described in item 1 of the scope of patent application, wherein the etching of the second conductor layer and the sub-gate insulating layer is a reactive ion coin. 1 3 · A thin film transistor structure comprising: an insulating substrate; a source / electrode layer on the insulating substrate; a main gate insulating layer on the source / drain layer; Page 16 538529 _ Case No. 91115746 __----- i ~ --- VI. Application scope: a main gate conductor structure, a first sub-gate edge layer, and a second sub-gate insulation layer, Located on the third gate, on the edge layer; and a first sub-gate conductor structure and a first-sub-gate conductor structure, located on the first sub-gate insulation layer and the first inter-sub-pole insulation layer, It is isolated from the main gate conductor structure by a portion of the first sub-gate insulating layer and a portion of the first inter-electrode insulating layer. ^ ^ 1 4 · The "special film transistor structure" as described in item 13 of the scope of patent application, wherein the insulating substrate is a glass substrate. 》 1 5 · The thin film transistor structure described in item 13 of the scope of patent application, wherein the source / drain layer is a highly doped semiconductor ^ ° 1 6 · As described in item 15 of the scope of patent application A thin film transistor structure in which the highly doped semiconductor layer is completed with a high amount of doping. 17 · The thin film transistor structure according to item 13 of the scope of patent application, wherein the source / drain layer includes a drain structure, a channel, and a source structure. 1 8 · The tritium film transistor structure described in item 17 of the scope of patent application, wherein the length of the channel is equal to the length of the main gate conductor structure, the thickness of the first sub-gate insulation layer, and the second The sum of the thickness of the 孑 gate '纟 bar marginal layer, the length of the first sub-gate conductor structure, and the length of the second sub-gate conductor structure. 1 9 · The thin film transistor structure as described in item 3 of the patent application scope, wherein the main gate insulating layer is selected from the group consisting of Nitrogen Nitride (Si i NX), Oxide (Si 0x), Silicon oxynitride (Si0xNy), oxide button (TaOx), and aluminum oxide (A 1 0 X) are combined into any combination of them. 538529 _ Case No. 91115746 _ ^^-VI. Patent Application Range 20 · The thin film transistor structure described in item 13 of the patent application scope, wherein the sub-gate insulating layer is selected from the following silicon nitride (S i Nx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), oxide button (Ta0x), and aluminum oxide (A 1 0 X) or any combination of insulating materials. 2 1 · A method for manufacturing a thin film transistor, the steps include: providing an insulating substrate; forming a source / drain layer and a main gate insulating layer on the insulating substrate; and forming on the main gate insulating layer A main gate conductor structure and a sub-gate insulation layer; a sub-gate conductor structure is formed on the sub-gate insulation layer. 2 2 The manufacturing method as described in item 21 of the scope of patent application, wherein the insulating substrate is a glass substrate. 2 3 · The manufacturing method as described in item 21 of the patent application scope, wherein the source / drain layer is a highly doped semiconductor layer. 2 4 · The manufacturing method as described in item 23 of the scope of patent application, wherein the highly doped semiconductor layer is completed with highly doped polycrystalline silicon. 25. The manufacturing method as described in item 21 of the patent application, wherein the source / drain layer includes a drain structure, a channel, and a source structure. 2 6 · The manufacturing method as described in item 25 of the scope of patent application, wherein the degree of the channel is equal to the length of the main gate conductor structure, the thickness of the sub-gate insulation layer, and the sub-gate conductor structure The sum of its length. 2 7 · π The manufacturing method described in item 21 of the scope of patent application, wherein the main gate, and the edge layer are selected from the group consisting of the following silicon nitride (siNx), silicon oxide (SiOx), and nitrogen Page 18 538529 ___Case No. 91115746 __Year_Month_Revision_ VI. One or any of insulating materials such as silicon oxide (SiOxNy), oxide button (TaOx), and aluminum oxide (AlOx) To complete. 28. The manufacturing method as described in item 21 of the scope of patent application, wherein the sub-gate insulating layer is selected from the group consisting of the following silicon nitride (S i NX), silicon oxide (S i Ox), and silicon oxynitride ( One or any combination of insulating materials such as SiOxNy), oxide button (TaOx), and aluminum oxide (AlOx). 2 9 · —A thin film transistor structure including: an insulating substrate; a source / drain layer on the insulating substrate; a main closed-pole insulating layer on the source and electrode layers; a main gate conductor Structure and a sub-gate insulation layer on the first gate insulation layer; and a sub-gate conductor structure on the sub-gate insulation layer, which is formed by a part of the first sub-gate insulation layer and The main gate conductor structure is isolated. 30. The thin film transistor structure according to item 29 of the patent application scope, wherein the insulating substrate is a glass substrate. 3 1 · The thin film transistor structure described in item 29 of the patent application scope, wherein the source / electrode layer is a highly doped semiconductor layer. 32. The thin-film transistor structure according to item 31 of the scope of patent application, wherein the highly doped semiconductor layer is made of highly doped polycrystalline silicon. 3 3 · The thin film transistor structure according to item 29 of the patent application scope, wherein the source / drain layer includes a drain structure, a channel, and a source structure. 3 4 · The thin film transistor structure described in item 33 of the scope of patent application, wherein 538529 _Case No. 91115746_Amended in January of the year_ 6. The scope of the patent application The length of the channel is equal to the length of the main gate conductor structure, the thickness of the sub-gate insulation layer, and the length of the sub-gate conductor structure sum. 3 5. The thin film transistor structure according to item 29 of the scope of the patent application, wherein the main gate insulating layer is selected from the group consisting of the following silicon nitride (Si Nx), silicon oxide (SiOx), and oxynitride (SiOxNy), oxidized group (TaOx), and oxidized I (A 1 Ox) insulation materials such as one or any combination of them. 3 6. The thin-film transistor structure according to item 29 of the scope of the patent application, wherein the sub-gate insulating layer is selected from the group consisting of the following nitrides (Si i NX), oxides (SiOx), and oxynitrides One or any combination of insulating materials such as SiOxNy, TaOx, and A1 Ox. Page 20