CN107221563A - A kind of bottom gate self-alignment structure metal oxide thin-film transistor and preparation method thereof - Google Patents
A kind of bottom gate self-alignment structure metal oxide thin-film transistor and preparation method thereof Download PDFInfo
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- CN107221563A CN107221563A CN201710327144.1A CN201710327144A CN107221563A CN 107221563 A CN107221563 A CN 107221563A CN 201710327144 A CN201710327144 A CN 201710327144A CN 107221563 A CN107221563 A CN 107221563A
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- metal oxide
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 81
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 81
- 239000010409 thin film Substances 0.000 title claims abstract description 61
- 238000002360 preparation method Methods 0.000 title claims description 30
- 239000000126 substance Substances 0.000 claims abstract description 68
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 63
- 238000002161 passivation Methods 0.000 claims abstract description 62
- 239000012212 insulator Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000010408 film Substances 0.000 claims abstract description 40
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- 239000011737 fluorine Substances 0.000 claims abstract description 18
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000001257 hydrogen Substances 0.000 claims abstract description 17
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 17
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000009413 insulation Methods 0.000 claims abstract description 13
- 238000011068 loading method Methods 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 9
- 230000000802 nitrating effect Effects 0.000 claims abstract description 8
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 claims abstract description 5
- 241000720974 Protium Species 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 33
- 238000000137 annealing Methods 0.000 claims description 32
- 230000008021 deposition Effects 0.000 claims description 24
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims description 20
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 18
- 238000005286 illumination Methods 0.000 claims description 11
- 229910021529 ammonia Inorganic materials 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 10
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 9
- 238000007687 exposure technique Methods 0.000 claims description 9
- 239000001272 nitrous oxide Substances 0.000 claims description 9
- 229910000077 silane Inorganic materials 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 8
- 230000006835 compression Effects 0.000 claims description 7
- 238000007906 compression Methods 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 238000002156 mixing Methods 0.000 claims 1
- 239000007789 gas Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000005300 metallic glass Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- BHHYHSUAOQUXJK-UHFFFAOYSA-L zinc fluoride Chemical compound F[Zn]F BHHYHSUAOQUXJK-UHFFFAOYSA-L 0.000 description 2
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- VBXWCGWXDOBUQZ-UHFFFAOYSA-K diacetyloxyindiganyl acetate Chemical compound [In+3].CC([O-])=O.CC([O-])=O.CC([O-])=O VBXWCGWXDOBUQZ-UHFFFAOYSA-K 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- LKRFCKCBYVZXTC-UHFFFAOYSA-N dinitrooxyindiganyl nitrate Chemical class [In+3].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O LKRFCKCBYVZXTC-UHFFFAOYSA-N 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000002779 inactivation Effects 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- DJWUNCQRNNEAKC-UHFFFAOYSA-L zinc acetate Chemical class [Zn+2].CC([O-])=O.CC([O-])=O DJWUNCQRNNEAKC-UHFFFAOYSA-L 0.000 description 1
- 235000013904 zinc acetate Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The invention discloses a kind of bottom gate self-alignment structure metal oxide thin-film transistor, including substrate, the grid being cascading on substrate, gate insulation layer, metal oxide semiconductor layer, etching barrier layer and insulator passivation layer containing doped chemical, and be arranged on the outside of insulator passivation layer containing doped chemical and the source electrode being connected respectively with metal oxide semiconductor layer and drain electrode, the insulator passivation layer containing doped chemical is any one in fluorine-doped silica film layer, fluorine doped silicon nitride film layer, nitrating silicon oxide film layer and hydrogen loading silicon nitride film layer；Doped chemical in the insulator passivation layer containing doped chemical is at least one of fluorine element, nitrogen and protium.Present invention process is simple, uniformity is good, reproducible, large area and stability high.
Description
Technical field
The present invention relates to display field, and in particular to a kind of bottom gate self-alignment structure metal oxide thin-film transistor and its
Preparation method.
Background technology
Metal oxide thin-film transistor turns into a kind of new core component in Display Technique, has been widely used in
In the flat display field such as display of organic electroluminescence and liquid crystal display.The flat display field paid close attention to both at home and abroad at present
Emphasis is to improve display quality, realizes it to large area, high-resolution, slimming, flexible rollableization.Therefore, film crystal
Manifold technology is to determine that can FPD realize large scale, high-resolution key.Compared with traditional silicon-based film transistor,
Metal oxide thin-film transistor has the advantages that broad stopband, high uniformity, high stability, high field-effect mobility, Er Qiejin
Belong to oxide thin film transistor production technology not only can compatible existing silicon substrate FPD technology, can also realize low
Even on cheap substrate prepared by large area at room temperature for temperature, is conducive to industrialized production, and cater to modernization Display Technique
Development trend.
Report the metal-oxide film using amorphous indium gallium zinc oxide as active layer first from Hosono in 2004 etc.
Since transistor, in last decade, amorphous metal oxide semiconductor turns into the study hotspot of thin film transistor active layer, for example
Zinc oxide, tin indium oxide, indium tin zinc oxide, indium oxide and gallium oxide zinc etc..And compared with traditional silica-base material, broad stopband
Amorphous metal oxide semi-conducting material has relatively low defect state density.This causes metal oxide thin-film transistor scene effect
Advantage is obvious in terms of mobility, light transmission rate, homogeneity, while there is preferable characteristic working curve, including low-threshold power
Pressure, low off-state current, steep subthreshold swing, insignificant dielectric hysteresis etc..
During metal oxide thin-film transistor is prepared, its structure, the preparation condition of each layer film, photoetching technique,
Defect type and its density of states and active in the factors affect metal-oxide semiconductor (MOS) forbidden band such as lithographic method and method for annealing
Layer and interfacial dielectric layer charge trap density, so as to influence MOTFT working characteristics and stability.In current flat panel display field
In, bottom gate (reciprocal cross stack-type) structure is most widely used.For the bottom gate thin film transistor without etching barrier layer and passivation layer,
If active layer back of the body channel surface is exposed in air, thin film transistor (TFT) stability is produced effects because of field cause absorption/desorption should be easily by air
In oxygen and steam influence.However, stabilization of equipment performance can be effectively improved by preparing etching barrier layer and passivation layer.In recent years
Come, domestic and international researcher is used as passivation layer, such as silica, silicon nitride, titanium oxide and aluminum oxide using various insulating materials
Deng.In addition, one of reciprocal cross stack-type structure has the disadvantage there are overlapping coverage sectors between grid and source and drain areas, posted so as to produce
Raw electric capacity, causes the high frequency characteristics of device to degenerate, and influences the operating rate of thin film transistor (TFT), causes thin film transistor backplane
Middle signal delay.Meanwhile, parasitic capacitance can also influence to drive the work electricity of thin film transistor (TFT) in each pixel of flat-panel monitor
Pressure, has a strong impact on the luminous uniformity of pixel.Therefore, it is realization large area of future generation, high-resolution, large-scale integrated flat board
Display, perfect alignment structure between grid and source and drain areas can be prepared by the back-exposure technology of substrate and eliminates parasitic electricity
Hold, improve metal oxide thin-film transistor circuit operating rate, improve pixel uniformly light-emitting in flat-panel monitor.However,
During thin film transistor (TFT) is prepared, its structure, the preparation condition of each layer film, photoetching technique, lithographic method and method for annealing
Deng defect type and its density of states in factors affect metal-oxide semiconductor (MOS) forbidden band and active layer and interfacial dielectric layer electric charge
Trap density, so as to influence the working characteristics and stability of transistor.
Because in switch/driving liquid crystal display and display of organic electroluminescence, thin film transistor (TFT) is often operated in
Negative gate bias is simultaneously exposed under backlight or natural light, while thin film transistor (TFT) is acted on by the fuel factor of substrate, especially negative
Bias under the conditions of irradiation stress and positive bias temperature stress, threshold voltage shift can be caused.Report that threshold drift is attributed to electricity
Lotus is bound by gate insulation layer, active layer and interfacial dielectric layer, active layer, barrier layer and active layer interface, the deep acceptor class produced
Several aspects such as type defect, this is the key factor for causing thin film transistor (TFT) stability degradation.
The research of each panel business and scientific research institution is made a general survey of, is fundamentally to solve metal oxide thin-film transistor stability
Problem, can realize the inactivation of defect present in oxide semiconductor, such as hydrogen annealing is handled, hydrogen by introducing new element
Corona treatment etc..Existing introducing new element method is harsher in the experiment condition needed for implementation process at present, leads to
Often need HTHP, very expensive instrument and equipment or complex process, and lack of homogeneity, repeatability are poor.Therefore, realize
Technique is simple, low cost, large area and high-performance MOTFT controllable preparation are the significant challenges currently faced.
The content of the invention
It is an object of the invention to provide a kind of bottom gate self-alignment structure metal oxide thin-film transistor and its preparation side
Method, to overcome the defect that above-mentioned prior art is present, present invention process is simple, uniformity is good, reproducible, large area and stably
Property it is high.
To reach above-mentioned purpose, the present invention is adopted the following technical scheme that：
A kind of bottom gate self-alignment structure metal oxide thin-film transistor, including substrate, be cascading on substrate
Grid, gate insulation layer, metal oxide semiconductor layer, etching barrier layer and insulator passivation layer containing doped chemical, Yi Jishe
Put on the outside of insulator passivation layer containing doped chemical and the source electrode being connected respectively with metal oxide semiconductor layer and drain electrode, it is described
Insulator passivation layer containing doped chemical be fluorine-doped silica film layer, fluorine doped silicon nitride film layer, nitrating silicon oxide film layer and
Any one in hydrogen loading silicon nitride film layer；Doped chemical in the insulator passivation layer containing doped chemical is fluorine element,
At least one of nitrogen and protium.
Further, the metal oxide semiconductor layer includes source contact area, drain contact region, and connection source electrode
Contact zone and the channel region of drain contact region；The insulator passivation layer containing doped chemical connects in correspondence source contact area and drain electrode
The position for touching area is respectively equipped with a through hole run through, and the source electrode and drain electrode are respectively through the through hole.
Further, the field-effect mobility of described bottom gate self-alignment structure metal oxide thin-film transistor be 12~
15cm2V-1s-1, cut-in voltage is less than 0.5V, and subthreshold swing is less than 0.2, in 20V positively biaseds compression 104S conditions lower threshold value electricity
Pressure drift is less than 0.1V, in -20V back bias voltages 460nm illumination stress 104Threshold voltage shift is less than 0.2V under the conditions of s.
A kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor, comprises the following steps：
Step one：Sequentially formed on substrate after grid, gate insulation layer, metal oxide semiconductor layer, using grid to cover
Template is using dorsad UV exposure techniques formation etching barrier layer；
Step 2：Insulator passivation layer containing doped chemical is prepared, insulator passivation layer containing doped chemical includes insulator master
Body and doped chemical, the doped chemical are formed in chemical vapor deposition method simultaneously with insulator body；
Step 3：Insulator passivation layer containing doped chemical is punched so that metal oxide semiconductor layer two ends are each
There is a surface exposed to the open air；Then deposition source electrode and drain electrode, the source electrode and drain electrode are blunt respectively through insulator containing doped chemical
The hole changed on layer is connected with metal oxide semiconductor layer；
Step 4：Doped chemical in annealing, insulator passivation layer containing doped chemical is by barrier of etching barrier layer to gold
Category oxide semiconductor layer is not etched the part and etching barrier layer thermal diffusion that barrier layer blocks.
Further, the atmosphere of chemical vapor deposition method includes at least one in ocratation, ammonia, nitrogen
Kind, the doped chemical in the insulator passivation layer containing doped chemical is at least one of fluorine, nitrogen, hydrogen element.
Further, the atmosphere of chemical vapor deposition method is silane, nitrous oxide and nitrogen, and what is formed contains
Doped chemical insulator passivation layer is nitrating silicon oxide film layer.
Further, the atmosphere of chemical vapor deposition method is ocratation, nitrous oxide and nitrogen, is formed
Insulator passivation layer containing doped chemical be fluorine-doped silica film layer.
Further, the atmosphere of chemical vapor deposition method is ocratation, ammonia and nitrogen, and containing for being formed is mixed
Miscellaneous element insulator passivation layer is fluorine doped silicon nitride film layer.
Further, the atmosphere of chemical vapor deposition method is silane, ammonia and nitrogen, the member containing doping formed
Plain insulator passivation layer is hydrogen loading silicon nitride film layer.
Further, the thermal diffusion in step 4 is heat-treated using short annealing mode, and annealing temperature is 250-
350 DEG C, annealing time is 60-180 minutes.
Compared with prior art, the present invention has following beneficial technique effect：
The self-alignment structure metal oxide thin-film transistor of the present invention, by dorsad UV exposure techniques, using bottom gate as
Mask plate formation etching barrier layer, while preparing passivation layer using plasma enhanced chemical vapor deposition method, passes through regulation and control
Plasma enhanced chemical vapor deposition method presoma atmosphere carries out ion implanting to improve film to source-drain electrode and active layer
The structure of transistor, optics, electricity, thermal stability；Its structurally and functionally principle it is as described below.(1) self-alignment structure is not only
The parasitic capacitance between source-drain electrode and grid is avoided that, and can effectively control film crystal pipe size, so as to improve flat board
The resolution ratio of display；(2) by adjusting presoma atmosphere in plasma enhanced chemical vapor deposition method deposition process, realize
The processing of source-drain electrode regional metal sull surface plasma, reduces source-drain electrode surface roughness, while reducing metal
Potential barrier between sull and source-drain electrode；(3) plasma enhanced chemical vapor deposition method experiment parameter is adjusted, is realized
Element is introduced to source-drain electrode regional metal sull ion implanting ability, increases source-drain electrode regional carrier concentration,
Obtain low resistivity metal oxide film；(4) thickness of optimization etching barrier layer and annealing time, introducing element is caused
It is uniformly injected into and is diffused into metal oxide semiconductor layer and etch stopper bed boundary, metal oxide semiconductor layer, metal oxidation
Between thing semiconductor layer and gate insulator layer interface, diffusion element can fill Lacking oxygen position in metal-oxide semiconductor (MOS) and reduce
Metal-oxide semiconductor (MOS) defect state density, while the effectively trap of reduction metal oxide semiconductor films and interfacial dielectric layer
Density, so as to improve thin film transistor (TFT) service behaviour and optics and electrical stability.
The inventive method forms etching barrier layer using grid as mask plate by dorsad UV exposure techniques, utilize etc. from
While daughter enhancing chemical vapour deposition technique simply prepares fluorine-containing, nitrogen or protium passivation layer, directly to source-drain electrode region
Uniform ion injection is carried out, in addition, being etched by regulating and controlling plasma enhanced chemical vapor deposition method presoma atmosphere and optimization
Barrier layer thickness and annealing time, uniform diffusion of certain element in thin film transistor active layer can be realized again, from
And improve the stability of thin film transistor (TFT).The self-alignment type metal oxide thin-film transistor that this inventive method is realized has technique
Simply, uniformity is good, large area, the characteristics of reproducible, stability is high.
Further, the compatible existing FPD technology of the inventive method, it is adaptable to industrialized production, improves life
Produce efficiency.
Further, the present invention can realize heat diffusion treatment to source-drain electrode in thin film transistor (TFT) and active layer, be applicable
Scope is wide, can obtain preferable high stability self-alignment structure metal oxide thin-film transistor.
Further, the present invention is improving the same of oxide semiconductor layer quality in 250-350 DEG C of heat treatment environment
When, the stability for effectively improving thin film transistor (TFT) is acted on by thermal diffusion.
Brief description of the drawings
Fig. 1 is the structural representation of the bottom gate self-alignment structure metal oxide thin-film transistor of the present invention.
In figure：1 is substrate, and 2 be grid, and 3 be gate insulation layer, and 4 be metal oxide semiconductor layer, and 40 be channel region, 41
It is drain contact region for source contact area, 42,5 be etching barrier layer, and 6 be insulator passivation layer containing doped chemical, and 7 be source electrode, 8
For drain electrode.
Embodiment
The present invention is described in further detail below：
A kind of bottom gate self-alignment structure metal oxide thin-film transistor, its field-effect mobility is more than 12cm2V-1s-1, open
Voltage is opened less than 0.5V, subthreshold swing is less than 0.2, in 20V positively biaseds compression 104Threshold voltage shift is less than under the conditions of s
0.1V, in -20V back bias voltages 460nm illumination stress 104Threshold voltage shift is less than 0.2V, including substrate 1, successively under the conditions of s
It is stacked grid 2, gate insulation layer 3, metal oxide semiconductor layer 4, etching barrier layer 5 and member containing doping on substrate 1
Plain insulator passivation layer 6, and be arranged on the outside of insulator passivation layer containing doped chemical 6 and respectively with metal-oxide semiconductor (MOS)
The source electrode 7 of the connection of layer 4 and drain electrode 8, the insulator passivation layer containing doped chemical 6 is fluorine-doped silica film layer, fluorine doped is nitrogenized
Any one in silicon membrane layer, nitrating silicon oxide film layer, hydrogen loading silicon oxide film layer and hydrogen loading silicon nitride film layer；It is described
Doped chemical in insulator passivation layer containing doped chemical 6 is at least one of fluorine element, nitrogen and protium.
Wherein, metal oxide semiconductor layer 4 includes source contact area 41, drain contact region 42, and connection source electrode connects
Touch the channel region 40 of area 41 and drain contact region 42；The insulator passivation layer containing doped chemical 6 is in correspondence source contact area 41
A through hole run through is respectively equipped with the position of drain contact region 42, the source electrode 7 and drain electrode 8 are respectively through the through hole.
A kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor, comprises the following steps：
Step one：Sequentially form on substrate 1 after grid 2, gate insulation layer 3, metal oxide semiconductor layer 4, with grid 2
It is that mask plate forms etching barrier layer 5 using dorsad UV exposure techniques；
Step 2：Insulator passivation layer containing doped chemical 6 is prepared, insulator passivation layer containing doped chemical 6 includes insulator
Main body and doped chemical, the doped chemical are formed in chemical vapor deposition method simultaneously with insulator body；Chemical gaseous phase
The atmosphere of depositing operation includes at least one of ocratation, hydrogen, nitrogen, the passivation of insulator containing doped chemical
Doped chemical in layer 6 is at least one of fluorine, nitrogen, hydrogen element；
When the atmosphere of chemical vapor deposition method is silane, nitrous oxide and nitrogen, the member containing doping formed
Plain insulator passivation layer 6 is hydrogen loading silicon oxide film layer；
When the atmosphere of chemical vapor deposition method is ocratation, nitrous oxide and nitrogen, containing for being formed is mixed
Miscellaneous element insulator passivation layer 6 is fluorine-doped silica film layer；
When the atmosphere of chemical vapor deposition method is ocratation, ammonia and nitrogen, what is formed contains doped chemical
Insulator passivation layer 6 is fluorine doped silicon nitride film layer；
When the atmosphere of chemical vapor deposition method is silane, ammonia and nitrogen, what is formed insulate containing doped chemical
Body passivation layer 6 is hydrogen loading silicon nitride film layer；
Step 3：Insulator passivation layer containing doped chemical 6 is punched so that the two ends of metal oxide semiconductor layer 4
Respectively there is a surface exposed to the open air；Then deposition source electrode 7 and drain electrode 8, the source electrode 7 and drain electrode 8 are respectively through exhausted containing doped chemical
Hole on edge body passivation layer 6 is connected with metal oxide semiconductor layer 4；
Step 4：Annealing, doped chemical in insulator passivation layer containing doped chemical 6 with etching barrier layer 5 be barrier to
Metal oxide semiconductor layer 4 is not etched the part and the thermal diffusion of etching barrier layer 5 that barrier layer 5 blocks, and thermal diffusion is to adopt
It is heat-treated with short annealing mode, annealing temperature is 250-350 DEG C, annealing time is 60-180 minutes.
The present invention is described in further detail with reference to embodiment：
Embodiment 1
A kind of bottom gate self-alignment structure metal oxide thin-film transistor preparation method, comprises the following steps：
1) preparation of metal oxide semiconductor films：Grid 2, gate insulation layer 3 are prepared based on Fig. 1 structures on substrate 1
Afterwards, when preparing metal oxide semiconductor layer 4 using magnetically controlled sputter method, so that target is indium gallium zinc as an example, deposition gas
Body atmosphere is argon gas and oxygen, and its ratio is 29.4:0.6sccm, depositing temperature is 150 DEG C, and deposition power is 180W, deposition pressure
It is by force 1Pa, deposit thickness is 50nm.
2) reference picture 1 prepares etching barrier layer 5 after, and thickness is 150nm.
3) it is mask plate with grid 2 using dorsad UV exposure techniques, with reference to photoetching technique, forms self-alignment structure etching
Barrier layer 5, performs etching patterning to metal oxide semiconductor layer 4 afterwards.
4) preparation of insulator passivation layer containing doped chemical 6：In step 3) after, it is heavy using Plasma Enhanced Chemical Vapor
Area method prepares fluorine doped silicon nitride, and deposition gases atmosphere is ocratation, ammonia, nitrogen, its flow is respectively 2,50,120sccm,
Deposition pressure is 110Pa, and deposition power is 50W, and depositing temperature is 170 DEG C, and deposit thickness is 100nm.
5) in step 4) after, it is sequentially prepared source electrode 7, drain electrode 8.
6) thin film transistor (TFT) is heat-treated using short annealing mode, annealing temperature is 350 DEG C, annealing time is
180 minutes, annealing atmosphere was nitrogen.
The field-effect mobility of self-alignment structure indium gallium zinc thin film transistor (TFT) with fluorine doped silicon nitride passivation is
12cm2V-1s-1, cut-in voltage is 0.5V, and subthreshold swing is less than 0.2；In 20V positively biaseds compression 104S condition lower threshold voltages
Drift is less than 0.1V, in the illumination of -20V back bias voltages (460nm) stress 104Threshold voltage shift is less than 0.2V under the conditions of s.Its illumination
Stability can compare favourably with existing commercial polycrystalline SiTFT.
Embodiment 2
A kind of bottom gate self-alignment structure metal oxide thin-film transistor preparation method, comprises the following steps：
1) preparation of metal oxide semiconductor films：Grid 2, gate insulation layer 3 are prepared based on Fig. 1 structures on substrate 1
Afterwards, when preparing metal oxide semiconductor layer 4 using antivacuum chemical vapour deposition technique, by taking indium zinc oxide as an example, precursor liquid
For zinc fluoride, indium acetate, solvent is water and methanol, and respectively 10 and 90mL is stirred 3 hours, afterwards with 0.2 μm of filter screen at room temperature
Filtering.Sedimentary condition is as follows, and deposition gases are air, and depositing temperature is 350 DEG C, and deposit thickness is 45nm.
2) reference picture 1 prepares barrier layer 5 after, and thickness is 50nm.
3) it is mask plate with grid 2 using dorsad UV exposure techniques, with reference to photoetching technique, forms self-alignment structure etching
Barrier layer 5, performs etching patterning to metal oxide semiconductor layer 4 afterwards.
4) preparation of insulator passivation layer containing doped chemical 6：In step 3) after, it is heavy using Plasma Enhanced Chemical Vapor
Area method prepares fluorine-doped silica, and deposition gases atmosphere is ocratation, nitrous oxide, nitrogen, its flow is respectively 2,100,
120sccm, deposition pressure is 110Pa, and deposition power is 50W, and depositing temperature is 170 DEG C, and deposit thickness is 100nm.
5) in step 4) after, it is sequentially prepared source electrode 7, drain electrode 8.
6) thin film transistor (TFT) is heat-treated using short annealing mode, annealing temperature is 250 DEG C, annealing time is
120 minutes, annealing atmosphere was nitrogen.
The field-effect mobility of self-alignment structure indium zinc oxide thin film transistor (TFT) with fluorine-doped silica passivation layer is
14cm2V-1s-1, cut-in voltage is 0.5V, and subthreshold swing is less than 0.2；In 20V positively biaseds compression 104S condition lower threshold voltages
Drift is less than 0.1V, in the illumination of -20V back bias voltages (460nm) stress 104Threshold voltage shift is less than 0.2V under the conditions of s.Its illumination
Stability can compare favourably with existing commercial polycrystalline SiTFT.
Embodiment 3
A kind of bottom gate self-alignment structure metal oxide thin-film transistor preparation method, comprises the following steps：
1) preparation of metal oxide semiconductor films：Grid 2, gate insulation layer 3 are prepared based on Fig. 1 structures on substrate 1
Afterwards, when preparing metal oxide semiconductor layer 4 using spin-coating method, by taking indium zinc oxide as an example, precursor liquid be 0.1M zinc acetates,
0.1M indium nitrates, solvent is water, is stirred 3 hours at room temperature, afterwards with 0.2 μm of strainer filtering.Afterwards in 4000rpm condition backspins
Apply 30s, afterwards under air atmosphere 250 DEG C be heat-treated 1 hour.
2) reference picture 1 prepares barrier layer 5 after, and thickness is 100nm.
3) it is mask plate with grid 2 using dorsad UV exposure techniques, with reference to photoetching technique, forms self-alignment structure etching
Barrier layer 5, performs etching patterning to metal oxide semiconductor layer 4 afterwards.
4) preparation of insulator passivation layer containing doped chemical 6：In step 3) after, it is heavy using Plasma Enhanced Chemical Vapor
Area method prepares hydrogen loading silicon nitride, and deposition gases atmosphere is silane, ammonia, nitrogen, its flow is respectively 2,100,120sccm, sink
It is 110Pa by force to overstock, and deposition power is 50W, and depositing temperature is 170 DEG C, and deposit thickness is 100nm.
5) in step 4) after, it is sequentially prepared source electrode 7, drain electrode 8.
6) thin film transistor (TFT) is heat-treated using short annealing mode, annealing temperature is 300 DEG C, annealing time is
120 minutes, annealing atmosphere was nitrogen.
The field-effect mobility of self-alignment structure indium zinc oxide thin film transistor (TFT) with hydrogen loading silicon nitride passivation is
12cm2V-1s-1, cut-in voltage is 0.4V, and subthreshold swing is less than 0.2；In 20V positively biaseds compression 104S condition lower threshold voltages
Drift is less than 0.1V, in the illumination of -20V back bias voltages (460nm) stress 104Threshold voltage shift is less than 0.2V under the conditions of s.Its illumination
Stability can compare favourably with existing commercial polycrystalline SiTFT.
Embodiment 4
A kind of bottom gate self-alignment structure metal oxide thin-film transistor preparation method, comprises the following steps：
1) preparation of metal oxide semiconductor films：The self-alignment structure thin-film transistor structure of reference picture 1 is on substrate 1
Grid 2, gate insulation layer 3 are prepared, when preparing metal oxide semiconductor layer 4 using magnetically controlled sputter method, using target as indium oxide
Exemplified by tin zinc, its atom number ratio is 1:1:1, deposition gases atmosphere is argon gas, oxygen, and its flow is respectively 15 and 15sccm,
Depositing temperature is 150 DEG C, and deposition power is 150W, and deposition pressure is 1Pa, and deposit thickness is 50nm.
2) preparation on barrier layer 5：In step 1) after, barrier layer 5 is prepared using plasma reinforced chemical vapour deposition method,
Deposition gases atmosphere is silane, nitrous oxide, nitrogen, its flow is respectively 2,100,120sccm, deposition pressure is 110Pa,
Deposition power is 50W, and depositing temperature is 170 DEG C, and deposit thickness is 50nm.
3) it is mask plate with grid 2 using dorsad UV exposure techniques, with reference to photoetching technique, forms self-alignment structure etching
Barrier layer 5, performs etching patterning to metal oxide semiconductor layer 4 afterwards.
4) preparation of insulator passivation layer containing doped chemical 6：In step 3) after, it is heavy using Plasma Enhanced Chemical Vapor
Area method prepares nitrating silica, and deposition gases atmosphere is silane, nitrous oxide, nitrogen, its flow is respectively 2,50,
120sccm, deposition pressure is 110Pa, and deposition power is 50W, and depositing temperature is 170 DEG C, and deposit thickness is 100nm.
5) in step 4) after, it is sequentially prepared source electrode 7, drain electrode 8.
6) thin film transistor (TFT) is heat-treated using short annealing mode, annealing temperature is 350 DEG C, and annealing time is 60
Minute, annealing atmosphere is nitrogen.
The field-effect mobility of self-alignment structure indium tin zinc oxide thin film transistor with nitrating silicon oxide passivation layer is
15cm2V-1s-1, cut-in voltage is 0.3V, and subthreshold swing is less than 0.2；In 20V positively biaseds compression 104S condition lower threshold voltages
Drift is less than 0.1V, in the illumination of -20V back bias voltages (460nm) stress 104Threshold voltage shift is less than 0.1V under the conditions of s.Its illumination
Stability can compare favourably with existing commercial polycrystalline SiTFT.
What the present invention was realized has high stability self-alignment structure metal oxide thin-film transistor device, can be applied to master
Dynamic matrix organic LED display and liquid crystal display and flexibility, portable type electronic product field.Need explanation
It is that experiment parameter, working environment, test condition, device size, ratio for being related in present example etc. are not intended to limit gold
Belong to the preparation technology of oxide thin film transistor device, in actual production process, corresponding tune can be made as the case may be
It is whole.Above example is merely illustrative of the technical solution of the present invention rather than limiting the scope of the invention, although right in example
The present invention is made that detailed description, and the scientific research technological staff of this area should be appreciated that the experimental program that can be listed to the present invention
Modify or replace, without departing from the spirit and scope of technical solution of the present invention.
Claims (10)
1. a kind of bottom gate self-alignment structure metal oxide thin-film transistor, it is characterised in that including substrate (1), stack gradually
The grid (2) that is arranged on substrate (1), gate insulation layer (3), metal oxide semiconductor layer (4), etching barrier layer (5) and contain
Doped chemical insulator passivation layer (6), and be arranged on the outside of insulator passivation layer containing doped chemical (6) and respectively with metal oxygen
The source electrode (7) of compound semiconductor layer (4) connection and drain electrode (8), the insulator passivation layer containing doped chemical (6) aoxidize for fluorine doped
Any one in silicon membrane layer, fluorine doped silicon nitride film layer, nitrating silicon oxide film layer and hydrogen loading silicon nitride film layer；It is described
Doped chemical in insulator passivation layer containing doped chemical (6) is at least one of fluorine element, nitrogen and protium.
2. a kind of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 1, it is characterised in that institute
Stating metal oxide semiconductor layer (4) includes source contact area (41), drain contact region (42), and connection source contact area
(41) and drain contact region (42) channel region (40)；The insulator passivation layer containing doped chemical (6) is in correspondence source contact
The position of area (41) and drain contact region (42) is respectively equipped with a through hole run through, the source electrode (7) and drain electrode (8) respectively through
The through hole.
3. a kind of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 1, it is characterised in that institute
The field-effect mobility for the bottom gate self-alignment structure metal oxide thin-film transistor stated is 12~15cm2V-1s-1, cut-in voltage
Less than 0.5V, subthreshold swing is less than 0.2, in 20V positively biaseds compression 104Threshold voltage shift is less than 0.1V under the conditions of s ,-
20V back bias voltages 460nm illumination stress 104Threshold voltage shift is less than 0.2V under the conditions of s.
4. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor, it is characterised in that including following step
Suddenly：
Step one：Sequentially formed on substrate (1) after grid (2), gate insulation layer (3), metal oxide semiconductor layer (4), with
Grid (2) is mask plate using dorsad UV exposure techniques formation etching barrier layer (5)；
Step 2：Insulator passivation layer containing doped chemical (6) is prepared, insulator passivation layer containing doped chemical (6) includes insulator
Main body and doped chemical, the doped chemical are formed in chemical vapor deposition method simultaneously with insulator body；
Step 3：Insulator passivation layer containing doped chemical (6) is punched so that metal oxide semiconductor layer (4) two ends
Respectively there is a surface exposed to the open air；Then deposition source electrode (7) and drain electrode (8), the source electrode (7) and drains (8) respectively through containing mixing
Hole on miscellaneous element insulator passivation layer (6) is connected with metal oxide semiconductor layer (4)；
Step 4：Annealing, doped chemical in insulator passivation layer containing doped chemical (6) with etching barrier layer (5) be barrier to
Metal oxide semiconductor layer (4) is not etched the part and etching barrier layer (5) thermal diffusion that barrier layer (5) blocks.
5. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 4, its
It is characterised by, the atmosphere of chemical vapor deposition method includes at least one of ocratation, ammonia, nitrogen, described to contain
Doped chemical in doped chemical insulator passivation layer (6) is at least one of fluorine, nitrogen, hydrogen element.
6. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 4, its
It is characterised by, the atmosphere of chemical vapor deposition method is silane, nitrous oxide and nitrogen, and what is formed contains doped chemical
Insulator passivation layer (6) is nitrating silicon oxide film layer.
7. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 4, its
It is characterised by, the atmosphere of chemical vapor deposition method is ocratation, nitrous oxide and nitrogen, and what is formed contains doping
Element insulator passivation layer (6) is fluorine-doped silica film layer.
8. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 4, its
It is characterised by, the atmosphere of chemical vapor deposition method is ocratation, ammonia and nitrogen, and what is formed is exhausted containing doped chemical
Edge body passivation layer (6) is fluorine doped silicon nitride film layer.
9. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 4, its
It is characterised by, the atmosphere of chemical vapor deposition method is silane, ammonia and nitrogen, the insulator containing doped chemical formed
Passivation layer (6) is hydrogen loading silicon nitride film layer.
10. a kind of preparation method of bottom gate self-alignment structure metal oxide thin-film transistor according to claim 4, its
It is characterised by, the thermal diffusion in step 4 is heat-treated using short annealing mode, annealing temperature is 250-350 DEG C, is moved back
The fiery time is 60-180 minutes.
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| CN108258021A (en) * | 2018-01-22 | 2018-07-06 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), preparation method, array substrate and display device |
| CN108878540A (en) * | 2018-07-12 | 2018-11-23 | 南方科技大学 | A kind of bottom gate thin film transistor and preparation method thereof |
| CN110098261A (en) * | 2019-05-05 | 2019-08-06 | 华南理工大学 | A kind of thin film transistor and its manufacturing method, display base plate, panel, device |
| CN112635572A (en) * | 2020-12-24 | 2021-04-09 | 广东省科学院半导体研究所 | Thin film transistor, preparation method thereof and display device |
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| US7709894B2 (en) * | 2001-07-17 | 2010-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including a transistor with a gate electrode having a taper portion |
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