CN110120349A - The source-drain electrode and crystal tube preparation method of InGaZnO thin film transistor (TFT) - Google Patents
The source-drain electrode and crystal tube preparation method of InGaZnO thin film transistor (TFT) Download PDFInfo
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- CN110120349A CN110120349A CN201910402464.8A CN201910402464A CN110120349A CN 110120349 A CN110120349 A CN 110120349A CN 201910402464 A CN201910402464 A CN 201910402464A CN 110120349 A CN110120349 A CN 110120349A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 title claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010936 titanium Substances 0.000 claims abstract description 16
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 12
- 239000010931 gold Substances 0.000 claims abstract description 12
- 238000010894 electron beam technology Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 7
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 7
- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000000428 dust Substances 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000005416 organic matter Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 12
- 229910052802 copper Inorganic materials 0.000 abstract description 9
- 239000010949 copper Substances 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 4
- 238000012360 testing method Methods 0.000 abstract description 4
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 230000001276 controlling effect Effects 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 230000001105 regulatory effect Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 239000013077 target material Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
- H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of source-drain electrode of InGaZnO thin film transistor (TFT) and crystal tube preparation methods, source electrode and drain electrode successively evaporates generation titanium using electron beam by mask plate and layer gold is prepared, the method overcome copper electrodes in the prior art, and easy to oxidize, copper electrode is deposited on the defect that copper atom is spread to oxide later in active layer of metal oxide, has the characteristics that high conductivity.The result shows that, the threshold voltage for the transistor being prepared by this method is 4.5V, and subthreshold swing is smaller, grid bias V after testgsTo the leakage current I of devicedsThere is good regulating and controlling effect, device pinch-off behavior is good.
Description
Technical field
The present invention relates to a kind of source-drain electrode of InGaZnO thin film transistor (TFT) and crystal tube preparation methods.
Background technique
Since the 21th century, electronic industry rises to global major industry.It is special with the progress of large scale integrated circuit
It is not that with the development of display technology, tech electronic product has been directed towards Highgrade integration and miniature multi-functionization develops, and new
The exploitation of material and its thin film technique become the micromation of realization system and integrated key.
With amorphous indium gallium zinc oxide InGaZnO (abbreviation a-IGZO or IGZA) display etc. fields be gradually introducing with
Development, a-IGZO film have good transmitance as a kind of novel transparent oxide semiconductor material, in visible light wave range,
And it and flexible base board have good compatible result, also have uniformity and stable chemical characteristic, thus have been more suitable for
Active layer material has huge application prospect in display industry.With traditional thin film transistor active layer material (amorphous silicon hydride)
It compares, IGZO material has more advantages, image height carrier mobility, low temperature process and good optical transmission, Neng Gouman
The LCD technology demand of sufficient large area, so that potential replace traditional silica-base material.In addition a-IGZO is also considered to be
One of flexible display technologies and wider flexible wearable electronic technology development important materials.Therefore carry out to emerging
The preparation of a-IGZO semiconductor material and performance study are significant, semiconductor device amorphous indium gallium zinc oxide field-effect
The preparation of thin film transistor (TFT) (IGZO-TFT) and its performance study are as microelectronics subject instantly and other corresponding disciplinary studies
Hot spot.In the prior art, copper after the copper electrode of IGZO-TFT is easy to oxidize, copper electrode is deposited in active layer of metal oxide
Atom is spread to oxide.
Summary of the invention
Goal of the invention: it is directed to the above-mentioned prior art, proposes the source-drain electrode and transistor of a kind of InGaZnO thin film transistor (TFT)
Preparation method overcomes after copper electrode in the prior art is easy to oxidize, copper electrode is deposited in active layer of metal oxide
The defect that copper atom is spread to oxide.
Technical solution: a kind of source-drain electrode preparation method of InGaZnO thin film transistor (TFT) utilizes electron beam by mask plate
Evaporation first generate one layer of 15~25nm thickness titanium layer, then on the titanium layer re-evaporation generation one layer of 70~90nm thickness gold
Layer.
A kind of InGaZnO film crystal tube preparation method of bottom gate formula structure, includes the following steps:
Step 1: heavily doped P-type silicon substrate being cleaned and dried, the dust, organic matter, gold of silicon chip surface are removed
Belong to ion；
Step 2: by thermal oxidation technology, silicon substrate being put into oxidized diffusion furnace, in 900 DEG C of high temperature and high purity oxygen gas
Under atmosphere, one layer of SiO is grown on silicon substrate surface2Film；
Step 3: using reactive magnetron sputtering system in SiO2Film surface generates one layer of InGaZnO film；
Step 4: by mask plate using electron beam evaporation in SiO2Film surface, and it is located at the InGaZnO film
Opposite sides first generates titanium layer respectively, and then evaporation generates layer gold on the titanium layer.
The utility model has the advantages that source electrode and drain electrode of the invention, which is successively evaporated by mask plate using electron beam, generates titanium and layer gold system
Standby to obtain, fitting has good chemical inertness, so that it is not easy corrosion oxidation in source electrode and drain electrode and outside air long contact, and
Titanium specific strength is high, is not susceptible to deformation, the method overcome copper electrodes in the prior art, and easy to oxidize, copper electrode is deposited on gold
The defect that copper atom is spread to oxide after belonging in oxide active layer, in addition, titanium/gold metal work function is smaller, institute
There is higher conductivity with it.Preparation is completed using probe station and 4200 Semiconductor Parameter Analyzer of Keithley
It is found after IGZO-TFT test, the threshold voltage of the device is 4.5V, and subthreshold swing is smaller, grid bias VgsLeakage to device
Electric current IdsThere is good regulating and controlling effect, and device has good pinch-off behavior, which has good electrology characteristic.
Detailed description of the invention
Fig. 1 is the InGaZnO thin-film transistor structure schematic diagram of bottom gate formula structure；
Fig. 2 is magnetron sputtering method schematic diagram；
Fig. 3 is the transfer characteristic curve of the IGZO-TFT of preparation；
Fig. 4 is transmission characteristic of the IGZO-TFT of preparation under different grid voltages.
Specific embodiment
Further explanation is done to the present invention with reference to the accompanying drawing.
As voltage-controlled device, a-IGZO transistor is as common field-effect tube, and all there are three outer contacting poles:
Grid G, source S and drain D.
In structure, a-IGZO transistor has bottom gate, top-gated and three kinds of double-gate structure.Compared with latter two structure, bottom gate
Formula structure has effective mobility height, source-drain terminal electric current IsdGreatly, the good feature of threshold voltage stability.Meanwhile it being controlled as display
Device processed is in use, bottom gate formula structure can also better ensure that IGZO film is not influenced by foundation light photograph, in display application side
Face has better stability.
As shown in Figure 1, a kind of InGaZnO thin film transistor (TFT) of bottom gate formula structure includes substrate 1, and gate oxide 2, source electrode 3,
Drain 4, InGaZnO semiconductor layer 5.Wherein, substrate 1 is flexible insulating substrate or rigid insulation substrate, can be glass, insulation
Polymer or the silicon wafer for being covered with insulating layer.Gate oxide 2 is arranged on substrate 1, is the upper of P-type semiconductor silicon wafer after cleaning
Silicon dioxide insulating layer is produced by oxidation.Source electrode 3, drain electrode 4 are arranged on gate oxide 3, and phase is arranged on gate oxide 2
To two sides.InGaZnO semiconductor layer 5 is arranged on gate oxide 2, while connecting source electrode 3 and drain electrode 4.
The preparation method of the InGaZnO thin film transistor (TFT) of bottom gate formula structure includes the following steps:
Step 1: to the P type substrate Wafer Cleaning of heavy doping and drying, removing the dust, organic matter, metal of silicon chip surface
Ion.
Step 2: by thermal oxidation technology, silicon substrate being put into oxidized diffusion furnace, in 900 DEG C of high temperature and high purity oxygen gas
Under atmosphere, one layer of SiO is grown on silicon substrate surface2Film forms gate oxide 2.
Step 3: using reactive magnetron sputtering system in SiO2Film surface generates one layer of InGaZnO film, i.e. InGaZnO
Semiconductor layer 5.
Step 4: by mask plate using electron beam evaporation in SiO2Film surface, and it is located at the opposite of InGaZnO film
The titanium layer that two sides are first generated respectively with a thickness of 15~25nm, the layer gold that then evaporation generates with a thickness of 70~90nm on titanium layer,
Source electrode 3 and drain electrode 4 as the device.Wherein, the preferred 20nm of titanium layer thickness, the preferred 80nm of layer gold thickness.
In this method, consider that the consistency of TFT charge storage layer is of less demanding, more easily trapped electron when existing defects,
It therefore as the IGZO film of charge storage layer is prepared using magnetron sputtering method.Magnetron sputtering method is as shown in Fig. 2, be with certain
The particle (ion or neutral atom, molecule) of energy bombards target material surface, obtains the atom of target material surface or molecule sufficiently large
Energy and finally escape the technique of target material surface, can be used to deposit film.
Using the Vacuum Discovery Deposition System of Denton company manufacture in the present embodiment
(DVDDS) reactive magnetron sputtering system.Substrate material is put into sputtering chamber first, is then extracted using mechanical pump and molecular pump
Vacuum environment makes intracavitary vacuum degree reach 1.3 × 10-3Pa sets radio-frequency power as 100W, is filled with the Ar and 5scem of 45scem
Oxygen gas mixture, then by setting technological parameter complete sputtering process, in SiO2It is one layer of Surface Creation long to be with width
The IGZO film of 50um.The titanium layer of 20nm and the layer gold of 80nm are successively evaporated using electron beam by mask plate, in IGZO film
Upper formation source S and drain terminal D, is finally completed the preparation of IGZO-TFT.
Performance is carried out to the IGZO-TFT of preparation by probe station and 4200 Semiconductor Parameter Analyzer of Keithley to grind
Study carefully.For the ease of test, the IGZO-TFT that preparation is completed is adhered on stainless steel blade with conductive silver paste, and utilizes drying glue platform
Drying, to draw grid, when test, can directly be pricked probe on stainless steel.
The transfer characteristic curve of the IGZO-TFT of preparation is as shown in figure 3, work as grid voltage VgsWhen less than 4.5V, leakage current
IdsNumerical value very little illustrates that device is in close state；Work as VgsAfter 4.5V, IdsIt increased dramatically, it follows that the device
Threshold voltage VthFor 4.5V.On the other hand, with VgsIncrease, IdsExponentially rise, illustrates that subthreshold swing is smaller, device
Better performances.
Source S is grounded, grid voltage VgsBe set to 3V, 4V, 5V, 6V, or else with grid voltage under drain terminal voltage from 0V
It is gradually increased to 6V, detects the transmission characteristic of the device under different grid voltages, as a result as shown in Figure 4.Lower than 4.5V's
Under grid voltage control, IdsAlmost 0；Work as VgsHigher than VthWhen, device channel conducting, IdsIt is no longer 0, and with VgsIncrease, leakage
Electric current IdsIt significantly increases；Work as Vgs>VthWhen, under different grid voltages, IdsIt all shows as with VdsIncrease first significantly increase, with
After tend to be saturated it is constant.This shows for IGZO-TFT device, grid bias VgsTo the leakage current I of devicedsThere is good tune
Control effect, and device has good pinch-off behavior, and in saturation region, for leakage current without apparent lifting, this shows that TFT has
Good electrology characteristic.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (2)
1. a kind of source-drain electrode preparation method of InGaZnO thin film transistor (TFT), it is characterised in that: utilize electron beam by mask plate
Evaporation first generate one layer of 15~25nm thickness titanium layer, then on the titanium layer re-evaporation generation one layer of 70~90nm thickness gold
Layer.
2. a kind of InGaZnO film crystal tube preparation method of bottom gate formula structure, which comprises the steps of:
Step 1: heavily doped P-type silicon substrate is cleaned and is dried, remove the dust, organic matter, metal of silicon chip surface from
Son；
Step 2: by thermal oxidation technology, silicon substrate being put into oxidized diffusion furnace, in 900 DEG C of high temperature and high purity oxygen gas atmosphere
Under, one layer of SiO is grown on silicon substrate surface2Film；
Step 3: using reactive magnetron sputtering system in SiO2Film surface generates one layer of InGaZnO film；
Step 4: by mask plate using electron beam evaporation in SiO2Film surface, and it is located at opposite the two of the InGaZnO film
Side first generates titanium layer respectively, and then evaporation generates layer gold on the titanium layer.
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| CN201910402464.8A CN110120349A (en) | 2019-05-15 | 2019-05-15 | The source-drain electrode and crystal tube preparation method of InGaZnO thin film transistor (TFT) |
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| CN201910402464.8A CN110120349A (en) | 2019-05-15 | 2019-05-15 | The source-drain electrode and crystal tube preparation method of InGaZnO thin film transistor (TFT) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112164723A (en) * | 2020-09-24 | 2021-01-01 | 山东华芯半导体有限公司 | Bottom gate thin film transistor of random access memory and manufacturing method thereof |
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| CN102403363A (en) * | 2011-10-27 | 2012-04-04 | 华南理工大学 | Double-layered oxide thin film transistor and preparation method thereof |
| CN103606564A (en) * | 2013-07-24 | 2014-02-26 | 复旦大学 | Electrical programming-ultraviolet light erasing memory device structure and preparation method thereof |
| CN104992981A (en) * | 2015-05-26 | 2015-10-21 | 中国科学院宁波材料技术与工程研究所 | Oxide thin film transistor, preparation method thereof, phase inverter and preparation method thereof |
| CN106876515A (en) * | 2017-03-06 | 2017-06-20 | 中国科学院宁波材料技术与工程研究所 | Visible blind photodetector of thin-film transistor structure and preparation method thereof |
-
2019
- 2019-05-15 CN CN201910402464.8A patent/CN110120349A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070145460A1 (en) * | 2005-12-27 | 2007-06-28 | Dongbu Electronics Co., Ltd. | Flash memory device and method of manufacturing the same |
| CN102403363A (en) * | 2011-10-27 | 2012-04-04 | 华南理工大学 | Double-layered oxide thin film transistor and preparation method thereof |
| CN103606564A (en) * | 2013-07-24 | 2014-02-26 | 复旦大学 | Electrical programming-ultraviolet light erasing memory device structure and preparation method thereof |
| CN104992981A (en) * | 2015-05-26 | 2015-10-21 | 中国科学院宁波材料技术与工程研究所 | Oxide thin film transistor, preparation method thereof, phase inverter and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112164723A (en) * | 2020-09-24 | 2021-01-01 | 山东华芯半导体有限公司 | Bottom gate thin film transistor of random access memory and manufacturing method thereof |
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Application publication date: 20190813 |
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