經濟部中央標準局員工消費合作社印製 538474 Λ7 ___—_ 五、發明説明（1 ) 本發明係有關於一種半導體製程，且特別是一種半導體 積體電路製造方法的改良，可配合淺溝槽隔離區（sti)之製程， 而在化式機械研磨程序（CMP)後重現基底上的對準標記 (alignment marks)，以利於後續微影程序的施行。Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 538474 Λ7 ___ —_ 5. Description of the invention (1) The present invention relates to a semiconductor process, and in particular to an improvement of a semiconductor integrated circuit manufacturing method, which can be used with shallow trench isolation Sti, and the alignment marks on the substrate are reproduced after the chemical mechanical polishing process (CMP) to facilitate the subsequent lithography process.
Be著半導體製程尺寸曰趨縮小，製程中光學微影 (lithography)的解析度要求更趨嚴格。要達到更高的光學解析 度’不僅需要提南製程設備的性能，同時對於製程中可能造 成干擾的因素亦必須排除。材料表面不平坦所引發之對準誤 差即為其中之一。因此，在次微米或更細微尺寸的製程中， 將材料的微觀表面變得更平坦，即成為不可或缺的步驟。在 各種平坦化方法中，化學性機械研磨（Chemical_Mechankal Polishing，CMP)技術挾其全面平坦化的優勢，已成為目前生產 線上重要的製程技術，而廣泛應用於淺溝槽隔離製程（STI)、 金屬内連導線製程（metal interconnection)等方面。 然而，化學性機械研磨在應用上具有一嚴重缺點，即磨 平材料表面的同時，亦會將基底上的對準標記(Alignmem Mark) 一併磨平，而影響後續微影製程的施行。對準標記是提供如 ASM步進機之光罩製程設備進行光罩對準之用，通常為複數 個溝槽構成之幾何圖案，每個溝槽的寬度一般為8μιη。於光 罩製程時，將光罩中的標記和晶圓表面的對準標記相匹配， 即可大致決定光罩的方向及位置，減少對準所需的時間。因 此，晶圓表面的對準標記溝槽須具有傳遞性，亦即每覆蓋一 材料層，對準標記會傳遞至新材料層的表面；但如上所述， 以化學性機械研磨此材料層時，對準標記卻會因此而消失。 上述的問題會發生在淺溝槽隔離製程中，亦即當施行化 (210X 297公麓） (請先閲讀背面之注意事項再填寫本頁)The size of the semiconductor process is shrinking, and the resolution requirements of optical lithography in the process are becoming stricter. Achieving higher optical resolutions' requires not only the performance of the southern process equipment, but also the factors that may cause interference in the process must also be eliminated. One of them is misalignment caused by uneven material surfaces. Therefore, in the process of sub-micron or finer size, it becomes an indispensable step to make the microscopic surface of the material flatter. Among various planarization methods, Chemical Mechanical Polishing (CMP) technology, with its comprehensive planarization advantages, has become an important process technology on the current production line, and is widely used in shallow trench isolation (STI), metal In aspects such as metal interconnection process. However, chemical mechanical polishing has a serious disadvantage in application. That is, while aligning the surface of the material, it will also flatten the alignment marks on the substrate, which affects the subsequent lithography process. Alignment marks are used to provide mask alignment equipment, such as ASM stepper, for mask alignment. It is usually a geometric pattern composed of a plurality of grooves, and the width of each groove is generally 8 μm. During the mask manufacturing process, matching the marks in the mask with the alignment marks on the wafer surface can roughly determine the direction and position of the mask, reducing the time required for alignment. Therefore, the alignment mark grooves on the wafer surface must be transmissive, that is, each time a material layer is covered, the alignment mark is transmitted to the surface of the new material layer; as described above, when this material layer is chemically and mechanically ground , The alignment mark will disappear. The above problems will occur in the shallow trench isolation process, that is, when implemented (210X 297 feet) (Please read the precautions on the back before filling this page)
經濟部中央標準局員工消費合作社印裝 538474 A7 ' —---—______ B7 五、發明説明（2 ) ~ 一 — 學性機械研磨之後，原本轉移到氧化層的對準標記也一併被 磨^ 了，使得後續的光軍製程沒有對準的依據。為了更清楚 了解問、所在’以下請參照第iA圖至第⑴圖，說明一習知 淺溝槽隔離區的製造流程，其中圖示左側的區域工爲對準標記 區，圖示右侧的區域Π為同一步驟之元件區。首先，如第1A 圖所示者，提供一半導體基底10,例如是-石夕晶圓，其包括 對準標記區I和元件區虹。以微影成像和姓刻程序，在半導體 基底10的對準檩記區I上，製作出複數個間隔配置的溝槽12， 用以當作對準標號，其寬度大約在8μη1左右。 其-人’ 4參見第1Β圖，在半導體基底的元件區I上 覆蓋一遮蔽層，並定義出一遮蔽層圖案，露出半導體基底10 奴形成淺溝槽的區域。例如，先以熱氧化方法形成一墊氧化 層13 ,再以化學氣相沈積程序形成一氮化石夕層μ，共同構成 遮蔽層。然後，以微影成像程序定義出如圖所示的遮蔽層圖 案15。接著，利用遮蔽層圖案15當作罩幕，施行一蝕刻程序 而在半導體基底10的元件區][上形成淺溝槽16。 接下來’如第1C圖所示者，形成一氧化層18，例如是以 低壓化學氣相沈積程序（LPCVD)所形成之四乙氧基矽甲烷 (TEOS)氧化物層，或是一臭氧一四乙氧基矽甲烷（〇3_TE〇s)氧 化物層，用以填滿對準標記區I的溝槽12和元件區ϋ的淺溝 槽16,並延伸覆蓋在整個半導體基底1〇的表面上。應注意者， 在圖示左侧的對準標記區I上，對準標記的溝槽12圖案已轉 移到氧化層18上，而形成新的對準標記19。 之後，如第1C圖所示者，對氧化層is施行一化學性機 械研磨程序，以使基底表面全面平坦化，直至氧化層18的表 ___ -4- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） ~ ^ —€-------衣— (請先閱讀背面之注意事項再填寫本頁) 訏 538474 Λ7 五、發明説明（3 ) 面與遮蔽層圖案15的表面等高為止，而留下在元件區I的隔 離區18a，以及在對準標記區I的平坦氧化層18b。很明顯地， 轉移到氧化層18的對準標記溝槽19，在此一化學性機械研磨 程序後也一併被磨平，使得基底表面再無可供光罩對準之標 號圖案。當後續覆蓋的不透光材料層，例如是一金屬層，且 欲藉微影成像和蝕刻程序定義其圖案時，已沒有對準標記可 供光罩對準之用，此即所所謂的遮蔽(blind)現象。 欲消除化學性機械研磨後造成之遮蔽現象，必須設法使 對準標號重現(regeneration)。在習知的改良方法中，大多藉由 額外的微影成像和触刻步驟，而於平坦的氧化層表面上形成 相同或不同的對準標號溝槽，供後續光罩對準之用，然而其 製程步驟通常過於複雜，並不適用於實際的生產線上。此外， 由於習知之製程大多係將對準標記製作在元件區以外的空白 區域中，基於化學性機械研磨程序對線路密集的元件區和空 白區域的研磨特性差異，將導致與對準標記鄰近之晶方（die)的 不當磨損，造成產品良率的降低。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 有鑑於此，本發明之主要目的，在提供一種化學性機械 研磨後重現對準標記之製造方法，以利於後續微影程序的施 行。此製造方法無需增加額外之製程光罩，並且可避免一般 於基底空白區域形成對準標記之製程所造成其鄰近晶方（die)不 當磨損的問題。 為達成上述目的，本發明提出一種半導體積體電路製造 方法的改良，可配合淺溝槽隔離區（ST1)之製程，而在化式機 械研磨程序（CMP)後重現基底上的對準標記（alignment 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公漦） 538474 經 濟 部 t 標 工 消 費 合 作 社 印 製 Λ7 B7 五、發明説明（4 ) ' marks)。洋研之’此一種化學性機械研磨後重現對準標記之製 1^方法’包括下列步驟：形成一遮蔽層覆於一半導體基底上， 並疋義出一遮蔽層圖案，露出半導體基底欲形成對準標記的 邵分；利用上述遮蔽層圖案當作罩幕，蝕刻半導體基底以形 成複數個間隔配置的溝槽當作對準標記；形成一氧化層以填 滿上述溝槽，並延伸覆蓋在遮蔽層圖案的表面上；蝕刻去除 上述氧化層位於遮蔽層圖案上方的部分；施行一化學性機械 研磨程序’將溝槽中之氧化層研磨至與遮蔽層表面等高的位 置’得到一平坦的表面構造；以及去除上述遮蔽層圖案，使 得溝槽中之氧化層突出於半導體基底表面之上，重現一反相 的對準標記，以供後續微影程序對準之用。 根據本發明的較佳實施例，上述遮蔽層係包括一墊氧化 層和一氮化石夕層所構成的疊層，其中遮蔽層的厚度約為u〇人， 氮化矽層的厚度為介於1600A和1700A之間。上述溝槽的深 度約爲3500A，而其寬度須小於上述氧化層厚度的兩倍，以利 於氧化層填滿上述溝槽。至於氧化層的材質，可以是一低壓 化學氣相沈積程序（LPC VD)所形成之四乙氧基矽甲烷（TE〇s) 氧化物層，或是一臭氧一四乙氧基矽甲烷（〇3_TE〇S)氧化物 層，其厚度約為6000人。此外，化學性機械研磨程序係選用對 氧化層/氮化發層為高選擇比之研漿（slurry)來進行的，而去除 上述遮蔽層圖案之後，溝槽中之氧化層突出於半導體基底表 面之上的高度係約為1200A。 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下： 6 - (請先閱讀背面之注意事項再填寫本頁) 訂 本纸張尺度適用中國國家標举 (CNS ) A4規格（210X 297公f 538474 Λ7 B7 五、發明説明（5 ) 圖式之簡簞說明 第1A圖至第1D圖係顯示一習知形成淺溝槽隔離區的製 造流程，其中區域I爲對準標記區，區域為同一步驟之元件 區；以及 第2A圖至第2E圖爲一系列剖面圖，顯示本發明一較佳 實施例的製造流程，其於化學性機械研磨後，重現元件區内 的對準標記。 實施例 依據本發明所提出重現對準標號的方法，可配合一般的 淺溝槽隔離製程，將對準標記製作在元件區中，在化學性機 械研磨程序後，可藉由去除遮蔽層圖案而重現元件區的對準 標記，可供後續光罩對準之用。以下，即請參照第2A圖至第 2E圖，說明本發明製造方法之一較佳實施例。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事^再填寫本頁) 首先，如第2A圖所示者，提供一半導體基底2〇，例如是 一具有平整表面的矽晶圓，其並未形成有任何對準標記。在 半導體基底20上覆蓋一遮蔽層，並定義出一遮蔽層圖案23， 露出半導體基底20之元件區欲形成對準標記溝槽的部分。例 如’先以熱氧化方法形成一墊氧化層21，其厚度約爲n〇A， 再以化學氣相沈積程序形成一氮化矽層22,其厚度介於1600A 和1700A之間，共同構成上述遮蔽層。然後，施行一微影成 像程序，定義出如圖所示的遮蔽層圖案23。 利用上述遮蔽層圖案23當作罩幕，蝕刻半導體基底2〇 以形成複數個間隔配置的溝槽24，用來當作對準標記。其中， 溝槽24的深度約為35〇〇A，而其寬度須較一般對準標記溝槽 本紙張尺度適用中國國家標準（CNS ) Λ4規格 (210X297公漦） 經濟部中夬標準局員工消費合作衽印製 538474 Λ7 -----____ B7 五、發明説明（6 ) — ' 者為小，以使後續形成的氧化層易於填滿溝槽24。接著，如 第2B圖所示者，形成一氧化層μ填滿溝槽24，並延伸覆蓋 在遮蔽層圖案23的表面上。此一氧化層25的厚度约為6〇〇〇A， 而其材質可以是一低壓化學氣相沈積程序（LPCVD)所形成之四 乙氧基矽甲烷（TEOS)氧化物層，或是一臭氧一四乙氧基矽甲 烷（〇3-TEOS)氧化物層。 备月參見苐2C圖，施行一回触刻（etchjng back)程序，去除 氧化層25位於遮蔽層圖案23上方的部分，而留下在溝槽24 中的部分25a。之後，施行一化學性機械研磨程序，將溝槽24 中之氧化層25a表面研磨至與遮蔽層23表面等高的位置，形 成如第2D圖所示平坦的表面構造。此一化學性機械研磨程序， 例如是選用對氧化層：氮化矽層高研磨選擇比之研漿（slurry) 來進行的，且由於對準標記係形成在雞的空曠區域上，因此 遮蔽層圖案23受研磨的速率較低，其厚度損失並不會太多。 接下來，請參見第2E圖，依序去除遮蔽層圖案之氮化矽 層22a和塾氧化層21，露出半導體基底2〇的表面，使得溝槽 24中原本平整的氧化層25b，變成突出於半導體基底2〇表面 之上，例如是約為1200A的高度。如此，可在元件區中重製 一反相的對準標記，供作後續微影程序光罩對準之用。 與習知技術相比較，本發明所提出於化學性機械研磨後 重現對準標記之製造方法，具有下列優點： 1 ·無需增加額外的光罩，即可達成重現對準標記之目的。 由於光罩的製作佔一般製程成本中相當的比例，因此本發明 改良製程可降低生產成本。 本紙張尺度適用中國國家標準（CNS ) A4規格（2IOX 297公釐） 1 -1 ,t I n m· m ml mi ϋϋ n —K^i ϋϋ - -1— I - - 1 4 ml - J I nn - Hi ml -- (請先閲讀背面之注意事項再填寫本頁) 538474 Λ7 Β7 五、發明説明（7 ) 2.由於本發明的對準標記可形成於元件區的切割線（scribe line)上，因此可避免一般於基底空白區域形成對準標記之製程 所造成其鄰近晶方（die)不當磨損的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此項技藝者，在不脫離本發明之精神和 範圍内，當可作些許之更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐)Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 538474 A7' —---—______ B7 V. Description of the Invention (2) ~ 1 — After the mechanical grinding, the alignment marks originally transferred to the oxide layer were also ground. ^, So that the subsequent Guangjun process has no basis for alignment. For a clearer understanding of where and where you are, please refer to Figures iA to ⑴ below to explain the manufacturing process of a conventional shallow trench isolation area. The area on the left side of the figure is an alignment mark area, and the area on the right side of the figure is The area Π is a component area of the same step. First, as shown in FIG. 1A, a semiconductor substrate 10, such as a Shi Xi wafer, is provided, which includes an alignment mark region I and a device region rainbow. Using the lithography imaging and engraving procedures, a plurality of grooves 12 arranged at intervals on the semiconductor substrate 10 in the alignment mark area I are used as alignment marks, and the width is about 8 μη1. Its-person '4 is shown in FIG. 1B, and a masking layer is covered on the element region I of the semiconductor substrate, and a masking layer pattern is defined to expose a region where the semiconductor substrate 10 forms a shallow trench. For example, a pad oxidation layer 13 is first formed by a thermal oxidation method, and then a nitride layer μ is formed by a chemical vapor deposition process to form a shielding layer together. Then, the lithography imaging program is used to define the masking layer pattern 15 as shown in the figure. Next, using the mask layer pattern 15 as a mask, an etching process is performed to form a shallow trench 16 on the element region of the semiconductor substrate 10] [. Next, as shown in FIG. 1C, an oxide layer 18 is formed, such as a tetraethoxysilylmethane (TEOS) oxide layer formed by a low pressure chemical vapor deposition process (LPCVD), or an ozone- Tetraethoxysilylmethane (〇3_TE〇s) oxide layer, which is used to fill the trench 12 aligned with the mark region I and the shallow trench 16 in the device region ,, and extends to cover the entire surface of the semiconductor substrate 10. on. It should be noted that, on the alignment mark area I on the left side of the figure, the pattern of the trench 12 of the alignment mark has been transferred to the oxide layer 18 to form a new alignment mark 19. After that, as shown in FIG. 1C, a chemical mechanical polishing process is performed on the oxide layer is to flatten the surface of the substrate comprehensively until the table of the oxide layer 18 ___ -4- This paper size applies the Chinese National Standard (CNS ) Α4 size (210X 297mm) ~ ^ — € ------- Cloth— (Please read the precautions on the back before filling in this page) 訏 538474 Λ7 V. Description of the invention (3) Surface and masking layer pattern The surface of 15 is so high that the isolation region 18a in the element region I and the flat oxide layer 18b in the alignment mark region I remain. Obviously, the alignment mark grooves 19 transferred to the oxide layer 18 are also flattened after this chemical mechanical polishing process, so that there is no more mark pattern on the substrate surface for the alignment of the photomask. When the layer of opaque material covered later, for example, is a metal layer, and its pattern is to be defined by lithography imaging and etching procedures, there is no alignment mark available for the alignment of the photomask, which is the so-called masking (blind) phenomenon. To eliminate the shadowing caused by chemical mechanical polishing, it is necessary to try to regenerate the alignment marks. In the conventional improved methods, the same or different alignment mark grooves are formed on the surface of the flat oxide layer by additional lithography imaging and touch-engraving steps, which are used for subsequent photomask alignment. However, The process steps are usually too complicated and are not suitable for actual production lines. In addition, since the conventional manufacturing processes mostly produce alignment marks in the blank area outside the component area, the difference in the grinding characteristics of the circuit-intensive component area and the blank area based on the chemical mechanical polishing process will lead to the proximity of the alignment marks. Improper wear of the die results in a reduction in product yield. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). In view of this, the main purpose of the present invention is to provide a manufacturing method for reproducing alignment marks after chemical mechanical polishing. To facilitate the implementation of subsequent lithography procedures. This manufacturing method does not need to add an additional process mask, and can avoid the problem of improper wear of the adjacent die caused by the process of forming an alignment mark generally in the blank area of the substrate. In order to achieve the above object, the present invention proposes an improvement of a semiconductor integrated circuit manufacturing method, which can cooperate with the process of a shallow trench isolation region (ST1) and reproduce an alignment mark on a substrate after a chemical mechanical polishing process (CMP). (Alignment This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 gong)) 538474 Printed by t Standard Industrial Consumer Cooperatives of the Ministry of Economic Affairs Λ7 B7 V. Description of the invention (4) 'marks). Yang Yanzhi's "Method for Reproducing Alignment Marks After Chemical Mechanical Grinding 1 ^ Method" includes the following steps: forming a masking layer on a semiconductor substrate, and defining a masking layer pattern to expose the semiconductor substrate. Shao points forming alignment marks; using the above masking layer pattern as a mask, etching the semiconductor substrate to form a plurality of spaced-apart trenches as alignment marks; forming an oxide layer to fill the trenches, and extending to cover On the surface of the masking layer pattern; etching to remove the part of the oxide layer above the masking layer pattern; performing a chemical mechanical polishing procedure 'grind the oxide layer in the trench to a position equal to the surface of the masking layer' to obtain a flat surface Surface structure; and removing the above masking layer pattern, so that the oxide layer in the trench protrudes above the surface of the semiconductor substrate, and reproduces an inverted alignment mark for subsequent lithography process alignment. According to a preferred embodiment of the present invention, the above-mentioned shielding layer includes a stacked layer composed of a pad oxide layer and a nitride nitride layer, wherein the thickness of the shielding layer is about u0, and the thickness of the silicon nitride layer is between Between 1600A and 1700A. The depth of the trench is about 3500A, and its width must be less than twice the thickness of the oxide layer to help the oxide layer fill the trench. As for the material of the oxide layer, it can be a TEOS oxide layer formed by a low-pressure chemical vapor deposition (LPC VD) process, or an ozone-tetraethoxysilane (0) 3_TE0S) oxide layer, its thickness is about 6000 people. In addition, the chemical mechanical polishing process is performed by using a slurry having a high selectivity ratio to the oxide layer / nitridation layer. After removing the masking layer pattern, the oxide layer in the trench protrudes from the surface of the semiconductor substrate. The height above is about 1200A. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: 6-(Please read the precautions on the back before (Fill in this page) The size of the paper is applicable to China National Standards (CNS) A4 specifications (210X 297 male f 538474 Λ7 B7 V. Description of the invention (5) Brief description of the drawings Figures 1A to 1D are shown in Figure 1 A conventional manufacturing process for forming a shallow trench isolation region, where region I is an alignment mark region, and the region is an element region at the same step; and FIGS. 2A to 2E are a series of cross-sectional views showing a preferred implementation of the present invention. The manufacturing process of the example is to reproduce the alignment marks in the element area after chemical mechanical polishing. According to the method of the present invention to reproduce the alignment marks, the embodiment can be used in conjunction with a general shallow trench isolation process to Quasi marks are made in the element area. After the chemical mechanical polishing process, the alignment marks of the element area can be reproduced by removing the masking layer pattern, which can be used for subsequent photomask alignment. Below, please refer to Section 2A Figure to Figure 2E, say Describes a preferred embodiment of the manufacturing method of the present invention. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back ^ before filling this page). First, as shown in Figure 2A, provide a semiconductor substrate 20, for example, is a silicon wafer with a flat surface, which is not formed with any alignment marks. A masking layer is covered on the semiconductor substrate 20, and a masking layer pattern 23 is defined to expose the device region of the semiconductor substrate 20. The portion where the alignment mark groove is to be formed. For example, 'a pad oxide layer 21 is formed by a thermal oxidation method with a thickness of about 0A, and then a silicon nitride layer 22 is formed by a chemical vapor deposition process, and the thickness is Between 1600A and 1700A, the above-mentioned masking layer is formed together. Then, a lithography imaging process is performed to define a masking layer pattern 23 as shown in the figure. Using the masking layer pattern 23 as a mask, the semiconductor substrate 2 is etched. A plurality of grooves 24 arranged at intervals are used as alignment marks. Among them, the depth of the grooves 24 is about 350,000 A, and the width of the grooves 24 must be larger than that of general alignment marks. Home Standards (CNS) Λ4 specifications (210X297) 漦 Printed by the Consumer Standards Cooperative Bureau of the Ministry of Economic Affairs of the People's Republic of China 538474 Λ7 -----____ B7 V. Description of the invention (6) — 'The one that is small, so that subsequent The oxide layer is easy to fill the trench 24. Then, as shown in FIG. 2B, an oxide layer μ is formed to fill the trench 24, and extends to cover the surface of the masking layer pattern 23. The thickness of this oxide layer 25 It is about 600A, and the material can be a tetraethoxysilylmethane (TEOS) oxide layer formed by a low pressure chemical vapor deposition process (LPCVD), or an ozone-tetraethoxysilylmethane (〇3-TEOS) oxide layer. Refer to Figure 2C for the next month, and perform an etchjng back procedure to remove the portion of the oxide layer 25 above the masking layer pattern 23 while leaving the remaining portion in the trench 24. Section 25a. Thereafter, a chemical mechanical polishing process is performed to grind the surface of the oxide layer 25a in the trench 24 to a position equal to the surface of the shielding layer 23 to form a flat surface structure as shown in FIG. 2D. This chemical mechanical polishing process is performed, for example, by using a slurry with a high polishing selection ratio for the oxide layer: silicon nitride layer, and since the alignment mark is formed on the open area of the chicken, the shielding layer The rate at which the pattern 23 is subjected to grinding is relatively low, and the thickness loss is not so great. Next, referring to FIG. 2E, the silicon nitride layer 22a and the hafnium oxide layer 21 of the masking layer pattern are sequentially removed to expose the surface of the semiconductor substrate 20, so that the originally flat oxide layer 25b in the trench 24 becomes protruding from Above the surface of the semiconductor substrate 20 is, for example, a height of about 1200A. In this way, an inverted alignment mark can be reproduced in the element area for subsequent photolithography process mask alignment. Compared with the conventional technology, the manufacturing method for reproducing the alignment mark after chemical mechanical polishing provided by the present invention has the following advantages: 1. The purpose of reproducing the alignment mark can be achieved without adding an additional photomask. Since the production of the photomask accounts for a considerable proportion of the general process cost, the improved process of the present invention can reduce the production cost. The paper size is in accordance with Chinese National Standard (CNS) A4 (2IOX 297 mm) 1 -1, t I nm · m ml mi ϋϋ n —K ^ i ϋϋ--1— I--1 4 ml-JI nn- Hi ml-(Please read the notes on the back before filling this page) 538474 Λ7 Β7 V. Description of the invention (7) 2. Since the alignment mark of the present invention can be formed on the scribe line of the component area, Therefore, the problem of improper wear of the adjacent die caused by the process of forming the alignment mark in the blank area of the substrate can be avoided. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm)