A7 B7 ^ 3〇C)twf . doc/008 1、發明説明（I ) 本發明是有關於一種曝光製程，且特別是有關於一 種晶圓外緣曝光用光罩。 化學機械硏磨法（Chemical-Mechanical Polishing)，簡 稱爲CMP，是能提供積體電路製程全面性平坦化（Global Planarization)的一種常用技術。這項技術係利用類似”拋 光”這種機械式硏磨的原理，配合適當的化學助劑 (Reagent)，來把晶圓表面高低起伏不一的輪廓，一倂加 以磨平的平坦化技術。 第1圖繪示一種積體電路的晶圓俯視示意圖，而第2 圖繪示根據第1圖之Π-ΙΙ剖面，一種晶圓的部份剖面示意 圖。在第2圖中，虛線的左側係表示晶圓1〇〇的內圍102， 而虛線的右側則表示此晶圓100的外緣104。所謂的內圍 1〇2係指晶圓100中，具有有效晶粒（effective die)的區域。 至於外緣104，則係指其晶粒並不完整，而爲無效晶粒的 區域。 請參照第2圖與第1圖，在^圓內圍102中，有數個 經定義的導線206a形成在基上，如第2圖所示。 至於晶圓外緣104的金屬層-般而言會被保留下 來。這將造成晶圓內圍102的金¥圖_密度小於晶圓外緣 104的金屬圖案密度，使得後續形&在&底200上的介電 層208在實施CMP製程之後，會在晶圓內圍102靠近外 緣104的邊緣區域102a發生突起。這種突起現象將使後 續在介電層上進行的光阻曝光製程發生圖形離焦 (Defocus)，也就是圖中邊緣區域108上的光阻層（未繪示) 3 (請先閱讀背面之注意事項再填寫本頁) -5 經濟部智慧財產局®工消費合作社印製 本紙張尺度適用中國國家標隼（CNS ) A4規格（2丨〇X297公釐> 經濟部智慧財產局員工消費合作社印製 Q〇 A7 4 3 0 0 twi.doc ' ·Τ " ? B7 五、發明説明（i ) 無法落在聚焦深度（Depth of Focus ; DOF)有效範圍內，而 造成曝光失誤等情形。 這種因爲圖案密度的不同所引起的現象稱之爲圖案效 應（Pattern Effect)。它不僅常見於金屬內連線製程，還常 .發生於淺溝渠隔離平坦化製程。請參照第3圖，其所繪示 爲一種淺溝渠隔離平坦結構的剖面示意圖。其中，虛線的 左側係表示晶圓300的內圍302，而虛線的右側則表示此 晶圓的外緣304。當淺溝渠隔離的氧化層在基底上形成， 並進行化學機械硏磨製程之後，會在晶圓內圍靠近外緣的 邊緣區域發生突起，因其圖案密度比外緣的圖案密度來得 低。換句話說，部份位在氮化矽層上方的氧化層將無法去 除。這些無法去除的氧化層將連帶使得其下方的氮化矽層 無法移除，而在製作電晶體等元件時，發生元件間的連伸 失誤（Fail Continuity) ° 因此，本發明提供一種晶圓外緣曝光製程，以避免 淺溝渠隔離之CMP製程所導致的導致氮化矽殘留等問題。 本發明提供一種淺溝渠隔離製程，以避免介電層之 CMP製程所導致的曝光失誤等問題。 爲達成本發明之上述和其他目的，提供一種晶圓外緣 曝光製程，應用於一晶圓，此晶圓包括一基底，此製程係 先於基底上形成氮化砂層。接著，於氮化砂層上形成光阻 層。之後，提供一光罩，此光罩包括一方形中空圖案。然 後，利用此光罩進行光阻層的第一曝光步驟，以將晶圓外 緣之光阻層曝光。接著，利用另一光罩進行晶圓內圍之光 4 -ϋ ^^1 ^^1 «^n ------ I- - - - - 1 IT -------- ^^1 ^^1 UK - - *-fl (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS > A4規格（2 (0 X 297公釐） 經濟部智慧財產局D貝工消費合作社印製 A7 4300twf.Q〇c/G03 B7 五、發明説明（]) 阻層的第二曝光步驟。之後，進行光阻層的顯影製程，以 形成光阻圖案。然後，以光阻圖案爲蝕刻罩幕，鈾刻氮化 矽層，以形成圖案化之氮化矽層，並去除晶圓外緣之氮化 矽層。接著，以圖案化之氮化矽層爲罩幕，蝕刻基底，以 .於基底中形成溝渠，並去除部份晶圓外緣之基底。之後， 於基底上形成氧化層覆蓋圖案化之氮化矽層。然後，以圖 案化之氮化矽層爲終點，進行氧化層的化學機械硏磨製 程。 應用本發明提出之光罩，可使介電層之CMP製程所導 致的曝光失誤，以及淺溝渠隔離之CMP製程所導致的氮 化矽殘留等問題獲得解決。 本發明尙有其他目的或優點，在此並未詳述*可於實 施本發明的過程中顯示出來，將於實施例中加以描述。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖繪示一種積體電路的晶圓俯視示意圖； 第2圖繪示根據第1圖之II-II剖面，一種晶圓的部份 剖面示意圖； 第3圖繪示一種淺溝渠隔離平坦結構的剖面示意圖； 第4A圖至第4G圖繪示根攄本發明實施例，一種晶圓 外緣曝光製程的流程剖面示意圖；以及 第5圖繪示根據第4A圖，一種晶圓俯視結構示意圖。 5 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐） ： ~ I 裝 訂 β (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^1.500 A7 4 3 Ο 0 t w f . d 〇 二./ W. 37五、發明説明（4 )圖式之標記說明： 100、500 :晶圓 】02、3 02、402 :晶圓內圍 104、304 ' 404 :晶圓外緣 200、300、400 :基底 102a ' 302a ·邊緣區域 206a :導線 2〇6b :金屬層 208 :介電層 3 0 6 :氧化層 3 08、406 :氮化矽層 404a :傾斜表面 4 0 6 a :圖案化之氮化ϊ夕層 408 :光阻層 410、420 :光源 412、422 :光罩 424 :光阻圖案 426 :溝渠 4 2 8 :氧化層 428a:氧化插塞（元件隔離結構) 412 :光罩（虛擬光罩） 502 :中空方形圖案 504a、504b、504c :虛線框格實施例 (請先閱讀背面之注意事項再填寫本頁) Λ衣. 本紙浪尺度適用中國國家標準（CNS ) A4規格（2〗0X297公釐） ^1^530 A7 4 3 0 0 t w f . d c c / 〇 〇 8 B7 五、發明説明（t) 本發明的特色之一在於去除晶圓外緣的氮化砂層，藉 此使其後續形成於晶圓外緣的氧化層，能低於形成於晶圓 內圍的氧化層，或者使CMP後在晶圓外緣的氧化層不會 殘留。 請參照第4A圖，其中虛線的左側係表示晶圓內圍402， 而虛線的右側則表示此晶圓外緣404。首先，提供一基底 400,並於基底400上依序形成氮化矽層4〇6與光阻層408。 然後，利用一光源410與光罩412，進行晶圓外緣404光 阻層408的曝光步驟。這個曝光步驟，可以利用較爲廉價 的曝光機來進行，或者利用解析能力較低的曝光機。這些 比較係相對於晶圓內圍402的製程而言。 請參照第4B圖，利用另一光源420與光罩422，進行 晶圓內圍4〇2光阻層4〇8的曝光步驟，用以曝出所欲形成 的溝渠圖案。 請參照第4C圖，經顯影製程後，即完成所要的光阻 圖案424。 請參照第4D圖，以光阻圖案(第4C圖之424)爲蝕刻 罩幕’蝕刻氮化矽層（第4C圖之4〇6)，以形成圖案化之氮 化矽層4〇6a’並去除晶圓外緣4〇4之氮化矽層406。之後， 去除光阻圖案424。 請參照第4E圖，以圖案化的氮化矽層406a爲蝕刻罩 幕’非等向性蝕刻基底400,以於基底400中形成溝渠426， 並去除部份晶圓外緣404的基底400。 請參照第4F圖，於基底400上形成氧化層428覆蓋氮 7 (請先閱讀背面之注意事項再填寫本頁) 、-° 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標率（CNS ) A4現格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製A7 B7 ^ 3 ° C) twf.doc / 008 1. Description of the Invention (I) The present invention relates to an exposure process, and in particular to a photomask for exposing the outer edge of a wafer. Chemical-mechanical polishing (Chemical-Mechanical Polishing), abbreviated as CMP, is a commonly used technique that can provide integrated planarization of integrated circuit manufacturing processes. This technology uses the principle of mechanical honing similar to "polishing" and the appropriate chemical agent (Reagent) to flatten the surface of the wafer with uneven contours. Fig. 1 shows a schematic plan view of a wafer of an integrated circuit, and Fig. 2 shows a schematic sectional view of a part of a wafer according to the Π-II cross section of Fig. 1. In FIG. 2, the left side of the dotted line indicates the inner circumference 102 of the wafer 100, and the right side of the dotted line indicates the outer edge 104 of the wafer 100. The so-called inner circumference 102 refers to a region of the wafer 100 having an effective die. As for the outer edge 104, it refers to a region where the grains are not complete but are invalid grains. Referring to FIG. 2 and FIG. 1, in the inner circle 102, a plurality of defined wires 206a are formed on the base, as shown in FIG. As for the metal layer of the wafer outer edge 104, it is generally retained. This will cause the gold inner diameter of the wafer inner circumference 102 to be less than the metal pattern density of the wafer outer edge 104, so that the subsequent shape & dielectric layer 208 on the bottom 200 will be in the crystal after the CMP process is performed. The edge region 102 a of the round inner periphery 102 close to the outer edge 104 is raised. This protrusion phenomenon will cause the subsequent photoresist exposure process on the dielectric layer to defocus, that is, the photoresist layer (not shown) on the edge region 108 in the figure. 3 (Please read the back Note: Please fill in this page again) -5 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs® Industrial and Consumer Cooperatives. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 〇297mm > Employee Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Print Q〇A7 4 3 0 0 twi.doc '· T "? B7 V. Description of the Invention (i) Cannot fall within the effective range of Depth of Focus (DOF), resulting in exposure errors, etc. This This phenomenon caused by the difference in pattern density is called the Pattern Effect. It is not only common in the metal interconnection process, but also often occurs in the shallow trench isolation and planarization process. Please refer to Figure 3, where Shown is a schematic cross-sectional view of a shallow trench isolation flat structure. The left side of the dotted line represents the inner circumference 302 of the wafer 300, and the right side of the dotted line represents the outer edge 304 of the wafer. On the substrate After performing the chemical mechanical honing process, protrusions will occur in the edge region of the wafer inner periphery near the outer edge, because its pattern density is lower than the pattern density of the outer edge. In other words, some are located in silicon nitride The oxide layer above the layer will not be removed. These unremovable oxide layers will cause the silicon nitride layer below it to be removed, and in the production of components such as transistors, Fail Continuity will occur between the components ° Therefore, the present invention provides a wafer outer edge exposure process to avoid problems such as silicon nitride residue caused by a shallow trench isolation CMP process. The present invention provides a shallow trench isolation process to avoid a dielectric layer CMP process. In order to achieve the above and other objectives of the invention, a wafer outer edge exposure process is provided for a wafer, the wafer includes a substrate, and the process is to form a nitrided sand layer on the substrate first. Then, a photoresist layer is formed on the nitrided sand layer. Then, a photomask is provided, the photomask includes a square hollow pattern. Then, the photomask is used for light The first exposure step of the layer is to expose the photoresist layer on the outer edge of the wafer. Then, another photomask is used to perform the light on the inner periphery of the wafer 4 -ϋ ^^ 1 ^^ 1 «^ n ----- -I-----1 IT -------- ^^ 1 ^^ 1 UK--* -fl (Please read the precautions on the back before filling this page) This paper size applies Chinese national standards ( CNS > A4 specification (2 (0 X 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs D Beige Consumer Cooperative A7 4300twf.Q〇c / G03 B7 5. Description of the invention (]) The second exposure step of the resist layer. Thereafter, a development process of the photoresist layer is performed to form a photoresist pattern. Then, using a photoresist pattern as an etching mask, uranium is etched into the silicon nitride layer to form a patterned silicon nitride layer, and the silicon nitride layer on the outer edge of the wafer is removed. Then, using the patterned silicon nitride layer as a mask, the substrate is etched to form a trench in the substrate, and a portion of the substrate on the outer edge of the wafer is removed. Then, an oxide layer is formed on the substrate to cover the patterned silicon nitride layer. Then, using the patterned silicon nitride layer as an end point, a chemical mechanical honing process of the oxide layer is performed. By applying the photomask provided by the present invention, problems such as exposure errors caused by the CMP process of the dielectric layer, and silicon nitride residue caused by the CMP process of shallow trench isolation can be solved. The present invention does not have other objects or advantages, and is not described in detail here. * It can be shown in the process of implementing the present invention and will be described in the embodiments. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 FIG. 2 is a schematic plan view of a wafer of an integrated circuit; FIG. 2 is a schematic sectional view of a part of a wafer according to the II-II section of FIG. 1; FIG. 3 is a schematic sectional view of a shallow trench isolation flat structure; Figures 4A to 4G are schematic cross-sectional views of a wafer outer edge exposure process according to an embodiment of the present invention; and Figure 5 is a schematic plan view of a wafer according to Figure 4A. 5 This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 〇 X 297 mm): ~ I Binding β (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 1.500 A7 4 3 〇 0 twf. D 〇. 2 / W. 37 V. Description of the invention (4) Marking description of drawings: 100, 500: wafer] 02, 3 02, 402: wafer inner circumference 104, 304 '404: wafer outer edges 200, 300, 400: substrate 102a' 302a edge region 206a: wire 206b: metal layer 208: dielectric layer 3 06: oxide layer 3 08, 406: silicon nitride layer 404a: inclined surface 4 0 6a: patterned nitride layer 408: photoresist layer 410, 420: light source 412, 422: photomask 424: photoresist pattern 426: trench 4 2 8: oxide layer 428a: oxidation Plug (element isolation structure) 412: Photomask (virtual photomask) 502: Hollow square pattern 504a, 504b, 504c: Example of dotted frame (please read the precautions on the back before filling this page) The standard is applicable to China National Standard (CNS) A4 specification (2〗 0X297 mm) ^ 1 ^ 530 A7 4 3 0 0 twf. Dcc / 〇〇8 B7 Explanation (t) One of the features of the present invention is to remove the nitrided sand layer on the outer edge of the wafer, so that the subsequent oxide layer formed on the outer edge of the wafer can be lower than the oxide layer formed on the inner periphery of the wafer, or The oxide layer on the outer edge of the wafer will not remain after CMP. Please refer to FIG. 4A, wherein the left side of the dotted line indicates the wafer inner circumference 402, and the right side of the dotted line indicates the outer edge 404 of the wafer. First, a substrate 400 is provided, and a silicon nitride layer 406 and a photoresist layer 408 are sequentially formed on the substrate 400. Then, a light source 410 and a photomask 412 are used to perform the exposure step of the photoresist layer 408 on the outer edge 404 of the wafer. This exposure step can be performed using a relatively inexpensive exposure machine, or an exposure machine with a lower resolution. These comparisons are relative to the manufacturing process of wafer inner circumference 402. Referring to FIG. 4B, using another light source 420 and a photomask 422, an exposure step of the photoresist layer 408 on the wafer inner periphery 408 is performed to expose a desired trench pattern. Please refer to FIG. 4C. After the development process, the desired photoresist pattern 424 is completed. Please refer to FIG. 4D, using a photoresist pattern (424C in FIG. 4C) as an etching mask 'etch the silicon nitride layer (406 in FIG. 4C) to form a patterned silicon nitride layer 406a' And the silicon nitride layer 406 on the wafer outer edge 404 is removed. After that, the photoresist pattern 424 is removed. Referring to FIG. 4E, the patterned silicon nitride layer 406a is used as an etching mask 'to anisotropically etch the substrate 400 to form a trench 426 in the substrate 400, and a portion of the substrate 400 on the outer edge 404 of the wafer is removed. Please refer to Figure 4F. An oxide layer 428 is formed on the substrate 400 to cover nitrogen 7 (please read the precautions on the back before filling this page),-° Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Rate (CNS) A4 is now available (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
411500 A7 4 3 0 0 r. w f . d 〇 c 3 15 B7 五、發明説明（6 ) 化石夕層406a。 請參照第4G圖，以氮化矽層406a爲終點，進行化學 機械硏磨製程，藉以完成元件隔離結構428a，也就是氧化 插塞428a =因爲不具有氮化矽層的晶圓外緣404，其圖 案密度較晶圓內圍402的圖案密度低，所以在進行硏磨 的時候，晶圚外緣404會遭受較多的硏磨，而略低於所 形成的氧化插塞428a表面。雖然這度差會造成一 個傾斜表面404a，但是這個傾斜表面並非出現在具 W^\ 有氮化矽層406a的晶圓內圍4〇2，而^’出\現在沒有氮化 矽層的晶圓外緣404。換句話說，晶圓402氮化矽 層上方的氧化層406a將被去除，不會有窖靠近外緣的 氮化矽層上方氧化層沒有去除等情事發生。 特別注意的是，使晶圓外緣略低於所形成的氧化插塞 表面，不但可以改善習知靠近外緣的氮化较層上方氧化 層沒有去除等問題，還有助於改善後續金屬內連線製程 中，介電層在實施CMP製程之後，會在晶圓內圍靠近外 緣的邊緣區域發生突起等問題。 第5圖繪不根據第4 A圖，一種晶圓5 0 0俯視結構不 意圖，用以說明晶圓外緣曝光用光罩的示意結構及其使 用情形。這個俯視圖的4A-4A剖面示意圖即爲第4A圖。 請同時參照第5圖與第4A圖，此光罩412具有一個中空 方形圖案502，稱之爲虛擬光罩（virtual mask)，可適用晶 圓外緣404中各個不同區域。這些不同區域之光罩對準方 式如圖中幾個虛線框格504a、504b、504c所示範，只要 S (請先閱讀背面之注意事項再填寫本頁) 本紙浪尺度適用中國國家標準（CNS > A4規格（2ί〇Χ297公釐） 經濟部智慧財產局員工消費合作社印製 4H50U Α7 4300 twf . doc / 008 gy 五、發明説明（7 ) 將此虛擬光罩412的邊緣或直角對準晶圓內圍402與外緣 404的邊界或直角，即可完成對準。根據這些示範可知， 利用一個這種具有中空矩形圖案502的光罩，即可曝開所 有晶圓外緣404的光阻層（未繪示）。 此外，必須注意的是，晶圓外緣的曝光步驟並非限定 於在曝晶圓內圍之前完成。相反地，外緣的曝光步驟也可 以在曝晶圓內圍之後實施，端視不同製程的需要而定，並 不影響本發明之精神。 由上述說明可知，本發明至少具有優點如下： 1. 關於介電層之CMP製程導致曝光失誤，以及淺溝 渠隔離之CMP製程導致氮化矽殘留等問題，都可 以應用本發明之光罩來解決。 2. 每個晶圓產品的外緣曝光步驟皆可適用同一片本發 明所提出之光罩，因爲這個光罩具有中空方形圖 案。 3. 利用本發明之光罩，搭配較爲廉價的曝光機，或者 解析能力較低的曝光機來進行晶圓外緣的曝光步 驟，可避免圖案效應所引發的諸多製程問題。其中， 這個曝光步驟可在曝晶圓內圍之前，或者之後來實 施。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾。尤其本發明尙有其 他目的或優點，在此並未盡述，可於實行本發明的過程中， 9 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2 i 0 X 297公釐） 3 0 0· 411500 A7 B7 五、發明説明)或者於本發明後附之申請專利範圍各構件及其結合中，顯 示出來。因此本發明之保護範圍當視後附之申請專利範圍 所界定者爲準= (請先閱讀背面之注意事項再填寫本頁) 装- 經濟部智慧財產局員工消費合作社印製 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐）411500 A7 4 3 0 0 r. W f. D oc 3 15 B7 V. Description of the invention (6) Fossil evening layer 406a. Referring to FIG. 4G, a chemical mechanical honing process is performed with the silicon nitride layer 406a as the end point to complete the element isolation structure 428a, that is, the oxide plug 428a = because the wafer outer edge 404 does not have a silicon nitride layer, Its pattern density is lower than the pattern density of the wafer inner periphery 402. Therefore, when honing, the outer edge 404 of the crystal haze will suffer more honing, which is slightly lower than the surface of the formed oxide plug 428a. Although this difference will cause an inclined surface 404a, this inclined surface does not appear on the inner periphery of the wafer with a silicon nitride layer 406a, and there is no crystal of the silicon nitride layer. Circle outer edge 404. In other words, the oxide layer 406a above the silicon nitride layer of the wafer 402 will be removed, and no incidents such as the oxide layer above the silicon nitride layer near the outer edge will not be removed. Special attention is to make the outer edge of the wafer slightly lower than the surface of the formed oxide plugs, which can not only improve the problem of the oxide layer above the conventional nitrided layer near the outer edge, but also help improve the subsequent metal In the connection process, after the CMP process is performed on the dielectric layer, protrusions and the like occur in the edge region of the wafer inner periphery near the outer edge. FIG. 5 is not based on FIG. 4A, and a 500 ° top view structure of the wafer is not intended, and is used to explain the schematic structure of the photomask for exposing the outer edge of the wafer and its use. The schematic 4A-4A cross-sectional view of this top view is Figure 4A. Please refer to FIG. 5 and FIG. 4A at the same time. This mask 412 has a hollow square pattern 502, which is called a virtual mask, and can be applied to different regions in the outer edge 404 of the wafer. The alignment of the masks in these different areas is shown in the dotted boxes 504a, 504b, and 504c in the figure. As long as S (please read the precautions on the back before filling this page) The standard of this paper applies to Chinese national standards (CNS > A4 specification (2ί297 × 297 mm) 4H50U printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy 4H50U Α7 4300 twf .doc / 008 gy 5. Description of the invention (7) Align the edge or right angle of this virtual photomask 412 to the wafer Alignment can be completed at the boundary or right angle of the inner periphery 402 and the outer edge 404. According to these demonstrations, using a photomask with a hollow rectangular pattern 502 can expose the photoresist layer of all wafer outer edges 404 (Not shown). In addition, it must be noted that the exposure step of the outer edge of the wafer is not limited to be completed before the inner periphery of the wafer is exposed. On the contrary, the exposure step of the outer edge can also be performed after the inner periphery of the wafer is exposed. It depends on the needs of different processes and does not affect the spirit of the present invention. From the above description, it can be seen that the present invention has at least the following advantages: 1. The CMP process of the dielectric layer causes exposure errors and shallow trench isolation. The problem of silicon nitride residue caused by the CMP process can be solved by applying the mask of the present invention. 2. The outer edge exposure step of each wafer product can be applied to the same mask of the present invention because of this The photomask has a hollow square pattern. 3. The photomask of the present invention is used in combination with a relatively inexpensive exposure machine or an exposure machine with a lower resolving power to perform the exposure step of the outer edge of the wafer, which can avoid a lot of effects caused by the pattern effect. Process issues. Among them, this exposure step can be implemented before or after the wafer is exposed. Although the present invention has been disclosed as above with the preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art, in Various changes and modifications can be made without departing from the spirit and scope of the present invention. In particular, the present invention has other purposes or advantages, which are not described in detail here. In the process of implementing the present invention, 9 (Please read first Note on the back, please fill in this page again) This paper size applies the Chinese National Standard (CNS) Λ4 specification (2 i 0 X 297 mm) 3 0 0 411500 A7 B7 V. Description of the invention) or After the invention of the scope of the appended patent application and their respective binding member, the splayed. Therefore, the scope of protection of the present invention is subject to the definition of the scope of the attached patent application = (Please read the precautions on the back before filling this page). Packing-Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. China National Standard (CNS) A4 specification (210 × 297 mm)