TW538266B - Active matrix array substrate and its manufacturing method - Google Patents

Abstract

An active matrix array substrate having active elements aligned in matrix, and more than one scanning line and data line for driving the active elements. Each scanning line is connected to a common scanning bus through a scanning line test resistance, and each data line is connected to a common data bus through a data line test resistance. Each data line is configured with a metal multilayer, and each scanning line test resistance and data line test resistance are configured with a lowest metal layer of this metal multilayer. With this configuration, electrostatic breakdown between a scanning line 4 and data line 5 or neighboring data lines 5 during the manufacturing process is preventable. Accordingly, an active matrix array substrate and its manufacturing method which delivers good yields are achieved.

Description

538266 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention relates to the field of active matrix array substrates, and in particular to such an array used in a display panel of a liquid crystal display device for information processing and the like Production method. BACKGROUND OF THE INVENTION Liquid crystal display devices (abbreviated as LCD) have been widely used in video display devices including OA terminals and televisions. In particular, LCDs with high display performance, such as LCDs using thin film transistors, use an active matrix array substrate in which a plurality of active elements are arranged. Generally, such an active matrix array substrate has some electrical defects in its final manufacturing stage. To this end, a test resistor is formed on the active matrix array substrate. An earlier-published patent case No. H8-101397 discloses an active matrix array substrate formed with a resistor and a method of manufacturing the same. Conventionally, as shown in FIG. 3, the pixel unit 1 is composed of a pixel electrode 3 and a TFT 2. A plurality of pixel units 1 are arranged in a matrix. The plurality of scanning lines 4 and the plurality of data lines 5 that scan each TFT are located between the pixel early cells. Each scan line 4 is connected to a common scan bus 10 via a scan test resistor 12, making it possible to perform an electrical inspection. Each data line 5 is connected to a common data bus 11 via a data line test resistor 13. A scanning line input pad 6 and a data line input 塾 8 are located on the scanning line 4 or the data line 5, respectively. These rotations ---------------------- Order i II (Please read the notes on the back before filling this page)

n n I Paper size _ t _ Specifications (21G x 297 mm y -4- 538266

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (2) The pad is used for electrical inspection, and is used to input drive signals to scan lines and data lines after they are finally connected to an external circuit (drive IC). The common scan pad 14 and the common data pad 15 for inspection are located at the tail ends of the common scan bus 10 and the common data bus 11, respectively. FIG. 3 shows a conventional active matrix array, which is manufactured through the following steps: forming a metal layer to generate the scan lines; processing the patterns of the scan lines; forming three layers, including a gate Electrode insulation layer, a-Si layer (a-Si: amorphous-Si), and low-resistance silicon layer; the pattern of the core layer / low-resistance a_Sl layer is processed to form a-Si island of the TFT; Forming a contact window on the gate insulating layer; forming a metal line to generate data lines; processing the patterns of the data lines; etching the channel (by removing the exposed low-resistance a-Si layer); forming a protective insulation Layer; processing a contact window on the protective insulating layer; forming an IT0 (indium tin oxide) layer for a pixel electrode; and processing a pattern of the pixel electrode. Since it is preferable to have a sheet resistance value, the scan line test resistor 12 and the data line test resistor 13 are formed using the ITO layer for forming the pixel electrode 3. In each of the above steps, it is important to always electrically connect all the data lines 5 and the common data line ii at least after the processing step of the data line pattern 'so that even if the data line is charged during processing, Can prevent the occurrence of local abnormal voltage. This ITO resistor is formed between the data line 5 and the common data bus i i in the last step of the fabrication of the array substrate. Therefore, until the final step, it still needs to pass some other components to adapt the data line 5 and the common paper size to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) — · ------- ---------- Order --------- (Please read the precautions on the back before filling out this page) 538266 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the invention description (according to w Line 11 is electrically connected. Therefore, when a Si island for a TFT is generated, a process for connecting the data line 5 and the common data bus is also formed in the processing step of the a_Si layer / low resistance a-Si layer pattern. An a_si island. However, the resistance of the 'a-Si island is increased after removing the low-resistance core on the surface during the etching step (removing the exposed low-resistance a-Si layer) step. This causes static electricity Insufficient discharge of the charge and reduction of the potential generated in the data line leading to the common data bus. In particular, when dry etching is used for channel | worming, the data line is due to the use of plasma in dry etching. It is charged to a high potential, which causes serious problems. The object of the present invention is to improve An active matrix array substrate and a method for manufacturing the same can prevent a decrease in yield due to electrostatic breakdown and achieve a high yield, and can perform electrical inspection. The active matrix array of the present invention includes a plurality of arrays arranged in a matrix array. An active element on the outline, more than one scan line for driving the active element; more than one data line for providing image data to the active element; a common scan bus; a common data Bus; most scan line test resistors that connect each scan line to a common scan bus; and most data line test resistors that connect each data line to a common data bus. Each data line and common data bus are The multilayer structure of a plurality of metal layers is configured, and each scan line test resistance and data line test resistance data is configured by removing at least the uppermost layer of the multilayer structure. This configuration can prevent the scan lines and Electrostatic breakdown between data lines or between adjacent data lines, and makes the manufacture of active matrix arrays This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------------------- Order --------- (Please (Please read the notes on the back before filling out this page) 538266

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the δ-resistance measured by the star mother can only be composed of the lowest layer of the multilayer metal structure. The active matrix array substrate of the present invention further includes a plurality of non-polar electrodes made of the same material with the same level as each data line; a protective insulating layer covering each of the drain electrodes; and a plurality of Pixel electrodes on the protective insulating layer. Each pixel electrode is connected to each drain electrode through the contact window provided on the insulating layer. The suitable structure provides an active matrix array with high aperture ratio pixels on the substrate. The present invention provides the active matrix array substrate, in which more than one data line has a multilayer structure including an upper layer made of A1 and a lower layer made of &, Ti, w, Mo, or Ta. This can reduce parasitic resistance, and can be realized in a high-quality daylight surface with low flicker or crosstalk in a liquid crystal display device. The method for manufacturing an active matrix array according to the present invention comprises: (A) forming a plurality of active elements in a matrix arrangement on one surface of a substrate; (B) forming a plurality of scan lines and one on the substrate A common sweep line, each scan line is connected to the scan line via a first temporary connection; (C) forming a plurality of data lines for supplying image data to a plurality of active element, one connected to the plurality of data lines Common data lines' and by depositing and patterning at least two metal layers, each of the plurality of scan lines is combined with the common scan line and the gate of the line (Please read the precautions on the back before filling in this Page) Order ----- 1111 A7

538266 V. Description of the invention (5) A plurality of scan line bridges forming a first connection to form the data line, the common data bus, and the scan line bridge as a multilayer structure including a plurality of metal layers, the plurality of metal layers Including an upper metal layer and a lower metal layer; (D) truncating the first temporary connection between the 5H common scan bus and each scan line; and (E) by passing each data adjacent to the common data bus In one part of the line and from each scan line bridge, one of the metal layers other than the lower metal layer is removed to form a test resistance connecting each data line and the common data line and a connection between each scan line and the common scan Test resistance of the bus. This structure prevents electrostatic breakdown between scan lines and data lines or between adjacent data lines. FIG. 1 is a partially unintended plan view for describing a process in which half of the process f is performed in a method for manufacturing an active matrix array substrate according to a preferred embodiment of the present invention. Figures 2A to 2E are schematic partial plan views for describing each step in a method of manufacturing an active matrix array substrate according to a preferred embodiment of the present invention. Fig. 3 is a circuit diagram of an active matrix array substrate of the present invention and the prior art. DESCRIPTION OF THE PREFERRED EMBODIMENT An active matrix array substrate and its manufacture according to a preferred embodiment of the present invention are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Please read the note on the back first咅? Please fill in this page again for matters) ------ Order --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 538266

The method of printing by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is described in Figures i, 28 to 2E, and Figure 3 below. In all drawings, similar reference numerals indicate similar components. The numbers of each element arranged in the matrix are only given to the representative parts in the figure, and the others are omitted to avoid confusion and complicate the figure. The active matrix array in the preferred embodiment of the present invention has the same final circuit as the conventional technique of FIG. Next, referring to FIG. I, two of a plurality of TFTs 2 and pixel electrodes 3 are shown in the figure. Each electrode is connected to the drain electrode 24 of the TFT 2 and arranged in an array on a glass substrate (not shown). . The figure also shows a scan line 4 that scans each TFT 2 that supplies image data to the source electrode 23 of each TFT 2 and the gate electrode 20 of the data line 5. Each TFT 2 includes a gate electrode 20, a core island, a source electrode 23, and a drain electrode 24. Each scan line 4 is connected to the common scan bus 10 via the scan line test resistor 12, and each data line 1 is connected to the common data bus u via the data line test resistor 13. Each of the drawing lines 4 has a scanning line output pad 6, and each data line 5 has a data line input pad 8. The common scan bus 10 has a common scan pad U, and the common data bus U has a common data pad 15. Electrical inspection is carried out by detecting from external ports 6, 8, 14 # 15. A detail different from the conventional technology in the preferred embodiment is that the data line 5 is a multilayer metal conductor, and the scan line test resistor 12 and the data line test resistor 13 are formed by a part of a multilayer metal structure. Instead of the simple IT0 layer in the conventional technology. Reference is made to Figures 2A to 2E, which describes the generation of an 具有 @ 0 (CNSU7ii72T〇χ 297 ^ Γ)-~ _____ with a multilayer metal conductor and a resistor on a substrate according to a preferred embodiment of the present invention .-- ------ ^ --------- ^ 9. (Read the precautions on the back before filling out this page before filling out this page} 538266 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (Manufacturing method of source matrix array. First, as shown in FIG. 2A, a 350-nm-thick AlZr alloy (Zr: 1 atomic% thick) layer is formed on a glass substrate, and then etching is performed to form a scan line 4. TFT gate electrode 20, scan line input pad 6, common scan bus 10 and common scan pad 14. Preferably these are formed at the same time. The scan line 4 and the common scan pad 14 are connected by a temporary scan line path 4a. Connected. The temporary scan line connection path is removed during subsequent processing, but it is also used to prevent electrostatic charges from being built up inside the array. Pad 4b is a pad connected to scan line bridge 25 in subsequent processing steps. Next, Plasma-assisted chemical vapor deposition method p_CVD method) Three layers are sequentially formed on the entire surface. One is to form a TFT gate insulating layer with 1 ^ layer. An a_Si layer is to form a channel layer and a low-resistance core layer is used to hold the TFT source. Contact with the drain electrode. After forming these layers, as shown in FIG. 2B, the a-Si layer and the low-resistance a_Si layer are etched into an island shape to form an a-Si island 21, which is The main components of the TFT. Next, as shown in FIG. 2B, a part of the gate insulating SiNx layer surrounding the temporary scan line connection path and a part of the SiNx layer on the upper part of the scan line bridge are removed to insulate the gate A contact window 22 and 22 is generated on the layer. Next, a 100 nm thick Ti layer and a 300 nm thick A1 layer are sequentially formed to form a multilayer metal layer. The multilayer metal layer is subsequently subjected to dry etching to Form the data line 5, the data line connection pathization, the source electrode 23, the data line input pad 8, the common data bus u, the common data line 15, the drain electrode 24 and the scan line bridge 25, and lightly occupy # 门 士 孕A good line is formed at the same time, if this paper size applies Chinese national standards CNS) A4 size (210 x 297 mm) (Please read the note on the back? Matters before filling out this page} ----- Order ---------] Ί0- 538266 A7 B7 V. Invention Explanation (8 shown in FIG. 2C.) In the etching step, the temporary scan line connection channel exposed through the contact window 22 of the gate insulating layer is also removed. The common data bus 11 and the data line 5 are formed by Subsequently, the data line connection path 5a of the data line test type resistor 13 is connected. The scan line bridge is also processed later to form the scan line test resistance 丨 2. However, in this step, after the temporary scan line connection path 4a is removed, the scan line bridge 25 continues to connect the scan line 4 and the common scan bus 10. The etching of the data line 5 and the removal of the temporary scanning line connection path can be performed in the same step. In the present preferred embodiment, the data line 5 and the temporary scanning line connection path 4a are made of A1, and are therefore etched simultaneously. However, even if they are made of different materials, they can be etched away by changing the etch gas and etch solution. After P, the low-resistance a_si layer in the a-Si island 21 between the source electrode 23 and the non-electrode electrode 24 is removed to form a channel of the TFT 2 (FIG. I). Subsequently, a part of the upper layer of A1 on the scan line bridge 25, the data line connection path 5a, and the non-electrode 24 is removed to leave only the lower layer. As shown in Fig. 2D, this forms a scan line test resistor 12, a data line test resistor 13, and a drain contact electrode 24a. The A1 layer on the drain electrode 24 is removed because the underlying Ti layer is preferably used to make contact with the ιτο pixel electrode at a low resistance which will be described later. The upper A1 layer is used to reduce the resistance value of the S data line 5 to prevent signal delay. Next, a siNx layer is formed by the p-CVD method to produce the protective insulating layer. Subsequently, as shown in FIG. 2E, the scan line input pad 6, the data line input pad 8, the common scan pad 14, the common data pad 15, and the paper-scale fine hat family standard (CNS) A4 specification (210 X (297 public directors) (Please read the notes on the back before filling out this page) -------- Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-11- 538266 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (contact the protective insulation layer of electrode 2 as above to create contact windows 26 via these protective insulation layers respectively. As shown in Figure 2E, on the entire surface After forming a HKhnn thick indium tin oxide (IT0) layer, the pixel electrode 3 connected to the TFT drain contact electrode 2 乜 via the contact window 26 on the insulating insulating layer is formed to make the active electrode. Matrix array substrate. As mentioned above, this preferred embodiment relates to an active matrix array using IT0 as a pixel electrode for a transparent LCD. If ITO is replaced with a metal such as 丨 and α§, Then the pixel electrode can also be used as a reflector, and

Achieving an active matrix array for reflective LCD. In the case of reflective [CD], a test resistor cannot be formed by the traditional method described in the background of the invention above, because ITO is not used here. Therefore, the present invention demonstrates greater efficiency in an active matrix array of a reflective LCD. The pixel electrode may also be formed in a step before forming a scan line or a data line. In the preferred embodiment, the pixel electrode is formed on a protective insulating layer so that it has an enlarged aperture ratio as much as possible. In one embodiment, the scan line 4 and the common scan bus 10 are connected by the scan line bridge 25 in the step of forming a TFT channel by removing the low-resistance a-Si layer. The data line 5 and the common data bus 11 are connected by a data line connection path 5a. This prevents static breakdowns. If an amorphous Si island is used instead of the data line connection path 5a when connecting, as in the conventional technology, after the low-resistance a-Si layer is removed, the resistance of the island has tens of megohms. . The multilayer structure of Ti and Al of the present invention has a resistance value of only a few hundred ohms. This prevents the paper size from applying the Chinese National Standard (CNS) A4 (210 X 297 mm) -12- -------- ^ ---------. (Please read the Note: Please fill in this page again) 538266 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (10) The establishment of the destructive electrostatic charge due to electricity crossing in the dry processing is stopped. The electrical inspection system requires the scanning line test resistor 12 and the data line test resistor 13 to be several tens of kiloohms. This resistance level can be obtained by removing only the A1 layer above the scan line bridge 25 and the data line connection path 5a and leaving a high resistance Ti. Gate In the above description, the scan line 4 and the gate resistor 20 are made of Ai-Zr alloy. Metals with high melting points, such as cr, Ta, etc. can also be used. Multi-layer metal structures such as Ti / Al / Ti can also be used. For LCDs with large display areas or extremely high display densities, the M system metal with low resistance is effective in preventing degradation of the daytime quality due to signal delays in the scanning lines. In the preferred embodiment, the data lines 5 and the scan line bridges 25 are formed in a multilayer structure formed of Ti and Al. However, any material with a sufficiently low resistance without delaying the data signal can also be used in the upper layer of the multilayer structure, and any material with a suitable resistance value for each test resistance used to achieve inspection and good point contact with ITO The material can also be used in the lower layer. The lower layer may be made of a metal having a high melting point, such as Cr, W, Mo, or Ta, and the like, and the upper layer may be made of an Al and one or more metal alloys having a high melting point. The metal multilayer structure may also include two or more layers, and each of the test resistances for inspection is provided by these metal layers except for the uppermost layer. The preferred embodiment uses a TFT as the active element. However, other non-linear end elements' such as MIM may be used. The present invention includes a common data bus, which is composed of multiple metal layers (please read the precautions on the back before filling this page) --------- Order ---------% i.

538266 A7 B7 V. Description of the invention (η) The data line formed by the lowest layer of the structured data line is electrically connected to more than one data line, and the common scan bus is tested by scan lines made of the same material The resistor is electrically connected to more than one scan line as the lowest layer of more than one data line. This makes it possible to prevent electrostatic breakdown between each scan line and the data line or adjacent data lines. Therefore, the present invention provides an active matrix array substrate and a manufacturing method which has a better yield and can be electrically inspected. Component reference table 1. Pixel unit; 2. TFT; 3. Pixel electrode; 4. Scan line; 4a. Temporary scan line connection path; 4b. Scan line bridge; 5. Data line; 5a. Data line connection Path; 6. Scan line input pads; 8 · Data line input pads; 10 · Common scan bus; 11 · Common data bus; 12. Scan line test resistance; 13 · Data line test resistance; 14 · Common scan pad; 15 · Common data pad, · 20 · Gate electrode; 21 · a-Si island; 22 · Contact window of gate insulating layer; 23 · Source electrode; 24 · Drain electrode; 24a. Drain contact electrode; 25 · Scan line bridge; 26. Contact window for protective insulation. (Please read the notes on the back before filling out this page) -------- Order --------- · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs

Claims (1)

538266 范围 利 ^ ι ^ ψ · Patent Application No. 089105783 Revised Patent Range 丨 An active matrix array, which includes: Date of revision: November 1991 Most of the substrates are moment __Active Components; f scan lines for scanning the plurality of active components; most scan lines for providing image data to the plurality of active components; according to a common scan bus; a common data bus; most scan line tests A resistor 'which is used to connect each of the plurality of scan lines to the common scan line; and a plurality of data line test resistors' which are used to connect each of the data lines to the common data bus; wherein, each The data line and the common data bus include a composite multilayer structure including a metal layer, a composite multilayer structure having an upper metal layer and a lower metal layer, and each of the plurality of scan line test resistors and the plurality of data line test resistors Each of them contains at least the upper metal layer structure. > 2 · If the scope of patent application is the first! In the active matrix array of the item, each of the plurality of scan line test resistors and each of the data line test resistors include only one metal layer, and the metal layer is the lower metal layer. 3. As the active matrix array of the first patent application scope, it also includes a plurality of drain electrodes, which are compatible with the use and include the and the miscellaneous ----- (Please read first Note on the back ¾ refill this page), one-T— Φ This paper size applies the Chinese National Standard (CNS) A4 specification (21〇297) Each data line simultaneously covers a protective insulating layer of each drain electrode; and a plurality of pixel electrodes formed on the protective insulating layer; wherein each of the plurality of pixel electrodes is routed through the channel. ::: The contact window in the insulating layer and each of the active matrix arrays of the drain electrode 如 as in item 3 of the patent application scope are connected to the 亥 ^ 邛 of one of the plurality of pixel electrodes. Remove the upper layer of the multilayer structure of each drain electrode. For example, the active matrix array of claim 3, wherein the plurality of pixel electrodes include ITO. For example, in the active matrix array of item 3 of the Shenqing Special Project, wherein the plurality of pixel electrodes include a metal selected from the group consisting of A1 and Ag, and wherein the plurality of pixels f are extremely reflective of human radiation. Shoot. For example, the patented active matrix array of item 1 of patent $ 1L®, wherein the plurality of active elements are thin film transistors. For example, the active matrix array of claim 2 of the patent scope, wherein the multilayer structure includes an upper layer made of A1 and at least one metal selected from the group consisting of heart, dimple w, Mo, and Ta The lower metal layer 109. The active matrix array according to item 1 of the patent application, wherein each of the plurality of scanning lines is an A1 alloy. 10 · —A method for manufacturing an active matrix array, comprising: 538266 A8 B8 C8 D8 VI. Patent application scope (A) Form a plurality of active elements in a matrix arrangement on one surface of a substrate; (B) Form a plurality of scan lines and a common scan line on the substrate, Each scan line is connected to the scan bus via a first temporary connection; (C) forming a plurality of data lines for providing image data to a plurality of active elements, and a common data connected to the plurality of data lines Bus lines, and scan line bridges forming a second connection between each of the plurality of scan lines and the common scan bus by depositing and patterning at least two metal layers to form the data lines, the The common data bus and the scan line bridge serve as a multi-layer structure including a plurality of metal layers, the plurality of metal layers including an upper metal layer and a lower metal layer; (D) truncating the common scan bus and each scan line A first temporary connection; and (E) by removing one of the metal layers other than the lower metal layer from a portion of each data line adjacent to the common data bus and from each scan line bridge To form a test resistor connected to each of the data lines and common data lines, and a test resistor connected to each scan line and a common scan bus. 11. The method of claim 10, wherein the plurality of scan lines, the common scan bus, and the first temporary connection are formed simultaneously. 12. The method according to item 11 of the patent application scope, wherein in step (C), the patterning of all data lines, common data buses, and scan line bridges occurs simultaneously. This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page)-, τ ·, patent application scope u. Such as patent application scope 10 Λ. AA Bei The method, wherein the step (c) and truncation of the plurality of pieces of data are performed, and the step (D) of the first temporary connection is performed in an early step. 14. The method as claimed in claim 10, wherein in step (E), the upper metal layer is removed to form the test resistor. 15. The method according to the scope of the patent application, wherein the plurality of active elements are thin film transistors. 16. The method according to item 14 of the application, wherein the multilayer structure includes an upper layer made of A1 and a lower layer made of at least one metal selected from the group consisting of Cr, Ti, w, and Mo * Ta. C Please read the precautions on the back before filling in this page), I t This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)